A PCB substrate

Abstract

This application provides a PCB substrate, comprising: a substrate body; an irradiation hole penetrating the substrate body; multiple chip test areas of different sizes nested within the substrate body, surrounding the irradiation hole; each chip test area including a die-attachment area and a gold finger area surrounding the die-attachment area; and a breakable structure disposed between adjacent chip test areas, the strength of which is less than the strength of the substrate body. In use, a test laser beam can directly irradiate the bottom of the chip through the irradiation hole, then penetrate the silicon layer to irradiate the chip's well region, avoiding excessive laser energy loss inside the chip, improving the accuracy of laser beam irradiation, and thus improving the accuracy of laser-simulated single-particle irradiation damage assessment tests. When testing chips with larger dimensions is required, smaller chip test areas can be removed, increasing the area of ​​the irradiation hole.

Description

Technical Field

[0001] This application belongs to the field of packaging and testing technology for microelectronic devices, specifically, it relates to a PCB substrate suitable for irradiation damage assessment tests on chips of various sizes. Background Technology

[0002] The size and variety of chip products produced in the current technology are increasing, and the demand for rapid chip packaging and testing is also growing.

[0003] Due to the variety of chip sizes, different PCB substrates (i.e. printed circuit boards) of different sizes are generally required before testing, which reduces the efficiency of testing.

[0004] On the other hand, to ensure the reliability of chips under special operating conditions, laser-simulated single-particle irradiation damage assessment tests are required. These tests primarily use lasers in ground-based laboratories to simulate single particles in space and evaluate the radiation effects on integrated circuits. The challenge lies in the fact that integrated circuit chips typically have one or more layers of metal wiring on their surface. This metal wiring blocks part of the laser beam, limiting the laser beam's accurate irradiation of the chip's well region, making it difficult to quantitatively study the energy loss of the laser within the integrated circuit.

[0005] To address the aforementioned issues, the conventional approach in the prior art is to use chemical or physical means to remove the back material of the packaged chip (including the substrate or package shell used during chip packaging), thereby directly exposing the underlying silicon material of the chip. Then, a laser beam is passed through the back silicon layer of the chip to irradiate the well region of the integrated circuit.

[0006] However, methods that remove back-side material from the chip can damage the chip, affecting the accuracy and reliability of the measured parameters. Therefore, the accuracy and reliability of laser-simulated single-particle irradiation damage assessment experiments need to be improved. Utility Model Content

[0007] In order to solve or improve the problems existing in the prior art, this application provides a PCB substrate that is designed to be able to adapt to a variety of chips of different sizes and to enable the test laser beam to accurately irradiate the well area of ​​the chip without damaging the material on the back of the chip.

[0008] The PCB substrate provided in this application specifically includes: a substrate body; an illumination hole that penetrates the substrate body; multiple chip test areas, which are of different sizes and nested within the substrate body, with the multiple chip test areas surrounding the illumination hole; each chip test area includes a die-attachment area and a gold finger area surrounding the die-attachment area; and a breakable structure disposed between adjacent chip test areas, the strength of which is less than the strength of the substrate body.

[0009] In the aforementioned scheme, the test laser beam can directly irradiate the bottom of the chip through the irradiation hole, and then pass through the silicon layer to irradiate the well region of the chip. This avoids excessive loss of laser energy inside the integrated circuit chip, improves the accuracy of laser beam irradiation, and thus improves the accuracy of laser simulation single-particle irradiation damage assessment test.

[0010] By using the aforementioned easily broken structure with a strength less than that of the substrate body, a semi-connection is formed between multiple chip test areas. When it is necessary to test chips with larger sizes, the smaller chip test area can be knocked off directly to enlarge the area of ​​the irradiation hole. The larger chip can then use the remaining chip test area outside the enlarged irradiation hole to bond with the substrate body and achieve electrical connection.

[0011] Optionally, the substrate body includes at least two insulating layers stacked together, and a metal isolation layer disposed between adjacent insulating layers; the orthographic projection of the metal isolation layer on the surface of the substrate body surrounds multiple chip test areas.

[0012] In the aforementioned scheme, by adding a metal isolation layer between the insulating layers of the substrate body, interference from large abrupt electromagnetic signals caused by dark current generated by the photoelectric effect during the scanning of the back of the chip by the experimental laser can be avoided during the transmission of circuit signals.

[0013] Optionally, at least two insulating layers include a first insulating layer, a second insulating layer, and a third insulating layer; the metal isolation layer includes a first metal isolation layer disposed between the first insulating layer and the second insulating layer, and a second metal isolation layer disposed between the second insulating layer and the third insulating layer; the first metal isolation layer and the second metal isolation layer may have the same or different dimensions and shapes.

[0014] Optionally, the thickness of at least a portion of the fractured structure is less than the thickness of the substrate body at the chip testing area; and / or, the fractured structure includes a single cutout structure or multiple cutout structures spaced apart.

[0015] Optionally, the chip test area is rectangular; the easily broken structure includes a connection structure located at the corner between adjacent chip test areas, and a cutout structure located between adjacent connection structures.

[0016] Optionally, the substrate body includes at least two insulating layers stacked together, and a plurality of metal isolation rings disposed between adjacent insulating layers; the orthographic projections of the plurality of metal isolation rings on the surface of the substrate body respectively surround the irradiation hole and at least a portion of the gold finger region.

[0017] In the aforementioned solution, a metal isolation ring is placed around the chip testing area to shield against sudden electromagnetic field changes in the surrounding environment during chip testing. Simultaneously, the metal isolation ring, along with the aforementioned metal isolation layer, effectively reduces temperature changes in the substrate caused by high-energy laser irradiation, improving the thermal stability of the PCB substrate and ensuring the authenticity and accuracy of the test signals.

[0018] Optionally, metal isolation rings are provided on both the inner and outer sides of certain gold finger areas.

[0019] Optionally, the chip test area is rectangular; the metal isolation ring is a rounded rectangular ring.

[0020] In the aforementioned solution, the rounded corners of the metal isolation ring can prevent the laser from irradiating the metal conductors of the PCB substrate during the laser scanning test chip back process, thus avoiding the sharp discharge effect that would affect the test circuit results.

[0021] Optionally, at least two insulating layers include a first insulating layer, a second insulating layer, and a third insulating layer; the plurality of metal isolation rings include a plurality of first metal isolation rings disposed between the first insulating layer and the second insulating layer, and a plurality of second metal isolation rings disposed between the second insulating layer and the third insulating layer; the plurality of first metal isolation rings have different sizes, and the plurality of second metal isolation rings have different sizes.

[0022] Optionally, it also includes: a plurality of sockets disposed at the edge of the substrate body and extending through the substrate body; a conductor is disposed on the inner wall of the socket, the conductor being electrically connected to a gold finger in at least one gold finger region via a lead; a portion of the lead is located on one surface of the substrate body, and another portion of the lead is located on another surface of the substrate body.

[0023] In the aforementioned scheme, leads are provided on both the front and back sides of the substrate. This method of arranging leads vertically and horizontally not only maximizes the physical distance between adjacent leads, but also allows horizontally adjacent leads on the same side of the substrate to be arranged further apart. This greatly reduces the electrical and thermal interactions between adjacent leads during the testing process, further ensuring the accuracy and reliability of chip test data.

[0024] In summary, when using the PCB substrate provided in this application to conduct laser simulation single-particle irradiation damage assessment tests, the laser can directly enter through the irradiation hole in the center of the PCB substrate and directly irradiate the well region inside the chip through the silicon layer on the back of the chip. This not only avoids the damage caused by removing the substrate or package shell from the back of the chip, but also reduces the energy loss of the laser, making the influence of the laser on the performance of the integrated circuit closer to the theoretical value, the measured electrical parameters more accurate, and the results of the assessment test more accurate.

[0025] After the experiment is completed, the irradiation hole can be sealed directly to complete the encapsulation, thus enabling rapid encapsulation.

[0026] Furthermore, due to the presence of a breakable structure with a strength less than that of the substrate body, the irradiation hole can be enlarged. Combined with multiple chip testing areas of different sizes, the PCB substrate can accommodate a variety of chips of different sizes to be tested. Attached Figure Description

[0027] Figure 1 This is a top view of the PCB substrate provided in the embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the metal interlayer inside the PCB substrate provided in the embodiments of this application;

[0029] Figure 3 This is a schematic cross-sectional view of each layer of the PCB substrate body provided in the embodiments of this application;

[0030] Figure 4 This is a schematic diagram of multiple chip testing areas and their easily breakable structures in the PCB substrate provided in the embodiments of this application;

[0031] Figure 5 This is a schematic diagram of the metal isolation ring in the PCB substrate provided in the embodiments of this application;

[0032] Figure 6 This is a schematic diagram of the lead connection between the chip test area and the socket in the PCB substrate provided in the embodiments of this application.

[0033] The image is labeled as follows:

[0034] 100: Illumination hole, 200: Chip testing area, 300: Fragile structure, 400: Insertion hole;

[0035] 010: Metal isolation layer, 011: First metal isolation layer, 012: Second metal isolation layer;

[0036] 021: First insulating layer; 022: Second insulating layer; 023: Third insulating layer;

[0037] 030: Metal isolation ring;

[0038] 210: Adhesive area, 220: Gold finger area;

[0039] 410: Terminal block, 420: Lead wire. Detailed Implementation

[0040] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete. The same reference numerals denote the same objects throughout the drawings.

[0041] In the specification of this application, when a region / structure / layer is referred to as being "connected to" other regions / structures / layers, such as "connected to" other regions / structures / layers, the region / structure / layer can be directly connected to or directly coupled to other regions / structures / layers, or there may be an intervening third region / structure / layer; in addition, in the embodiments of this application, "connection" can be a structural connection or an electrical connection, and "adjacent" or "adjacent" means that two regions are connected to each other, or that two regions are directly close to each other (excluding a third party) and separated by a preset distance.

[0042] This application provides a PCB substrate suitable for conducting irradiation damage assessment tests on chips of various sizes. To provide a more complete disclosure of the embodiments, the aforementioned irradiation damage assessment tests are explained below.

[0043] The radiation damage assessment test described in this application is specifically a laser-simulated single-event radiation damage assessment test, which is a test method for evaluating the radiation resistance of semiconductor devices or chips by simulating the irradiation effect of high-energy particles using laser pulses. Its core is to utilize the ionization effect generated by the interaction between laser and materials to equivalently simulate single-event effects (such as single-event upset, single-event latch-up, etc.) in a space radiation environment, thereby verifying the reliability and radiation resistance design of the device.

[0044] When laser photon energy exceeds the semiconductor bandgap (e.g., 1.1 eV for silicon), the photons are absorbed by the semiconductor device and excite electron-hole pairs, simulating charge deposition caused by high-energy particles passing through the conductive material in the chip. By controlling the laser wavelength, energy, and pulse width, the depth and density of charge generation can be adjusted, equivalent to particle irradiation with different LET (linear energy transfer) values. Studies have shown that laser-induced charge deposition is similar to the charge distribution in sensitive regions of devices under heavy-ion irradiation. By establishing a conversion relationship between laser energy and particle LET, the risk of single-event effects can be quantitatively assessed.

[0045] like Figure 1As shown in the figure, the PCB substrate provided by the embodiment of the present application specifically includes:

[0046] A substrate body;

[0047] An irradiation hole 100, the irradiation hole 100 penetrates through the substrate body;

[0048] A plurality of chip test areas 200, the plurality of chip test areas 200 are different in size from each other, and are nested on the surface of the substrate body, and the plurality of chip test areas 200 surround the irradiation hole 100; each chip test area 200 includes a die bonding area 210 and a gold finger area 220 surrounding the die bonding area 210;

[0049] An easily breakable structure 300 is provided between adjacent chip test areas 200, and the strength of the easily breakable structure 300 is less than the strength of the substrate body, and is used to form a semi-connection between adjacent chip test areas 200.

[0050] It is easy to understand that the semi-connection between adjacent chip test areas 200 can also achieve connection, but the strength of the easily breakable structure 300 used to connect adjacent chip test areas 200 is relatively low.

[0051] In a preferred embodiment, the plurality of chip test areas 200 are in a "square with a hole in the middle" shape and are nested layer by layer around the irradiation hole 100.

[0052] In a preferred embodiment, the irradiation hole 100 is a rounded rectangle or a rounded square, that is, a quasi-rectangle or quasi-square with a circular arc transition between adjacent sides.

[0053] Explanatorily, the strength of the aforementioned easily breakable structure 300 is less than the strength of the substrate body. When stress is applied to adjacent chip test areas 200, the easily breakable structure 300 can break prior to other positions of the substrate body, enabling an operator to separate adjacent chip test areas 200 by hand or using simple manual tools. The holes formed by the removed chip test areas 200 and the original irradiation hole together serve as the enlarged irradiation hole 100.

[0054] In this way, when testing chips of different sizes, the size of the irradiation hole 100 can be enlarged by removing the chip test areas 200 of smaller sizes, so as to test chips of different sizes.

[0055] During the experiment, the laser can directly irradiate the bottom of the chip from the irradiation hole 100 at the center of the PCB substrate, and the laser passes through the silicon layer on the back of the chip and irradiates the well region, thereby avoiding excessive loss of laser energy inside the integrated circuit chip, improving the accuracy of the laser beam irradiation, and further improving the accuracy of the laser simulation single particle irradiation damage assessment experiment.

[0056] The aforementioned embodiments can solve the problem that the laser beam can not accurately irradiate the chip well area due to one or more layers of metal wiring on the chip surface. At the same time, they can also avoid the problem that the removal of excess material by chemical or physical methods in the existing methods may damage the integrated circuit chip and cause inaccurate measurement parameters.

[0057] In an embodiment, such as Figure 4 As shown, the bonding area 210 is used to bond the chip to be tested; the gold finger area 220 surrounding the bonding area 210 is provided with multiple gold fingers (conductor connection terminals), which are used to connect with the pads (PADs) of the chip to be tested via bonding wires. The distances between the inner edges of the multiple chip test areas 200 and the illumination hole 100 are different, and in the direction from the illumination hole 100 toward the edge of the PCB substrate, the distances between the inner edges of the multiple chip test areas 200 and the illumination hole 100 increase sequentially, and are arranged to surround the illumination hole in ascending order.

[0058] In a preferred embodiment, the substrate body includes at least two insulating layers stacked together, and a metal isolation layer 010 disposed between adjacent insulating layers.

[0059] like Figure 2 As shown, the orthographic projection of the metal isolation layer 010 onto the surface of the substrate surrounds multiple chip test areas 200.

[0060] More specifically, the metal isolation layer 010, with the thickness direction of the substrate body as the projection direction and the surface of the substrate body where the chip test area 200 is formed as the projection surface, forms an orthographic projection as shown below. Figure 2 As shown, multiple chip test areas 200 are surrounding the chip.

[0061] In a preferred embodiment, the substrate body is provided with a socket 400 for mounting pins, and the metal isolation layer 010 has a cutout around the socket 400, that is, the metal isolation layer 010 avoids the area around the socket 400.

[0062] Optionally, the material of the metal isolation layer 010 can be a metal such as copper (Cu) or aluminum (Al).

[0063] By adding a metal isolation layer between the insulating layers of the substrate, interference from large abrupt electromagnetic signals caused by the dark current resulting from the photoelectric effect of the laser irradiating the silicon substrate and metal leads of the chip can be avoided during the transmission of circuit signals when the test laser scans the back of the chip outside the irradiation hole.

[0064] On the other hand, the metal isolation layer can minimize the electrical and thermal effects of the laser beam on the PCB substrate and interconnects, ensuring the accuracy and reliability of the test data.

[0065] In a typical embodiment, such as Figure 3 As shown, there are at least two insulating layers, specifically including a first insulating layer 021, a second insulating layer 022 and a third insulating layer 023;

[0066] The aforementioned adhesive area 210 and the gold finger area 220 surrounding the adhesive area 210 are both disposed on the top surface of the first insulating layer 021.

[0067] The metal isolation layer 010 specifically includes a first metal isolation layer 011 disposed between the first insulating layer 021 and the second insulating layer 022, and a second metal isolation layer 012 disposed between the second insulating layer 022 and the third insulating layer 023;

[0068] The first metal isolation layer 011 and the second metal isolation layer 012 may have the same or different dimensions and shapes.

[0069] In such Figure 2 In the top view shown, the first metal isolation layer 011 and the second metal isolation layer 012 both surround multiple chip test areas 200.

[0070] In the foregoing embodiments, the first insulating layer 021, the second insulating layer 022, and the third insulating layer 023 can be insulating media with low dielectric constants. Since the dielectric constant of the insulating layer affects signal transmission speed and signal integrity, insulating media with lower dielectric constants are beneficial for the rapid transmission of high-frequency and high-speed signals, reducing signal delay and distortion.

[0071] like Figure 4 As shown, the easily breakable structure 300 is arranged in a ring between adjacent chip test areas 200. Its shape can be similar to the shape of the chip test area 200, such as a rectangular ring, a square ring, or a rounded rectangular ring or a rounded square ring. The shape of the easily breakable structure 300 should be set to match the shape of the desired enlarged illumination aperture.

[0072] To enable the breakable structure 300 to be easily broken, in an optional embodiment, the thickness of at least a portion of the breakable structure 300 is less than the thickness of the substrate body at the chip test area 200. For example, the breakable structure 300 may be along... Figure 4 The path marked in the document is a semi-groove, or includes one or more hollow structures spaced apart; the aforementioned hollow structures may be through holes, windows, grooves, grids, patterns, etc., formed on the substrate body by mechanical subtractive manufacturing process or etching process, with the aim of reducing the structural strength between adjacent chip test areas 200.

[0073] In a typical embodiment, the easily broken structure 300 is a plurality of through holes arranged in a dashed line pattern.

[0074] In a typical embodiment, for the rectangular annular chip test area 200, the corresponding easily breakable structure 300 is also a rectangular annular shape. The easily breakable structure 300 is mostly a long, narrow perforation (through-hole), with connecting structures connecting the inner and outer chip test areas 200 only at a few corners. In other words, the easily breakable structure 300 includes connecting structures located at the corners between adjacent chip test areas 200, and perforated structures located between adjacent connecting structures.

[0075] In a typical embodiment, the substrate body includes at least two insulating layers stacked together, and a plurality of metal isolation rings 030 disposed between adjacent insulating layers;

[0076] like Figure 5 As shown, the orthographic projections of multiple metal isolation rings 030 on the surface of the substrate body surround the irradiation hole and at least part of the gold finger area, respectively.

[0077] More specifically, multiple metal isolation rings 030, with the thickness direction of the substrate body as the projection direction and the surface of the substrate body where the chip test area 200 is formed as the projection surface, form an orthographic projection as shown below. Figure 5 As shown, the area surrounding the irradiation hole and at least part of the gold finger region.

[0078] Typical, such as Figure 5 As shown, the metal isolation ring 030 is a rectangular ring.

[0079] In this embodiment, multiple metal isolation rings 030 are provided between the insulating layers to ensure that the chip has a certain anti-interference capability during the testing process. When the chip is subjected to a sudden change in electromagnetic field, the metal isolation rings 030 can effectively slow down the change rate of the electromagnetic field and minimize the impact of the sudden change in electromagnetic field around the chip on the chip under test.

[0080] In a preferred embodiment, the orthographic projection of a portion of the metal isolation ring 030 onto the surface of the substrate body is located on the inner and outer sides of a gold finger region, respectively, which can isolate abrupt electromagnetic fields from both the inner and outer sides of the gold finger region.

[0081] In a preferred embodiment, the chip test area 200 is a rectangular ring; the metal isolation ring 030 is a rounded rectangular ring. The rounded corner design can prevent the laser from irradiating the metal conductors of the PCB substrate during the laser scanning test of the back of the chip, thus avoiding the sharp discharge effect that would affect the test circuit results.

[0082] In a typical embodiment, at least two insulating layers specifically include a first insulating layer 021, a second insulating layer 022, and a third insulating layer 023; the plurality of metal isolation rings 030 include a plurality of first metal isolation rings disposed between the first insulating layer 021 and the second insulating layer 022, and a plurality of second metal isolation rings disposed between the second insulating layer 022 and the third insulating layer 023; the plurality of first metal isolation rings have different sizes, and the plurality of second metal isolation rings have different sizes.

[0083] like Figure 5 As shown, multiple metal isolation rings, such as multiple first metal isolation rings or multiple second metal isolation rings, of different sizes, are arranged in the same layer to surround the irradiation hole 100 and the gold finger region 220.

[0084] In some embodiments, two different metal isolation rings may be provided on the inner and outer sides of each gold finger region 220. The shape of the multiple metal isolation rings may be the same as or different from the shape of the chip test area.

[0085] The metal isolation rings in the aforementioned embodiments can shield against sudden electromagnetic field changes in the surrounding environment during chip testing. At the same time, these metal isolation rings, combined with the aforementioned metal isolation layer, can effectively reduce the temperature changes of the PCB substrate caused by high-energy laser irradiation, improve the thermal stability of the substrate itself, and ensure the authenticity and accuracy of the test signal.

[0086] In a preferred embodiment, such as Figure 6 As shown, the PCB substrate also includes:

[0087] Multiple 400 sockets are located at the edge of the substrate body and penetrate the substrate body;

[0088] Each socket 400 has a conductor on its inner wall, which is electrically connected to the gold finger in at least one gold finger area via a lead 420. The socket 400 is used to insert a pin header, and the pin header is electrically connected to the lead 420 via the conductor on the inner wall of the socket 400, thereby forming an electrical connection between the pin header and the gold finger.

[0089] In a preferred embodiment, a protruding terminal post 410 is provided at the top of the socket 400 for soldering pin headers.

[0090] In a preferred embodiment, the aforementioned conductor is a gold-plated layer on the inner wall of the socket 400.

[0091] In an optional embodiment, the gold plating layer on the inner wall of the socket 400 protrudes from the socket 400 on the surface of the substrate body to form a shape such as Figure 3 The terminal 410 is shown.

[0092] After the pin header is inserted into the socket 400, the aforementioned terminal block 410 can be soldered to the pin header to ensure a stable electrical connection after the pin header is inserted into the corresponding socket. In the aforementioned embodiment, the gold plating layer on the inner wall of the socket 400 has low contact resistance and good conductivity, which can reduce the systematic error of the test; while the terminal block 410 formed by the protruding gold plating layer is easy to solder, has strong corrosion resistance and wear resistance, and improves the reliability of the package.

[0093] In a plurality of sockets 400, the conductor-connected leads 420 in some sockets 400 are located on one surface of the substrate body (e.g., the top surface of the first insulating layer 021), while the conductor-connected leads 420 in other sockets 400 are located on another surface of the substrate body (e.g., the top surface of the third insulating layer 023).

[0094] exist Figure 6 In the diagram, the solid-lined lead 420 is disposed on the surface facing the observation direction, i.e., the surface of the first insulating layer, and is referred to as the upper layer trace; while the dashed-lined lead 420 is disposed on the surface away from the observation direction, i.e., the surface of the third insulating layer, and is referred to as the lower layer trace. In this embodiment, the lower layer trace uses through-hole (PTH) technology in PCB substrate design, which can directly electrically connect the lower layer trace and the inner wall conductor of the corresponding socket 400, ensuring that the physical spacing between adjacent traces is maximized, greatly reducing the electrical and thermal interactions between adjacent lines during the testing process, and further ensuring the accuracy and reliability of chip test data. Through-hole (PTH) technology is a very mature process design in PCB design, but it is not described in detail in this embodiment due to space limitations.

[0095] In the embodiment, the socket 400 penetrates the aforementioned first insulating layer 021, second insulating layer 022, third insulating layer 023, first metal isolation layer 011, and second metal isolation layer 012.

[0096] In this embodiment, an adhesive can be used to bond the chip to the bonding area 210. The adhesive is preferably a colorless, transparent, and insulating material, which will not cause a short circuit risk when bonding the chip and will not affect the light transmission, thus reducing the energy loss of the laser beam.

[0097] In the aforementioned embodiments, leads are provided on both the front and back sides of the substrate body. This method of arranging leads vertically and horizontally not only maximizes the physical distance between adjacent leads, but also allows horizontally adjacent leads on the same surface of the substrate to be arranged further apart. This greatly reduces the electrical and thermal interactions between adjacent leads during the testing process, further ensuring the accuracy and reliability of chip test data.

[0098] In the specific use of the PCB substrate provided in the aforementioned embodiment, firstly, according to the model and size of the integrated circuit chip, a suitable chip test area 200 is selected on the corresponding substrate, the smaller chip test area is removed, and the back of the integrated circuit chip is glued to the corresponding bonding area 210 with adhesive. After the chip is fixed, the chip pads (PAD) and the gold fingers in the corresponding gold finger area 220 are bonded together with silicon aluminum wire or gold wire. Then, the gold fingers are connected to the pin header in the socket through the lead wire 420, thereby connecting the chip to the test circuit or test equipment connected to the pin header, so that the chip is connected to the test circuit. Then, the laser is used to directly irradiate the irradiation hole 100 of the PCB substrate to perform the laser simulated single-particle irradiation damage assessment test.

[0099] The following provides a specific chip testing process using the PCB substrate described in the foregoing embodiments, which includes the following steps:

[0100] The first step is to provide the chip to be tested, and knock off the smaller chip test area according to the size of the chip to be tested, in preparation for bonding the chip in the corresponding bonding area;

[0101] The second step is to bond the chip. The back of the chip, i.e., the silicon substrate layer, is fixed to the bonding area of ​​the PCB substrate using adhesive.

[0102] The third step is wire bonding. Connect the chip PAD to the corresponding gold fingers on the PCB substrate using wires.

[0103] The fourth step is to cure the epoxy resin. After the chip is soldered, place it on a heating platform and surround it with low-temperature thermosetting epoxy resin. Heat until the epoxy resin cures, thus fixing the chip onto the PCB substrate.

[0104] Step 5: Solder the pin headers. Solder the corresponding pin headers from the PCB substrate onto the sockets to begin the chip testing process.

[0105] The sixth step is to conduct laser single-particle experiments.

[0106] In summary, when using the PCB substrate provided in the aforementioned embodiments to conduct laser simulation single-particle irradiation damage assessment tests, the laser can directly enter from the irradiation hole in the center of the PCB substrate, passing through the silicon layer on the back of the chip to directly irradiate the well region inside the chip. This not only avoids the damage caused by removing the substrate or package shell from the back of the chip, but also reduces the energy loss of the laser, making the influence of the laser on the performance of the integrated circuit closer to the theoretical value, the measured electrical parameters more accurate, and the results of the assessment test more accurate.

[0107] After the experiment is completed, the irradiation hole can be sealed directly to complete the encapsulation, thus enabling rapid encapsulation.

[0108] Furthermore, due to the design of the easily breakable structure, the illumination hole can be enlarged, and combined with multiple chip testing areas of different sizes, the PCB substrate can be adapted to a variety of chips of different sizes to be tested.

[0109] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A PCB substrate, characterized by, include: substrate body; An illumination hole (100) penetrates the substrate body; Multiple chip test areas (200) are provided, each having a different size and nested within the substrate body, surrounding the irradiation hole (100); each chip test area (200) includes a die-attachment area (210) and a gold finger area (220) surrounding the die-attachment area (210). A breakable structure (300) is disposed between adjacent chip test areas (200), and the strength of the breakable structure (300) is less than the strength of the substrate body.

2. The PCB substrate of claim 1, wherein, The substrate body includes at least two insulating layers stacked together, and a metal isolation layer (010) disposed between adjacent insulating layers; The metal isolation layer (010) is projected onto the surface of the substrate body and surrounds the plurality of chip test areas (200).

3. The PCB substrate according to claim 2, characterized in that, The at least two insulating layers include a first insulating layer (021), a second insulating layer (022), and a third insulating layer (023); The metal isolation layer (010) includes a first metal isolation layer (011) disposed between the first insulating layer (021) and the second insulating layer (022), and a second metal isolation layer (012) disposed between the second insulating layer (022) and the third insulating layer (023); The first metal isolation layer (011) and the second metal isolation layer (012) may have the same or different dimensions and shapes.

4. The PCB substrate according to claim 1, characterized in that, The thickness of at least a portion of the easily breakable structure (300) is less than the thickness of the substrate body at the chip test area (200); and / or The easily breakable structure (300) includes a single openwork structure or multiple openwork structures spaced apart.

5. The PCB substrate according to claim 4, characterized in that, The chip test area (200) is rectangular; The easily breakable structure (300) includes a connection structure disposed at the corner between adjacent chip test areas (200), and a cutout structure disposed between adjacent connection structures.

6. The PCB substrate according to claim 1, characterized in that, The substrate body includes at least two insulating layers stacked together, and a plurality of metal isolation rings (030) disposed between adjacent insulating layers; The orthographic projections of the plurality of metal isolation rings (030) on the surface of the substrate body respectively surround the irradiation hole and at least part of the gold finger region.

7. The PCB substrate according to claim 6, characterized in that, The metal isolation ring (030) is provided on both the inner and outer sides of the gold finger area.

8. The PCB substrate according to claim 6, characterized in that, The chip test area (200) is a rectangular ring; The metal isolation ring (030) is a rounded rectangular ring.

9. The PCB substrate according to any one of claims 6 to 8, characterized in that, The at least two insulating layers include a first insulating layer (021), a second insulating layer (022), and a third insulating layer (023); The plurality of metal isolation rings (030) include a plurality of first metal isolation rings disposed between the first insulating layer (021) and the second insulating layer (022), and a plurality of second metal isolation rings disposed between the second insulating layer (022) and the third insulating layer (023); The plurality of first metal isolation rings are of different sizes, and the plurality of second metal isolation rings are of different sizes.

10. The PCB substrate according to any one of claims 1 to 8, characterized in that, Also includes: Multiple insertion holes (400) are disposed on the edge of the substrate body and penetrate the substrate body; The inner wall of the socket (400) is provided with a conductor, which is electrically connected to at least one gold finger in the gold finger region via a lead wire (420). Some of the leads (420) are located on one surface of the substrate body, and other parts of the leads (420) are located on the other surface of the substrate body.

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