Power supply control circuit, power supply control device, and electronic device
By designing a power supply control circuit in a multi-chip system, the power supply voltage source of the peripheral chips is automatically shut off and the residual voltage is released, thus solving the problem of reverse power supply of SOC chips and ensuring the stability and reliability of integrated circuits.
Patent Information
- Application Number
- CN202521498999.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2035-07-17
AI Technical Summary
In a multi-chip system, when the power supply voltage source of the SOC chip is de-energized, the power supply voltage source of the peripheral chip may supply power to the SOC chip through a low-impedance electrical path, resulting in reverse power supply, which can cause logic errors, functional abnormalities, or even chip damage.
Design a power supply control circuit, including a power disable module and a voltage release module, to automatically shut down the power supply voltage source of the peripheral chip when the power supply voltage source of the SOC chip is de-energized, and release its residual voltage to prevent reverse power supply.
This effectively avoids logic errors and functional abnormalities in integrated circuits caused by abnormal power supply, ensuring the stable operation of integrated circuits.
Smart Images
Figure CN224684203U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit technology, and in particular to a power supply control circuit, a power supply control device, and an electronic device. Background Technology
[0002] With the rapid development of electronic technology, multi-chip systems have been widely used in many fields such as consumer electronics, industrial control, and automotive electronics. A multi-chip system typically consists of a system-on-chip (SoC) and multiple peripheral chips. These chips exchange data and work collaboratively through specific communication protocols and physical interfaces to meet the demands for high performance, low power consumption, and high integration in complex application scenarios. However, in the practical application of multi-chip systems, power management has become one of the key factors affecting system stability and reliability.
[0003] In multi-chip systems, the System-on-a-Chip (SoC) chip serves as the core processing unit, undertaking crucial tasks such as data processing and control coordination, while peripheral chips provide functions like storage, input / output, and signal processing according to system requirements. To ensure the normal operation of each chip, each chip is typically equipped with an independent power supply. However, in practical applications, due to the complexity of power management strategies, the unpredictability of power failures, and the unique electrical connections between chips, situations may arise where the SoC chip's power supply fails while the peripheral chips' power supplies continue to operate normally.
[0004] In this situation, if a low-impedance electrical path exists between the SOC chip and peripheral chips, the power supply voltage source of the peripheral chips may supply power to the SOC chip through this path, forming a so-called "reverse power supply" phenomenon. This reverse power supply may cause the SOC chip to operate at a voltage other than its design voltage, leading to serious consequences such as logic errors, functional abnormalities, or even chip damage. Utility Model Content
[0005] Based on this, the present invention provides a power supply control circuit, which is applied to a power supply circuit including a first voltage source, a second voltage source and a first capacitor. The first voltage source is used to supply power to a first integrated circuit, and the second voltage source is used to supply power to a second integrated circuit. Through this power supply control circuit, when the first voltage source is de-energized, the second voltage source can be automatically shut down, preventing the second voltage source from supplying power to the first integrated circuit through the electrical path between the first and second integrated circuits. This avoids problems such as logic errors and functional abnormalities of integrated circuits caused by abnormal power supply, and ensures the stable operation of integrated circuits.
[0006] On one hand, this utility model provides a power supply control circuit, which is applied to a power supply circuit including a first voltage source, a second voltage source and a first capacitor. The first voltage source is used to supply power to a first integrated circuit, the second voltage source is used to supply power to a second integrated circuit, the first capacitor is connected in parallel across the positive and negative terminals of the first voltage source, the first integrated circuit and the second integrated circuit are electrically connected, and the positive terminals of the first voltage source and the second voltage source are indirectly connected through the first integrated circuit and the second integrated circuit.
[0007] The power supply control circuit includes a power disable module and a voltage release module, wherein:
[0008] One end of the power disable module is connected to the positive terminal of the first voltage source, the other end of the power disable module is connected to the enable control port of the second voltage source, the first end of the voltage release module is connected to the positive terminal of the second voltage source, the second end of the voltage release module is connected to the other end of the power disable module, and the third end of the voltage release module is grounded.
[0009] The power disable module is used to output a power disable signal when the first voltage source is powered off, and the power disable signal is used to turn off the second voltage source;
[0010] The voltage release module is used to release the residual voltage of the second voltage source according to the power disable signal.
[0011] Furthermore, in some embodiments, the power disable signal is a low-level signal;
[0012] The power disable module includes a hysteresis comparator, wherein:
[0013] The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to the enable control port of the second voltage source.
[0014] Furthermore, in some embodiments, the power disable module includes a hysteresis comparator and an AND gate integrated circuit, wherein:
[0015] The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to the first input of the AND gate integrated circuit.
[0016] The second input terminal of the AND gate integrated circuit is connected to a power on / off signal used to control the on / off state of the second voltage source, and the output terminal of the AND gate integrated circuit is connected to the enable control port of the second voltage source.
[0017] Furthermore, in some embodiments, the voltage release module includes an inverter, an NMOS transistor, and a first resistor, wherein:
[0018] One end of the inverter is connected to the other end of the power disable module, and the other end of the inverter is connected to the gate of the NMOS transistor.
[0019] One end of the first resistor is connected to the positive terminal of the second voltage source, and the other end of the first resistor is connected to the drain of the NMOS transistor.
[0020] The source of the NMOS transistor is grounded.
[0021] Furthermore, in some embodiments, the voltage release module includes a PMOS transistor and a second resistor, wherein:
[0022] The gate of the PMOS transistor is connected to the other end of the power disable module, and the source of the PMOS transistor is connected to the positive terminal of the second voltage source.
[0023] The drain of the PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to ground.
[0024] Furthermore, in some embodiments, the power disable signal is a high-level signal;
[0025] The power disable module includes a hysteresis comparator and a first inverter, wherein:
[0026] The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to one end of the first inverter.
[0027] The other end of the first inverter is connected to the enable control port of the second voltage source.
[0028] Furthermore, in some embodiments, the voltage release module includes an NMOS transistor and a first resistor, wherein:
[0029] The gate of the NMOS transistor is connected to the other end of the power disable module, the drain of the NMOS transistor is connected to one end of the first resistor, and the source of the NMOS transistor is grounded.
[0030] The other end of the first resistor is connected to the positive terminal of the second voltage source.
[0031] Furthermore, in some embodiments, the voltage release module includes a second inverter, a PMOS transistor, and a second resistor, wherein:
[0032] One end of the second inverter is connected to the other end of the power disable module, and the other end of the second inverter is connected to the gate of the PMOS transistor.
[0033] The source of the PMOS transistor is connected to the positive terminal of the second voltage source, the drain of the PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to ground.
[0034] On the other hand, the present invention provides a power supply control device equipped with the power supply control circuit as described above.
[0035] On the other hand, the present invention provides an electronic device including the power supply control device as described above.
[0036] The power supply control circuit provided by this utility model is applied to a power supply circuit including a first voltage source, a second voltage source, and a first capacitor. The power supply control circuit includes a power disable module and a voltage release module, wherein: one end of the power disable module is connected to the positive terminal of the first voltage source, the other end of the power disable module is connected to the enable control port of the second voltage source, the first end of the voltage release module is connected to the positive terminal of the second voltage source, the second end of the voltage release module is connected to the other end of the power disable module, and the third end of the voltage release module is grounded; the power disable module is used to output a power disable signal when the first voltage source is de-energized, and the power disable signal is used to shut down the second voltage source; the voltage release module is used to release the residual voltage of the second voltage source according to the power disable signal; that is, through this power supply control circuit, the second voltage source can be automatically shut down when the first voltage source experiences a power failure, preventing the second voltage source from supplying power to the first integrated circuit through the electrical path between the first integrated circuit and the second integrated circuit, thereby reducing the probability of integrated circuit logic errors, functional abnormalities, and other problems caused by abnormal power supply, and ensuring the stable operation of the integrated circuit.
[0037] It should be understood that the description in this utility model description section is not intended to limit the key or essential features of the embodiments of this utility model, nor is it intended to restrict the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of a power supply circuit provided in an embodiment of this specification;
[0039] Figure 2 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0040] Figure 3 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0041] Figure 4 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0042] Figure 5 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0043] Figure 6 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0044] Figure 7 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0045] Figure 8 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification;
[0046] Figure 9 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.
[0048] In the description of one or more embodiments in this specification, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0049] In some embodiments of this specification, the power supply control circuit can be applied to a power supply circuit including a first voltage source, a second voltage source, and a first capacitor. In this power supply circuit, the first voltage source is used to power a first integrated circuit, the second voltage source is used to power a second integrated circuit, the first capacitor is connected in parallel across the positive and negative terminals of the first voltage source, the first integrated circuit and the second integrated circuit are electrically connected, and the positive terminals of the first voltage source and the second voltage source are indirectly connected through the first integrated circuit and the second integrated circuit.
[0050] The first integrated circuit can be a SOC chip in a multi-chip system, and the second integrated circuit can be a peripheral chip in the multi-chip system. Please refer to [link / reference]. Figure 1 The example shown is a schematic diagram of a power supply circuit provided in an embodiment of this specification. Figure 1 As shown, the power supply circuit includes a first voltage source V1, a first capacitor C1, a SOC chip IC1, diodes D1 and D2 located in IC1, a peripheral chip IC2, a resistor R1, and a second voltage source V2. The first voltage source powers the SOC chip, and the second voltage source powers the peripheral chips. Figure 1 In the power supply circuit shown, if the first voltage source is de-energized, the second voltage source can charge the first capacitor C1 through the electrical path of resistor R-diode D1, thereby forming a reverse power supply to the SOC chip. This reverse power supply may cause the SOC chip to operate at a non-design voltage, leading to serious consequences such as logic errors, functional abnormalities, or even chip damage.
[0051] Based on this, the present invention proposes a power supply control circuit for use in a power supply circuit including a first voltage source, a second voltage source, and a first capacitor. The first voltage source powers a first integrated circuit, the second voltage source powers a second integrated circuit, the first capacitor is connected in parallel across the positive and negative terminals of the first voltage source, the first integrated circuit and the second integrated circuit are electrically connected, and the positive terminals of the first and second voltage sources are indirectly connected through the first and second integrated circuits. The power supply control circuit proposed in this invention includes a power disable module and a voltage release module, wherein: one end of the power disable module is connected to the positive terminal of the first voltage source, the other end of the power disable module is connected to the enable control port of the second voltage source, the first end of the voltage release module is connected to the positive terminal of the second voltage source, the second end of the voltage release module is connected to the other end of the power disable module, and the third end of the voltage release module is grounded; the power disable module outputs a power disable signal when the first voltage source is de-energized, and the power disable signal is used to shut down the second voltage source; the voltage release module releases the residual voltage of the second voltage source according to the power disable signal. The power supply control circuit proposed in this utility model can automatically shut down the second voltage source and release the residual voltage of the second voltage source when the first voltage source is de-energized. This prevents the second voltage source from supplying power to the first integrated circuit through the electrical path between the first and second integrated circuits, thereby reducing the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply and ensuring the stable operation of the integrated circuit.
[0052] Please see Figure 2 This is a schematic diagram of a power supply control circuit provided in an embodiment of this specification. The power supply control circuit is connected to a power supply circuit including a first voltage source V1, a second voltage source V2, and a first capacitor C1. The first voltage source V1 supplies power to a first integrated circuit IC1, and the second voltage source V2 supplies power to a second integrated circuit IC2. The power supply control circuit 1 includes a power disable module 11 and a voltage release module 12, wherein:
[0053] One end of the power disable module 11 is connected to the positive terminal of the first voltage source V1, the other end of the power disable module 11 is connected to the enable control port of the second voltage source V2, the first end of the voltage release module 12 is connected to the positive terminal of the second voltage source V2, the second end of the voltage release module 12 is connected to the other end of the power disable module 11, and the third end of the voltage release module 12 is grounded.
[0054] The power disable module 11 is used to output a power disable signal when the first voltage source V1 is powered off. The power disable signal is used to shut down the second voltage source V2. The voltage release module 12 is used to release the residual voltage of the second voltage source V2 according to the power disable signal.
[0055] Specifically, one end of the power disable module in the power supply control circuit is connected to the positive terminal of the first voltage source. When the first voltage source is de-energized, the power disable module generates a power disable signal based on the power-off signal of the first voltage source. This power disable signal can be sent to the second voltage source V2 through the enable control port of the second voltage source V2. The second voltage source may include a power chip with enable control on / off function, and the second voltage source V2 can be controlled to shut down by the power chip based on the power disable signal. The voltage release module can open the electrical path between the positive terminal of the second voltage source and ground based on the power disable signal to release the residual voltage of the second voltage source.
[0056] This power supply control circuit prevents the second voltage source from supplying power to the first integrated circuit through the electrical path between the first and second integrated circuits by shutting down the second voltage source and releasing its residual voltage. This reduces the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply, and ensures the stable operation of the integrated circuit.
[0057] The power disable signal can be either a high-level signal or a low-level signal. The enable control logic for the second voltage source can be either controlled to turn off based on a high-level signal or controlled to turn off based on a low-level signal.
[0058] In some embodiments, the power-off signal is a low-level signal. For example... Figure 2 As shown, the power disable module 11 includes a hysteresis comparator U1, wherein: the non-inverting input terminal of the hysteresis comparator U1 is connected to the positive terminal of the first voltage source V1, the inverting input terminal of the hysteresis comparator U1 is connected to a reference voltage signal V0, and the output terminal of the hysteresis comparator U1 is connected to the enable control port of the second voltage source V2.
[0059] The hysteresis comparator operates based on a positive feedback mechanism. When the input signal rises from a low level and exceeds a high threshold, the output state flips; when the input signal falls from a high level and falls below a low threshold, the output state flips again.
[0060] The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source. When the first voltage source is operating normally, the voltage at the non-inverting input of the hysteresis comparator is higher than the reference voltage at the inverting input, and the hysteresis comparator outputs a high-level signal. When the first voltage source is de-energized, the voltage at the non-inverting input of the hysteresis comparator is lower than the reference voltage at the inverting input, and the hysteresis comparator outputs a low-level signal. Since the enable control logic of the second voltage source is based on a low-level signal to control its shutdown, the low-level signal output by the hysteresis comparator is the power disable signal. When the enable control port of the second voltage source receives this low-level signal, it shuts down the second voltage source, thereby reducing the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply, and ensuring the stable operation of the integrated circuit.
[0061] Furthermore, in one embodiment, the power-off signal is a low-level signal. For example... Figure 3 As shown, the power disable module 11 includes a hysteresis comparator U1 and an AND gate integrated circuit U2, wherein: the non-inverting input terminal of the hysteresis comparator U1 is connected to the positive terminal of the first voltage source V1, the inverting input terminal of the hysteresis comparator U1 is connected to a reference voltage signal V0, the output terminal of the hysteresis comparator U1 is connected to the first input terminal of the AND gate integrated circuit U2; the second input terminal of the AND gate integrated circuit U2 is connected to the power on / off signal V2-EN used to control the on / off state of the second voltage source, and the output terminal of the AND gate integrated circuit is connected to the enable control port of the second voltage source V2.
[0062] The AND gate integrated circuit is based on the AND operation. Its core function is that the output is high only when all inputs are high (logic 1); otherwise, the output is low (logic 0). The power on / off signal is a status signal corresponding to the operating state of the second voltage source. When the second voltage source is on, the power on / off signal is high; when the second voltage source is off, the power on / off signal is low.
[0063] Understandably, when the first voltage source is de-energized, the voltage at the non-inverting input of the hysteresis comparator is lower than the reference voltage at the inverting input. At this time, the hysteresis comparator outputs a low-level signal. This low-level signal serves as the input to the first input of the AND gate integrated circuit, causing the AND gate to output a low-level signal. When the enable control port of the second voltage source receives this low-level signal, it shuts down the second voltage source, thereby reducing the probability of logic errors and functional abnormalities in the integrated circuit caused by abnormal power supply, and ensuring the stable operation of the integrated circuit.
[0064] It should be further noted that the second voltage source is used to power the second integrated circuit. In some scenarios, the second integrated circuit does not need to work together with the first integrated circuit. When it is necessary to turn off the second voltage source, simply set the power on / off signal from high to low. At this time, the AND gate integrated circuit only outputs a low level. When the enable control port of the second voltage source receives this low-level signal, it turns off the second voltage source.
[0065] In one embodiment, the power-off signal is a low-level signal. For example... Figure 4 As shown, the voltage release module 12 includes an inverter U3, an NMOS transistor Q1, and a first resistor R2, wherein: one end of the inverter U3 is connected to the other end of the power disable module 11, and the other end of the inverter U3 is connected to the gate of the NMOS transistor Q1; one end of the first resistor R2 is connected to the positive terminal of the second voltage source V2, and the other end of the first resistor R2 is connected to the drain of the NMOS transistor Q1; the source of the NMOS transistor Q1 is grounded.
[0066] An inverter is an electronic circuit whose main function is to invert the phase of an input signal by 180 degrees. When the input signal is high, the output of the inverter is low; when the input signal is low, the output of the inverter is high. NMOS (N-Metal-Oxide-Semiconductor) is a semiconductor device. NMOS transistors are made of N-type semiconductor materials and have advantages such as high input resistance, low noise, low power consumption, large dynamic range, and ease of integration. The basic structure of an NMOS transistor includes a P-type silicon substrate and two highly doped N+ regions, serving as the drain and source, respectively. A gate is mounted on the insulating layer between the drain and source. The gate voltage controls whether the current flows between the drain and source. When the gate voltage is higher than a certain threshold, a conductive channel is formed between the drain and source, allowing current to flow.
[0067] Understandably, in this embodiment, the power-off signal is a low-level signal. When the inverter receives this low-level signal, it outputs a high-level signal. This high-level signal directly acts on the NMOS gate, causing the gate voltage to be higher than the source voltage. The NMOS transistor then turns on, allowing the residual voltage of the second voltage source to dissipate to ground through the drain-source channel. This prevents the residual voltage from the second voltage source from affecting the integrated circuit, ensuring the stable operation of the integrated circuit.
[0068] In some embodiments, the power-off signal is a low-level signal. For example... Figure 5 As shown, the voltage release module 12 includes a PMOS transistor Q2 and a second resistor R3, wherein: the gate of the PMOS transistor Q2 is connected to the other end of the power disable module 11, the source of the PMOS transistor Q2 is connected to the positive terminal of the second voltage source V2; the drain of the PMOS transistor Q2 is connected to one end of the second resistor R3, and the other end of the second resistor R3 is grounded.
[0069] Among them, PMOS (P-channel Metal-Oxide-Semiconductor) is a semiconductor device. PMOS refers to a metal-oxide-semiconductor field-effect transistor (MOSFET) with an n-type substrate and a p-channel, which mainly relies on the flow of holes to carry current.
[0070] A PMOS transistor consists of a gate, a source, and a drain. When the gate voltage VGS is lower than the source voltage, a negative electric field is formed between the gate and the channel, attracting holes (positive charge carriers) in the P-type semiconductor to accumulate in the channel, forming a conductive path, thereby making the source and drain conductive.
[0071] Understandably, in this embodiment, the power-off signal is a low-level signal. This low-level signal directly acts on the PMOS gate, causing the gate voltage to be lower than the source voltage. The PMOS transistor then turns on, allowing the residual voltage of the second voltage source to dissipate to ground through the drain-source channel. This prevents the residual voltage from the second voltage source from affecting the integrated circuit and ensures the stable operation of the integrated circuit.
[0072] In some embodiments, the power disable signal can also be a high-level signal, and the enable control logic of the second voltage source controls its shutdown based on the high-level signal. For example... Figure 6 As shown, the power disable module 11 includes a hysteresis comparator U1 and a first inverter U4, wherein: the non-inverting input terminal of the hysteresis comparator U1 is connected to the positive terminal of the first voltage source V1, the inverting input terminal of the hysteresis comparator U1 is connected to a reference voltage signal V0, the output terminal of the hysteresis comparator U1 is connected to one end of the first inverter U4; the other end of the first inverter U4 is connected to the enable control port of the second voltage source V2.
[0073] Understandably, when the power disable signal is high, the enable control logic of the second voltage source is to control its shutdown based on the high-level signal. The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source. When the first voltage source is operating normally, the voltage at the non-inverting input of the hysteresis comparator is higher than the reference voltage at the inverting input, at which point the hysteresis comparator outputs a high-level signal. When the first voltage source is de-energized, the voltage at the non-inverting input of the hysteresis comparator is lower than the reference voltage at the inverting input, at which point the hysteresis comparator outputs a low-level signal. The low-level signal output by the hysteresis comparator is converted to a high-level signal by the first inverter. When this high-level signal acts on the enable control port of the second voltage source, it triggers the shutdown of the second voltage source, thereby reducing the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply, and ensuring the stable operation of the integrated circuit.
[0074] In some embodiments, the power disable signal can also be a high-level signal, and the enable control logic of the second voltage source controls its shutdown based on the high-level signal. For example... Figure 7 As shown, the voltage release module 12 includes an NMOS transistor Q1 and a first resistor R2, wherein: the gate of the NMOS transistor Q1 is connected to the other end of the power disable module 11, the drain of the NMOS transistor Q1 is connected to one end of the first resistor R2, and the source of the NMOS transistor Q1 is grounded; the other end of the first resistor R2 is connected to the positive terminal of the second voltage source V2.
[0075] It is understood that in this embodiment, the power disable signal is a high-level signal. When the first voltage source is powered off, the high-level signal output by the power disable module directly acts on the NMOS gate, making the gate voltage higher than the source voltage. The NMOS transistor turns on, and the residual voltage of the second voltage source is dissipated to ground through the drain-source channel. This avoids the residual voltage when the second voltage source is turned off from affecting the integrated circuit and ensures the stable operation of the integrated circuit.
[0076] In some embodiments, the power disable signal can also be a high-level signal, and the enable control logic of the second voltage source controls its shutdown based on the high-level signal. For example... Figure 8 As shown, the voltage release module 12 includes a second inverter U5, a PMOS transistor Q2, and a second resistor R3. One end of the second inverter U5 is connected to the other end of the power disable module 11, and the other end of the second inverter U5 is connected to the gate of the PMOS transistor Q2. The source of the PMOS transistor Q2 is connected to the positive terminal of the second voltage source V2, the drain of the PMOS transistor Q2 is connected to one end of the second resistor R3, and the other end of the second resistor R3 is grounded.
[0077] It is understood that in this embodiment, the power disable signal is a high-level signal. When the first voltage source is powered off, the high-level signal output by the power disable module is converted into a low-level signal by the second inverter. This converted low-level signal directly acts on the PMOS gate, causing the gate voltage to be lower than the source voltage, thus turning on the PMOS transistor. This allows the residual voltage of the second voltage source to dissipate to ground through the drain-source channel. This avoids the residual voltage from the second voltage source being turned off from affecting the integrated circuit, ensuring the stable operation of the integrated circuit.
[0078] Finally, taking the example where the power disable signal is a low-level signal and the enable control logic of the second voltage source is controlled to shut down based on a high-level signal, please refer to [link to relevant documentation]. Figure 9 This is a detailed structural diagram of a power supply control circuit provided in the embodiment of the specification. The power supply control circuit is connected to a power supply circuit including a first voltage source V1, a second voltage source V2, and a first capacitor C1. The first voltage source V1 supplies power to a first integrated circuit IC1, and the second voltage source V2 supplies power to a second integrated circuit IC2. Figure 9As shown, the power supply control circuit includes a power disable module 11 and a voltage release module 12. The power disable module 11 includes a hysteresis comparator U1 and an AND gate integrated circuit U2, wherein: the non-inverting input terminal of the hysteresis comparator U1 is connected to the positive terminal of the first voltage source V1, the inverting input terminal of the hysteresis comparator U1 is connected to a reference voltage signal V0, the output terminal of the hysteresis comparator U1 is connected to the first input terminal of the AND gate integrated circuit U2, and the second input terminal of the AND gate integrated circuit U2 is connected to the power on / off signal V for controlling the on / off state of the second voltage source. 2-EN is connected to the output terminal of the AND gate integrated circuit and the enable control port of the second voltage source V2; the voltage release module 12 includes an inverter U3, an NMOS transistor Q1 and a first resistor R2, wherein: one end of the inverter U3 is connected to the other end of the power disable module 11, the other end of the inverter U3 is connected to the gate of the NMOS transistor Q1, one end of the first resistor R2 is connected to the positive terminal of the second voltage source V2, the other end of the first resistor R2 is connected to the drain of the NMOS transistor Q1; the source of the NMOS transistor Q1 is grounded.
[0079] In such Figure 9 In the power supply control circuit shown, when the first voltage source V1 is de-energized, the voltage at the non-inverting input of the hysteresis comparator U1 is lower than the reference voltage at the inverting input. At this time, the hysteresis comparator outputs a low-level signal. In response to this low-level signal, the AND gate integrated circuit U2 outputs a low-level signal. The low-level signal output by the AND gate integrated circuit U2 acts on the enable control port of the second voltage source V2, triggering the second voltage source V2 to turn off. The low-level signal output by the AND gate integrated circuit U2 also acts on the inverter U3, which outputs a high-level signal to the gate of the NMOS transistor Q1, making the gate voltage higher than the source voltage. The NMOS transistor then conducts, allowing the residual voltage of the second voltage source to dissipate to ground through the drain-source channel. By turning off the second voltage source and dissipating its residual voltage, the second voltage source is prevented from supplying power to the first integrated circuit through the electrical path between the first and second integrated circuits. This reduces the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply, ensuring the stable operation of the integrated circuit.
[0080] In some embodiments, the present invention also provides a power supply control device, including the power supply control circuit as described above. Using this power supply control circuit, when the first voltage source is de-energized, the second voltage source can be automatically shut off, preventing the second voltage source from supplying power to the first integrated circuit through the electrical path between the first and second integrated circuits. This reduces the probability of integrated circuit logic errors and functional abnormalities caused by abnormal power supply, ensuring the stable operation of the integrated circuit.
[0081] In some embodiments, the present invention also provides an electronic device including the power supply control device as described above.
[0082] Finally, the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.
[0083] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.
Claims
1. A power supply control circuit, characterized in that, The circuit is applied to a power supply circuit including a first voltage source, a second voltage source, and a first capacitor. The first voltage source is used to power a first integrated circuit, the second voltage source is used to power a second integrated circuit, the first capacitor is connected in parallel across the positive and negative terminals of the first voltage source, the first integrated circuit and the second integrated circuit are electrically connected, and the positive terminals of the first voltage source and the second voltage source are indirectly connected through the first integrated circuit and the second integrated circuit. The power supply control circuit includes a power disable module and a voltage release module, wherein: One end of the power disable module is connected to the positive terminal of the first voltage source, the other end of the power disable module is connected to the enable control port of the second voltage source, the first end of the voltage release module is connected to the positive terminal of the second voltage source, the second end of the voltage release module is connected to the other end of the power disable module, and the third end of the voltage release module is grounded. The power disable module is used to output a power disable signal when the first voltage source is powered off, and the power disable signal is used to turn off the second voltage source; The voltage release module is used to release the residual voltage of the second voltage source according to the power disable signal.
2. The power supply control circuit according to claim 1, characterized in that, The power-off signal is a low-level signal; The power disable module includes a hysteresis comparator, wherein: The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to the enable control port of the second voltage source.
3. The power supply control circuit according to claim 2, characterized in that, The power disable module includes a hysteresis comparator and an AND gate integrated circuit, wherein: The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to the first input of the AND gate integrated circuit. The second input terminal of the AND gate integrated circuit is connected to a power on / off signal used to control the on / off state of the second voltage source, and the output terminal of the AND gate integrated circuit is connected to the enable control port of the second voltage source.
4. The power supply control circuit according to claim 2, characterized in that, The voltage release module includes an inverter, an NMOS transistor, and a first resistor, wherein: One end of the inverter is connected to the other end of the power disable module, and the other end of the inverter is connected to the gate of the NMOS transistor. One end of the first resistor is connected to the positive terminal of the second voltage source, and the other end of the first resistor is connected to the drain of the NMOS transistor; The source of the NMOS transistor is grounded.
5. The power supply control circuit according to claim 2, characterized in that, The voltage release module includes a PMOS transistor and a second resistor, wherein: The gate of the PMOS transistor is connected to the other end of the power disable module, and the source of the PMOS transistor is connected to the positive terminal of the second voltage source. The drain of the PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to ground.
6. The power supply control circuit according to claim 1, characterized in that, The power-off signal is a high-level signal; The power disable module includes a hysteresis comparator and a first inverter, wherein: The non-inverting input of the hysteresis comparator is connected to the positive terminal of the first voltage source, the inverting input of the hysteresis comparator is connected to a reference voltage signal, and the output of the hysteresis comparator is connected to one end of the first inverter. The other end of the first inverter is connected to the enable control port of the second voltage source.
7. The power supply control circuit according to claim 6, characterized in that, The voltage release module includes an NMOS transistor and a first resistor, wherein: The gate of the NMOS transistor is connected to the other end of the power disable module, the drain of the NMOS transistor is connected to one end of the first resistor, and the source of the NMOS transistor is grounded. The other end of the first resistor is connected to the positive terminal of the second voltage source.
8. The power supply control circuit according to claim 6, characterized in that, The voltage release module includes a second inverter, a PMOS transistor, and a second resistor, wherein: One end of the second inverter is connected to the other end of the power disable module, and the other end of the second inverter is connected to the gate of the PMOS transistor. The source of the PMOS transistor is connected to the positive terminal of the second voltage source, the drain of the PMOS transistor is connected to one end of the second resistor, and the other end of the second resistor is connected to ground.
9. A power supply control device, characterized in that, It is equipped with a power supply control circuit as described in any one of claims 1-8.
10. An electronic device comprising the power supply control device as described in claim 9.