Method for polishing semiconductor element and method for observing semiconductor element

Abstract

To provide a method for polishing a semiconductor element which can control the thickness of a semiconductor element.SOLUTION: A method for polishing a semiconductor element 3 equipped to a supporting body by a solder includes the steps of: sealing a supporting body and a semiconductor element 3 by a buried resin 5; polishing the buried resin 5 so that a side surface of the supporting body is exposed from the buried resin 5; polishing the buried resin 5 and the semiconductor element 3 from the upper surface; and observing the polished side surface of the buried resin 5 and measuring the thickness of the buried resin 5 on the upper surface of the supporting body. In the present disclosure, the polishing step and the measurement step are repeated until the thickness of the buried resin 5 becomes a predetermined thickness T.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a method for polishing a semiconductor element and a method for observing a semiconductor element. [Background technology]

[0002] Patent Document 1 discloses a technique for observing electroluminescence (hereinafter referred to as EL) of a semiconductor element placed on a support, which makes it possible to observe the semiconductor element without damaging the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-256646 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned method, in order to observe the cross section of the active layer of the semiconductor element, it is necessary to remove the semiconductor element mounted on the support by soldering. However, since it is necessary to melt the solder at a higher temperature than when it was attached, there is a possibility that the semiconductor element may be deteriorated by heating. In addition, there is a risk of damaging the semiconductor element when it is picked up with tweezers.

[0005] In order to observe the cross section of the active layer of a semiconductor element mounted on a support by soldering, it is effective to polish the semiconductor element from the top surface to expose the vicinity of the desired observation location, but in the past, it was difficult to control the thickness of the semiconductor element during polishing.

[0006] In order to solve the above-mentioned problems, a first object of the present disclosure is to provide a method for polishing a semiconductor element that is capable of controlling the thickness of the semiconductor element.

[0007] A second object of the present disclosure is to provide a method for observing a semiconductor element that can be applied to a semiconductor element mounted on a support by soldering. [Means for solving the problem]

[0008] The first aspect of the present disclosure is 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; polishing the embedding resin so that a side surface of the support is exposed from the embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; a measuring step of observing a side surface of the polished embedding resin and measuring a thickness of the embedding resin present on the upper surface of the support; Including, It is preferable that the polishing step and the measuring step are repeated until the thickness of the potting resin reaches a predetermined thickness.

[0009] In addition, the second aspect is 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: Mounting a structure having a predetermined thickness on an upper surface of the support; encapsulating the structure, the support, and the semiconductor element with an embedding resin; polishing the embedding resin and the semiconductor element from the upper surface until the upper surface of the structure is exposed; It is preferred that the compound contains

[0010] Moreover, the third aspect is 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; forming a hole from a polished surface of the semiconductor element to a solder joint surface of the semiconductor element; a measuring step of measuring the depth of the hole; Including, It is preferable that the polishing step and the measuring step are repeated until the depth of the hole reaches a predetermined depth.

[0011] Moreover, the fourth aspect is The method for observing a semiconductor element includes the steps of: A step of carrying out the method for polishing a semiconductor element according to any one of claims 1 to 4; observing an active layer of the semiconductor device; Including, The predetermined thickness or the predetermined depth is preferably determined depending on the type of observation method for the active layer. Effect of the Invention

[0012] According to the first to fourth aspects of the present disclosure, it is possible to provide a polishing method for a semiconductor element that enables control of the thickness of the semiconductor element, and a method for observing a semiconductor element that can be applied to a semiconductor element mounted on a support by solder. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device having a semiconductor element that is the subject of polishing and observation according to the present disclosure. [Diagram 2] 2A to 2C are diagrams illustrating a method for polishing a semiconductor element according to the first embodiment. [Diagram 3] 3 illustrates a semiconductor device after completion of the process described in FIG. 2. [Figure 4] 3A to 3C are diagrams illustrating an EL observation method for the semiconductor element according to the first embodiment. [Diagram 5] 11A to 11C are diagrams illustrating a method for polishing a semiconductor element according to a second embodiment. [Figure 6] 6 illustrates a semiconductor device after completion of the process described in FIG. 5. [Figure 7] 11A to 11C are diagrams illustrating a method for polishing a semiconductor element according to a third embodiment. [Figure 8]8 illustrates a semiconductor device after completion of the process described in FIG. 7. [Figure 9] 11A and 11B are diagrams illustrating the semiconductor element after the side polishing step and the polishing step are completed. [Figure 10] 13A to 13C are diagrams illustrating a method for polishing a semiconductor element according to a fourth embodiment. [Figure 11] 11 illustrates a semiconductor device after completion of the process described in FIG. 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] A method for polishing a semiconductor element and a method for observing a semiconductor element according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0015] First embodiment 1 is a diagram showing the configuration of a semiconductor device 100 having a semiconductor element 3 that is the subject of polishing and observation in the present disclosure. The semiconductor device 100 includes a block 1, a submount 2 as a support, and the semiconductor element 3.

[0016] The submount 2 is a mounting base having wiring 12 and wiring 9 on its upper surface. The surface 31 side of the semiconductor element 3 is mounted to the wiring 12 with solder 11. In other words, the semiconductor element 3 is mounted upside down on the submount 2. The material of the submount 2 is an electrical insulator, typically a ceramic plate such as AlN or Al2O3.

[0017] The block 1 is bonded to the back surface of the submount 2. The material of the block 1 is a material with excellent thermal conductivity, such as a metal such as Ag, Cu, Fe, or Al, or an alloy thereof, or an insulator such as a ceramic or resin coated with a metal.

[0018] The semiconductor element 3 is made of materials such as InP, GaAs, GaN, InGaAs, Ge, and Si. The semiconductor element 3 is, for example, an LD (Laser Diode) that converts an electrical signal into an optical signal, or a PD (Photo Diode) that performs the inverse conversion. The semiconductor element 3 has an active layer 4 formed on the surface 31 side of the semiconductor element 3. The active layer 4 is, for example, a light absorption layer made of a material that generates carriers when light is incident. The thickness of the semiconductor element 3 is, for example, 80 μm, and the active layer 4 is formed at a position 5 μm or less from the surface 31 of the semiconductor element 3, but these numerical values ​​are merely examples and are not limited thereto.

[0019] A surface electrode 10 is formed on a surface 31 of the semiconductor element 3. The surface electrode 10 is electrically and mechanically joined to the submount 2 by solder 11. A back surface electrode 6 is formed on a back surface 32 of the semiconductor element 3. The back surface electrode 6 has a thickness of about 5 μm, but this is an example and is not limited to this value. One end of a wire 7 is connected to the back surface electrode 6. A wire ball 8 at the other end of the wire 7 is bonded to a wiring 9.

[0020] The thickness of the surface electrodes 10, the solder 11, and the wiring 12 is thin, and the total thickness is about 5 μm. However, these values ​​are only an example, and it is sufficient if they are sufficiently thin compared to the thickness of the semiconductor element 3.

[0021] As described above, in the present disclosure, the semiconductor element 3 to be polished and observed is mounted on the submount 2 with the solder 11 in an inverted state.

[0022] A method for polishing the semiconductor element 3 from the back electrode 6 side and observing the semiconductor element 3 will be described below with reference to FIGS.

[0023] FIG. 2 is a diagram showing a method for polishing the semiconductor element 3 according to the first embodiment.

[0024] First, the semiconductor device 100 is encapsulated with a hardening embedding resin 5. Specifically, a hardening agent is mixed into liquid resin and then hardened. At this time, among the components of the semiconductor device 100, at least the submount 2 and the semiconductor element 3 are encapsulated. This facilitates handling. Furthermore, the semiconductor element 3 can be protected in the polishing process described below.

[0025] Next, the embedding resin 5 is polished so that the side surface of the submount 2 is exposed from the embedding resin 5. The type of polishing is, but is not limited to, grinding stone polishing with SiC or metal, buff polishing, mirror polishing using diamond abrasive grains, etc. In FIG. 2, the line L1 indicates the position of the polished surface formed by side surface polishing.

[0026] Next, a polishing step is performed to polish the embedding resin 5 and the semiconductor element 3 from the upper surface. Furthermore, the polished surface formed by the side surface polishing is observed by an SEM or the like, and a measuring step is performed to measure the thickness t of the embedding resin 5 present on the upper surface of the submount 2 on the polished surface. Furthermore, the polishing step and the measuring step are repeated until the thickness t of the embedding resin 5 measured in the measuring step reaches a predetermined thickness T. Line L2 in FIG. 2 is the position of the polished surface formed by repeating the polishing step and the measuring step.

[0027] Fig. 3 is a diagram showing the semiconductor element 3 after completion of the process described in Fig. 2. By polishing the semiconductor element 3 until the thickness t of the embedding resin 5 present on the upper surface of the submount 2 reaches a predetermined thickness T, it is possible to control the distance from the polished surface to the upper surface of the submount 2 so that it is constant, even for the semiconductor element 3.

[0028] As described above, the surface electrodes 10, solder 11, and wiring 12 are included between the semiconductor element 3 and the submount 2, but these are thin, with the combined thickness a of the three layers (hereinafter referred to as the electrode wiring thickness a) being at most about 5 μm. If the electrode wiring thickness a is deemed sufficiently small, it may be ignored, but if the thickness of the semiconductor element 3 is to be strictly controlled, the thickness of the semiconductor element 3 is determined in the measurement process by subtracting the electrode wiring thickness a from the thickness t of the embedding resin 5. By utilizing this relationship, it is possible to polish the semiconductor element 3 so as to leave a desired thickness.

[0029] It is generally considered difficult to directly measure the thickness of the semiconductor element 3 embedded in the embedding resin 5 and determine it with an accuracy of several μm. In contrast, in the present disclosure, the embedding resin 5 on the submount 2, which has a thickness equivalent to that of the polished semiconductor element 3, is observed, and polishing is performed based on the thickness t of the embedding resin 5, thereby making it possible to control the thickness of the semiconductor element 3.

[0030] Here, the predetermined thickness T is determined according to the position of the observation target and the observation method. For example, when the observation method is EL observation, the rear electrode 6 only needs to be removed by polishing, and therefore the predetermined thickness T in the present disclosure is about 70 μm to 80 μm.

[0031] On the other hand, when the observation target is the active layer 4 and cross-sectional observation such as FIB-STEM is performed, it is necessary to process a hole from the polished surface indicated by line L2 to the active layer 4 using an FIB. In this case, the condition for the predetermined thickness T is a thickness that can be processed by FIB without difficulty. Furthermore, it is essential that the thickness is such that the active layer 4 is not damaged by the top surface polishing process. From the above viewpoints, the predetermined thickness T in the present disclosure is, for example, about 10 μm to 20 μm.

[0032] In this manner, in this embodiment, it is possible to provide a method for polishing a semiconductor element 3 that allows thickness control.

[0033] 4 is a diagram showing an EL observation method for a semiconductor element 3 according to the first embodiment. First, in a state in which the back electrode 6 of the semiconductor element 3 has been removed by the above-mentioned polishing process, a positive electrode and ground probe 13 are connected to the polished surface indicated by the line L2. Furthermore, an electric field is applied using the probe 13. This allows light emission 14 to be generated in the active layer 4, and EL observation can be performed.

[0034] Although EL observation is used as an example here, the observation method is not limited to EL observation. For example, cross-sectional observation using a FIB-SEM (Focused Ion Beam-Scanning Electron Microscope) or a FIB-STEM (Focused Ion Beam-Scanning Transmission Electron Microscope) may be used, or a combination of multiple observation methods may be used.

[0035] For example, after performing EL observation to identify deteriorated parts of the active layer 4, the polishing process and the measurement process of the semiconductor element 3 may be further performed, and the deteriorated parts may be observed by FIB-STEM. In this manner, in the present disclosure, a predetermined thickness T corresponding to each of the multiple observation means is set, and the polishing process is performed each time, making it possible to perform multiple observation means. As a result, a more detailed analysis of the semiconductor element 3 is possible.

[0036] Furthermore, in this embodiment, it is possible to provide a method for observing the semiconductor element 3 that can be applied to a semiconductor device mounted on the submount 2 by soldering.

[0037] Here, in order to observe the active layer 4 of the semiconductor element 3 mounted on the submount 2, in addition to the method of polishing the semiconductor element 3 from the back surface 32 side as in the present disclosure, there is also a method of removing the semiconductor element 3 from the submount 2. However, in order to remove the semiconductor element 3 mounted with the solder 11, the solder 11 is melted at a higher temperature than when it was attached, and therefore the semiconductor element 3 may be deteriorated by heating. In addition, there is a risk of the semiconductor element 3 being damaged when it is picked up with tweezers. On the other hand, in the present embodiment, these risks can be avoided.

[0038] Embodiment 2 5 is a diagram showing a polishing method for a semiconductor element 3 according to a second embodiment of the present disclosure. In this embodiment, first, a step of mounting a structure 200 having a predetermined thickness T on the upper surface of a submount 2 of a semiconductor device 100 is performed. The structure 200 is, for example, a metal foil or a glass plate, and is mounted on the submount 2 by soldering or the like. The mounting location of the structure 200 is the upper surface of the submount 2, and by exposing the upper surface of the structure 200 by a polishing step described later, the structure 200 may be mounted anywhere on the semiconductor element 3 as long as the thickness can be controlled.

[0039] Furthermore, the structure 200 and the semiconductor device 100 are sealed with an embedding resin 5. At this time, the structure 200 and at least the submount 2 and the semiconductor element 3 among the components of the semiconductor device 100 are sealed.

[0040] Furthermore, the embedding resin 5 and the semiconductor element 3 are polished from the upper surface until the upper surface of the structure 200 is exposed. A line L1 in Fig. 5 indicates the position of a polished surface formed by the polishing process.

[0041] Fig. 6 is a diagram showing the semiconductor element 3 after completion of the process described in Fig. 5. By polishing the semiconductor element 3 until the upper surface of the structure 200 having a predetermined thickness T is exposed, it is possible to control the distance from the polished surface to the upper surface of the submount 2 for the semiconductor element 3 to be constant. Note that, as described in the first embodiment, the thickness of the semiconductor element 3 is the predetermined thickness T minus the electrode wiring thickness a.

[0042] Furthermore, in this embodiment, by previously arranging the structure 200 serving as an index for thickness on the upper surface of the submount 2, the side surface polishing step described in the first embodiment becomes unnecessary.

[0043] The method of observing the semiconductor element 3 is the same as in the first embodiment, and therefore the explanation will be omitted. This is common to all the following embodiments.

[0044] <Variation 1> Before the polishing step, a side polishing step may be performed to polish the embedding resin 5 so that the side of the structure 200 is exposed from the embedding resin 5. The polishing step is performed while observing the polished surface formed in the side polishing step with an SEM or the like. By observing the structure 200 with an SEM or the like, it is possible to clearly confirm that the upper surface of the structure 200 is exposed, and the embedding resin 5 can be polished without excess or deficiency, compared to observing the structure 200 visually from the top surface. Furthermore, by using the metal structure 200, it is possible to reduce the risk of peeling and charging up of the observation target, compared to the method of observing the embedding resin 5 as in the first embodiment.

[0045] Third embodiment 7 is a diagram showing a method for polishing a semiconductor element 3 according to a third embodiment of the present disclosure. In this embodiment, first, a flat portion 300 having a predetermined thickness T is formed in the wire ball 8 of the semiconductor device 100, and then the flat portion 300 is bonded to the upper surface of the submount 2 via a wiring 9. This process can be performed in the manufacturing process of the semiconductor device 100. The flat portion 300 having the predetermined thickness T can be formed by a capillary method, but the method is not limited thereto. The thickness T of the flat portion 300 of the wire ball 8 has an accuracy of 15 μm to 20 μm.

[0046] The thickness of the wiring 9 is about 1 μm, which can be considered to be sufficiently small compared to the thickness T of the flat portion 300.

[0047] Furthermore, the semiconductor device 100 is sealed with an embedding resin 5. At this time, among the components of the semiconductor device 100, at least the wire balls 8, the submount 2, and the semiconductor element 3 are sealed. Furthermore, the embedding resin 5 and the semiconductor element 3 are polished from above until the upper surface of the flat portion 300 is exposed. Line L1 in FIG. 7 indicates the position of the polished surface formed by the polishing process.

[0048] Fig. 8 is a diagram showing the semiconductor element 3 after the completion of the process described in Fig. 7. By polishing the semiconductor element 3 until the upper surface of the flat portion 300 having a predetermined thickness T is exposed, it is possible to control the distance from the polished surface to the upper surface of the submount 2 for the semiconductor element 3 to be constant, as in the second embodiment. Moreover, since the flat portion 300 in this embodiment is formed in the manufacturing process of the semiconductor device 100, there is no need to separately form the structure 200 as in the second embodiment.

[0049] <Variation 2> As in the first modification, a side surface polishing step may be performed before the polishing step, in which the embedding resin 5 is polished so that the side surface of the flat portion 300 is exposed from the embedding resin 5. Furthermore, the polishing step is performed while observing the polished surface formed in the side surface polishing step with an SEM or the like. This makes it possible to obtain the same effect as in the first modification. Line L2 in FIG. 7 indicates the position of the polished surface formed in the side surface polishing step. Also, FIG. 9 is a diagram showing the semiconductor element 3 after the side surface polishing step and the polishing step are completed.

[0050] Fourth embodiment 10 is a diagram showing a method for polishing a semiconductor element 3 according to a fourth embodiment of the present disclosure. In this embodiment, first, the semiconductor device 100 is encapsulated with a curable embedding resin 5. At this time, among the components of the semiconductor device 100, at least the submount 2 and the semiconductor element 3 are encapsulated. Next, a polishing step is performed in which the embedding resin 5 and the semiconductor element 3 are polished from above.

[0051] Furthermore, a hole 400 reaching the surface 31 is formed from the polished surface of the semiconductor element 3 formed in the polishing process at an oblique angle by FIB or the like. The FIB angle is, for example, 54°, but the numerical value is an example and is not limited thereto. The cross-sectional shape of the hole 400 is triangular, and a vertical cross section of the semiconductor element 3 is exposed on the side surface of the hole 400. Furthermore, a measuring process is performed in which the side surface of the formed hole 400 is observed by SEM or the like, and the depth d of the hole 400 is measured. Furthermore, the polishing process and the measuring process are repeated until the depth d of the hole 400 measured in the measuring process reaches a predetermined depth D. The line L1 in FIG. 10 is a polished surface formed by repeating the polishing process and the measuring process.

[0052] If the thickness of the semiconductor element 3 polished in the polishing step is too large so that the hole 400 cannot be formed from the polished surface of the semiconductor element 3 to reach the front surface 31, the polishing step can be carried out again.

[0053] Fig. 11 is a diagram showing the semiconductor element 3 after completion of the process described in Fig. 10. The depth d of the hole 400 measured in the measurement process corresponds to the thickness of the semiconductor element 3. Therefore, by polishing the semiconductor element 3 until the depth d of the hole 400 becomes a predetermined depth D, the thickness of the semiconductor element 3 can be controlled.

[0054] <Modification> The present disclosure is not limited to the above-described embodiment, and various modifications can be made in the implementation stage without departing from the spirit of the present disclosure. In addition, the embodiments may be implemented in appropriate combination, and in that case, the combined effects can be obtained.

[0055] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; polishing the embedding resin so that a side surface of the support is exposed from the embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; a measuring step of observing a side surface of the polished embedding resin and measuring a thickness of the embedding resin present on the upper surface of the support; Including, The polishing step and the measuring step are repeated until the thickness of the potting resin reaches a predetermined thickness. (Appendix 2) 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: Mounting a structure having a predetermined thickness on an upper surface of the support; encapsulating the structure, the support, and the semiconductor element with an embedding resin; polishing the embedding resin and the semiconductor element from the upper surface until the upper surface of the structure is exposed; A method for polishing a semiconductor element, comprising: (Appendix 3) polishing the embedding resin so that a side surface of the structure is exposed from the embedding resin; an observation step of observing the exposed side surface of the structure; Further comprising: 3. The method for polishing a semiconductor element according to claim 2, wherein the exposure of the top surface of the structure is confirmed by the observation step. (Appendix 4) 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; forming a hole from a polished surface of the semiconductor element to a solder joint surface of the semiconductor element; a measuring step of measuring the depth of the hole; Including, The method for polishing a semiconductor element includes repeating the polishing step and the measuring step until the depth of the hole reaches a predetermined depth. (Appendix 5) 4. The method for polishing a semiconductor element according to claim 2 or 3, wherein the structure is a flat portion of a wire ball joined to the upper surface of the support. (Appendix 6) The method for observing a semiconductor element includes the steps of: A step of carrying out a method for polishing a semiconductor element according to any one of claims 1 to 5; observing an active layer of the semiconductor device; Including, The method for observing a semiconductor element, wherein the predetermined thickness or the predetermined depth is determined depending on the type of observation method for the active layer. [Explanation of symbols]

[0056] REFERENCE SIGNS LIST 1 block, 2 submount, 3 semiconductor element, 4 active layer, 5 embedding resin, 6 back electrode, 7 wire, 8 wire ball, 9 wiring, 10 front electrode, 11 solder, 12 wiring, 13 probe, 14 light emission, 31 front surface, 32 back surface, 200 structure, 100 semiconductor device, 300 flat portion, 400 hole

Claims

1. 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; polishing the embedding resin so that a side surface of the support is exposed from the embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; a measuring step of observing a side surface of the polished embedding resin and measuring a thickness of the embedding resin present on the upper surface of the support; Including, The polishing step and the measuring step are repeated until the thickness of the potting resin reaches a predetermined thickness.

2. 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: Mounting a structure having a predetermined thickness on an upper surface of the support; encapsulating the structure, the support, and the semiconductor element with an embedding resin; polishing the embedding resin and the semiconductor element from the upper surface until the upper surface of the structure is exposed; A method for polishing a semiconductor element, comprising:

3. polishing the embedding resin so that a side surface of the structure is exposed from the embedding resin; an observation step of observing the exposed side surface of the structure; Further comprising:

3. The method for polishing a semiconductor element according to claim 2, wherein the exposure of the upper surface of the structure is confirmed in the observing step.

4. 1. A method for polishing a semiconductor element mounted on a support by soldering, comprising the steps of: encapsulating the support and the semiconductor element with an embedding resin; a polishing step of polishing the embedding resin and the semiconductor element from above; forming a hole from a polished surface of the semiconductor element to a solder joint surface of the semiconductor element; a measuring step of measuring the depth of the hole; Including, The method for polishing a semiconductor element includes repeating the polishing step and the measuring step until the depth of the hole reaches a predetermined depth.

5. 4. The method for polishing a semiconductor element according to claim 2, wherein the structure is a flat portion of a wire ball bonded to the upper surface of the support.

6. The method for observing a semiconductor element includes the steps of: A step of carrying out the method for polishing a semiconductor element according to any one of claims 1 to 4; observing an active layer of the semiconductor device; Including, The method for observing a semiconductor element, wherein the predetermined thickness or the predetermined depth is determined depending on the type of observation method for the active layer.

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