Ceramic electronic component

Abstract

To provide a ceramic electronic component capable of suppressing performance degradation.SOLUTION: A ceramic electronic component includes a laminated chip in which dielectric layers and internal electrode layers are alternately stacked. Between the dielectric layers and the internal electrode layers, concentration peaks of two or more metals different from the main component metal of the internal electrode layers are present at different positions in the stacking direction of the dielectric layers and the internal electrode layers. Between the dielectric layers and the internal electrode layers, an interval from the interface of the internal electrode layers to the concentration peak of a first metal of the two or more metals is equal to or greater than the atomic radius of the first metal and equal to or less than 2 nm.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component. [Background technology]

[0002] As electronic devices become smaller, further miniaturization is also required for ceramic electronic components such as multilayer ceramic capacitors used in electronic devices. To increase the capacitance, which is a basic characteristic, there are three possible methods: (1) increasing the dielectric constant of the dielectric layer, (2) increasing the capacitance-specified area, or (3) making the dielectric layer thinner. When the dielectric constant and element size are fixed, thinner dielectric layers can increase the capacitance per layer. In addition, by making the dielectric layers and internal electrode layers thinner, it is possible to increase the number of layers to be stacked within a given thickness, which is advantageous. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-7562 Summary of the Invention [Problem to be solved by the invention]

[0004] On the other hand, if the dielectric layer is made thinner, the electric field strength applied to the dielectric layer increases even at the same operating voltage, which may result in a decrease in insulation reliability. Also, if the internal electrode layer is made thinner, the continuity ratio of the internal electrode layer may decrease. Thus, there is a risk of a decrease in the performance of the ceramic electronic component.

[0005] In response to these problems, it is possible to suppress the deterioration of the performance of the ceramic electronic component by appropriately selecting multiple metal elements as the metal elements used in the internal electrode layers. However, simply including multiple metal elements in the internal electrode layers may not be enough to suppress the deterioration of the performance of the ceramic electronic component.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a ceramic electronic component that can suppress performance degradation. [Means for solving the problem]

[0007] The ceramic electronic component according to the present invention comprises a laminated chip in which dielectric layers and internal electrode layers are alternately stacked, and is characterized in that, between the dielectric layers and the internal electrode layers, concentration peaks of two or more types of metals different from the main component metal of the internal electrode layers are present at different positions in the stacking direction of the dielectric layers and the internal electrode layers.

[0008] In the ceramic electronic component, the interval between the dielectric layer and the internal electrode layer may be a section from a minimum value of a differential value of a concentration of a constituent metal of the main component ceramic of the dielectric layer to a maximum value of a differential value of a concentration of a constituent metal of the main component ceramic of the dielectric layer when a component element concentration is measured from the internal electrode layer toward the dielectric layer.

[0009] In the ceramic electronic component, the dielectric layer may have a thickness of 0.6 μm or less.

[0010] Between the dielectric layer and the internal electrode layer of the ceramic electronic component, the distance from the interface of the internal electrode layer to the concentration peak of a first metal of the two or more types of metals may be 0.1 nm or more and 2 nm or less.

[0011] Between the dielectric layer and the internal electrode layer of the ceramic electronic component, the distance from the concentration peak of the first metal to the concentration peak of the second metal of the two or more types of metals may be 0.1 nm or more and 2 nm or less.

[0012] Between the dielectric layer and the internal electrode layer of the ceramic electronic component, the distance from the concentration peak of the second metal to the interface of the dielectric layer may be 0.1 nm or more and 2 nm or less.

[0013] In the ceramic electronic component, the main component metal of the internal electrode layers may be Ni.

[0014] In the ceramic electronic component, the dielectric layer may contain barium titanate.

[0015] In the ceramic electronic component, the concentration peaks of the two or more metals may include concentration peaks of Au and Sn.

[0016] A method for manufacturing a ceramic electronic component according to the present invention includes the steps of forming a laminate unit by forming an internal electrode pattern on a dielectric green sheet, forming a laminate by stacking a plurality of the laminate units, and firing the laminate, and is characterized in that, when forming the internal electrode pattern, patterns of two or more types of metal different from the main component metal of the internal electrode pattern are formed in sequence by sputtering on both main surfaces of the internal electrode pattern. [Effects of the Invention]

[0017] According to the present invention, it is possible to provide a ceramic electronic component that can suppress performance degradation. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 4A and 4B are diagrams for explaining details of the vicinity of the boundary between the internal electrode layer and the dielectric layer; [Figure 5] 10(a) to 10(c) are diagrams illustrating the analysis results when the concentration of each element is analyzed line-wise at each sample point along the lamination direction of the dielectric layers and internal electrode layers in a TEM image. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and 1(b) are diagrams illustrating the lamination process. [Figure 8] 10A and 10B are diagrams for explaining in detail the formation of an internal electrode pattern on a dielectric green sheet. [Figure 9] FIG. 1 is a Weibull plot. [Figure 10] FIG. 10 is a diagram showing a continuity rate. [Figure 11] 1(a) is a cross-sectional SEM image of Example 1, and FIG. 1(b) is a cross-sectional SEM image of Example 4. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings.

[0020] (First embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 in accordance with the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0021] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may have the same primary ceramic component as the dielectric layers 11.

[0022] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.110 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.1 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0023] The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sry Ti 1-z Zr z At least one of the following can be selected and used: O3 (0≦x≦1, 0≦y≦1, 0≦z≦1). 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate zirconate.

[0024] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0025] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0026] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0027] To miniaturize and increase the capacitance of the multilayer ceramic capacitor 100, it is preferable to form the dielectric layers 11 thin. For example, the thickness of each dielectric layer 11 is 0.05 μm to 5 μm, or 0.1 μm to 3 μm, or 0.2 μm to 1 μm, or 0.6 μm or less. The thickness of the dielectric layers 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a scanning electron microscope (SEM), measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value for all the measurement points.

[0028] FIG. 4 is a diagram for explaining details of the vicinity of the boundary between the internal electrode layer 12 and the dielectric layer 11. As illustrated in FIG. 4, the internal electrode layer 12 is covered with a first covering layer 17. Furthermore, the first covering layer 17 is covered with a second covering layer 18. For example, the first covering layer 17 is formed on the first main surface, which is one main surface of the internal electrode layer 12 (the upper main surface in FIG. 4), and the second covering layer 18 is formed on the first covering layer 17. Furthermore, the first covering layer 17 is formed below the second main surface, which is the other main surface of the internal electrode layer 12 (the lower main surface in FIG. 4), and the second covering layer 18 is formed below the first covering layer 17. Note that the first covering layer 17 does not necessarily have to cover the entire first and second main surfaces of the internal electrode layer 12, and may partially cover the first and second main surfaces of the internal electrode layer 12. Furthermore, the second coating layer 18 does not necessarily have to cover the entire first coating layer 17, and may cover the first coating layer 17 partially.

[0029] The first covering layer 17 is a layer containing a relatively large amount of a first metal different from the main component metal of the internal electrode layer 12. The second covering layer 18 is also a layer containing a relatively large amount of a second metal different from the main component metal of the internal electrode layer 12. The first metal and the second metal are different. Note that not only a single metal is present in each of the internal electrode layer 12, the first covering layer 17, and the second covering layer 18, but each metal is partially diffused in each layer. The main component metal of the internal electrode layer 12 may be a base metal such as nickel (Ni) or copper (Cu), or may be a precious metal.

[0030] 5(a) to 5(c) are diagrams illustrating analysis results when a line analysis of each component element concentration is performed on each sample point in a TEM image along the lamination direction of the dielectric layer 11 and the internal electrode layer 12. In the example of Fig. 5(a) to 5(c), as an example, Ni is used as the main component metal of the internal electrode layer 12, the first coating layer 17 contains a relatively large amount of gold (Au), the second coating layer 18 contains a relatively large amount of tin (Sn), and barium titanate is used as the main component ceramic of the dielectric layer 11.

[0031] In Figure 5(a), the horizontal axis represents the distance in the stacking direction, and the vertical axis represents the concentration (at%) of each component. The "0 nm" on the horizontal axis indicates the predicted interface between the internal electrode layer 12 and the first coating layer 17. As the distance on the horizontal axis increases, the stacking direction approaches the dielectric layer 11. As illustrated in Figure 5(a), at a distance of "0 nm," the concentration of Ni, the main metal component of the internal electrode layer 12, is highest. As the distance approaches the dielectric layer 11, the Ni concentration decreases, peaks appear in the Au and Sn concentrations, and the titanium (Ti) and oxygen (O) concentrations increase. Note that the example in Figure 5(a) has been smoothed by averaging over nine points to reduce noise.

[0032] FIG. 5(b) shows the results of differentiating the Ni concentration and Ti concentration in FIG. 5(a). By identifying the point of the steepest change, the interface of the internal electrode layer 12 and the interface of the dielectric layer 11 can be identified. In the example of FIG. 5(b), the position where the differential value of the Ni concentration is the smallest is the interface of the internal electrode layer 12. Also, the position where the differential value of the Ti concentration is the largest is the interface of the dielectric layer 11. This means that a large amount of Au and Sn is present between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12.

[0033] FIG. 5(c) is a graph showing the results of FIG. 5(a) with the vertical axis plotted logarithmically. As illustrated in FIG. 5(c), Au concentration peaks and Sn concentration peaks appear between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12. The Au concentration peak is located closer to the Ni interface than the Sn concentration peak. The Sn concentration peak is located closer to the Ti interface than the Au concentration peak. Thus, between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12, the concentration peak of the first metal contained in the first coating layer 17 and the concentration peak of the second metal contained in the second coating layer 18 are located at different positions in the stacking direction of the dielectric layer 11 and the internal electrode layer 12. Specifically, the concentration peak of the first metal is located closer to the interface of the internal electrode layer 12, and the concentration peak of the second metal is located closer to the interface of the dielectric layer 11.

[0034] According to this configuration, the effects of the first metal and the second metal are exerted individually. For example, if the first metal exerts an effect of suppressing a decrease in the reliability of the dielectric layer 11 and the second metal exerts an effect of suppressing a decrease in the continuity ratio of the internal electrode layer 12, the effect of suppressing a decrease in the reliability and the effect of suppressing a decrease in the continuity ratio are enhanced compared to when an alloy layer in which the first metal and the second metal are uniformly mixed is provided. Furthermore, if the first metal exerts an effect of suppressing a decrease in the reliability of the dielectric layer 11 and the second metal also exerts an effect of suppressing a decrease in the reliability of the dielectric layer 11, the effect of suppressing a decrease in the reliability is enhanced compared to when an alloy layer in which the first metal and the second metal are uniformly mixed is provided. In this way, the effects of the first metal and the second metal are exerted individually, thereby suppressing a decrease in the performance of the multilayer ceramic capacitor 100. This effect is particularly exerted when the dielectric layer 11 is formed thin (for example, 0.6 μm or less) and insulation properties are not sufficiently ensured. It should be noted that the amount of precious metal used can be reduced by combining a precious metal with a base metal or by combining base metals as the first metal and the second metal.

[0035] When Ni or Cu is used as the main component metal of the internal electrode layer 12, for example, metals that suppress a decrease in the insulation reliability of the dielectric layer 11 include arsenic (As), Au, cobalt (Co), chromium (Cr), Cu, iron (Fe), indium (In), iridium (Ir), magnesium (Mg), osmium (Os), palladium (Pd), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), selenium (Se), Sn, tellurium (Te), tungsten (W), yttrium (Y), and zinc (Zn).

[0036] When Ni or Cu is used as the main component metal of the internal electrode layer 12, for example, metals that suppress a decrease in the continuity ratio of the internal electrode layer 12 include silver (Ag), Cr, Ir, Mg, molybdenum (Mo), Os, Pd, Pt, Re, Rh, Ru, Y, W, etc.

[0037] When Ni or Cu is used as the main component metal of the internal electrode layer 12, examples of metals that have the effect of barriering diffusion between the internal electrode layer 12 and the dielectric layer 11 include tantalum (Ta) and Ti.

[0038] When Ni or Cu is used as the main component metal of the internal electrode layer 12, examples of metals that ensure adhesion between the internal electrode layer 12 and the dielectric layer 11 include Cr, Ta, and Ti.

[0039] When Ni or Cu is used as the main component metal of the internal electrode layer 12 and a perovskite oxide such as barium titanate is used as the main component ceramic of the dielectric layer 11, for example, Cu can be used as a metal that reduces the lattice mismatch between the internal electrode layer 12 and the dielectric layer 11.

[0040] To form one layer of the first metal, a distance at least equal to the atomic radius of the first metal is required. Therefore, it is preferable to set a lower limit for the distance from the interface of the internal electrode layer 12 to the concentration peak of the first metal in the stacking direction. On the other hand, if the distance is too large, the effect begins to saturate. Therefore, it is preferable to set an upper limit for the distance. In the stacking direction, the distance from the interface of the internal electrode layer 12 to the concentration peak of the first metal is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, or 0.1 nm to 1 nm. In the stacking direction, the distance from the concentration peak of the first metal to the concentration peak of the second metal is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, or 0.1 nm to 1 nm. In the stacking direction, the distance from the concentration peak of the second metal to the interface of the dielectric layer 11 is, for example, 0.1 nm to 2 nm, 0.1 nm to 1.5 nm, or 0.1 nm to 1 nm. Although the above example shows a case where there are two types of concentration peaks, the same intervals are also observed when multiple peaks exist.

[0041] The thickness of the internal electrode layers 12 is, for example, 10 nm or more and 1000 nm or less, 20 nm or more and 500 nm or less, or 50 nm or more and 300 nm or less. The thickness of the internal electrode layers 12 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with an SEM, measuring the thickness at 10 points for each of 10 different internal electrode layers 12, and deriving the average value of all the measurement points.

[0042] The number of metals whose concentration peaks appear at different positions in the stacking direction between the internal electrode layer 12 and the dielectric layer 11 is not limited to two. Three or more metal concentration peaks may appear at different positions in the stacking direction between the internal electrode layer 12 and the dielectric layer 11. In this case, the respective effects of the three or more metals can be obtained.

[0043] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0044] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0045] The resulting ceramic powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of Mg, manganese (Mn), vanadium (V), Cr, rare earth elements (Y, samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing Co, Ni, lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0047] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0048] Next, as illustrated in Fig. 7(a), internal electrode patterns 53 are formed on the dielectric green sheet 52. In Fig. 7(a), as an example, four layers of internal electrode patterns 53 are formed at predetermined intervals on the dielectric green sheet 52. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is defined as a lamination unit.

[0049] Next, while peeling off the dielectric green sheet 52 from the substrate 51, the lamination units are laminated as shown in FIG. 7(b).

[0050] Next, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are laminated on top and bottom of the laminate obtained by laminating the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 7(b), cutting is performed along the dotted lines. The cover sheet 54 may have the same components as the dielectric green sheet 52, or may contain a different additive compound.

[0051] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping. -5 ~10 -8 The mixture is then fired in a reducing atmosphere at 1100 to 1300° C. for 10 minutes to 2 hours at 1 atm. In this way, the multilayer ceramic capacitor 100 is obtained.

[0052] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0053] (Plating process) Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

[0054] FIG. 8 is a diagram for explaining in detail the formation of the internal electrode pattern 53 on the dielectric green sheet 52. As illustrated in FIG. 8, a first pattern 55 of a first metal relatively abundant in the first coating layer 17 is formed by sputtering on both main surfaces of the internal electrode pattern 53, and a second pattern 56 of a second metal relatively abundant in the second coating layer 18 is formed by sputtering on the first pattern 55. For example, the second pattern 56 is formed by sputtering on the dielectric green sheet 52. Next, the first pattern 55 is formed by sputtering on the second pattern 56. Next, the internal electrode pattern 53 is formed by sputtering on the first pattern 55. Next, the first pattern 55 is formed by sputtering on the internal electrode pattern 53. Next, the second pattern 56 is formed by sputtering on the first pattern 55.

[0055] According to the manufacturing method of the multilayer ceramic capacitor 100 of this embodiment, by forming each pattern by sputtering as shown in FIG. 8, mixing of the metals of each layer is suppressed. As a result, even if the metals diffuse into each other during the firing process, a structure such as that illustrated in FIG. 4 is obtained near the interface of the internal electrode layer 12 obtained after the firing process. In this case, when the element concentration is analyzed line-by-line at each sample point along the stacking direction in the TEM image, the concentration peak of the second metal contained relatively in large amounts in the first coating layer 17 and the concentration peak of the second metal contained relatively in large amounts in the second coating layer 18 are located at different positions between the interface of the internal electrode layer 12 and the interface of the dielectric layer 11. As a result, the effects of the first metal and the second metal are exerted individually.

[0056] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0057] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0058] Example 1 Additives were added to barium titanate powder, which was then thoroughly wet-mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder and toluene and ethyl alcohol solvents were added to the dielectric material, and the dielectric green sheet was then coated onto a PET substrate using the doctor blade method. A 200 nm thick pattern was formed on the surface of the dielectric green sheet by sputtering. To create a dissimilar metal coating layer on the Ni surface layer of the internal electrode pattern, Au and Sn layers were separately deposited before and after the Ni layer deposition. The Au and Sn layers were 1 nm thick on both the front and back, while the Ni layer was 196 nm thick. A metal mask method was used for patterning. One hundred dielectric green sheets with internal electrode patterns were stacked so that the internal electrode patterns were alternately offset, cut to the specified size, and the two end faces where the internal electrode patterns were exposed were coated with a metal conductive paste for the external electrodes. The resulting multilayer ceramic capacitor was then fired.

[0059] The composition of the obtained multilayer ceramic capacitor near the boundary between the dielectric layer and the internal electrode layer was analyzed using a scanning transmission electron microscope (STEM-EDS). Variation in the measurement data was averaged out by averaging approximately nine points. The interface was defined as the location where the concentration change was most abrupt in the region spanning the boundary. In other words, the interface was defined as the location showing the maximum / minimum value of the distance derivative of the concentration. The interface positions extracted using the above procedure for Ni and Ti were different, with a spacing of approximately 0.5 nm. The concentrations of Au and Sn both had maximum peaks, with the peak positions located between the Ni and Ti interfaces. The peak positions were different from each other, and in this element, the spacing was approximately 0.2 nm.

[0060] Example 2 In Example 2, a 1 nm thick Fe layer was deposited by sputtering instead of the 1 nm thick Sn layer. Other conditions were the same as in Example 1. In Example 2, concentration peaks of Au and Fe were observed at different positions between the Ni and Ti interfaces.

[0061] Example 3 In Example 3, a 1 nm thick Cr layer was deposited by sputtering instead of the 1 nm thick Sn layer. Other conditions were the same as in Example 1. In Example 3, concentration peaks of Au and Cr were observed at different positions between the Ni and Ti interfaces.

[0062] Example 4 In Example 4, the coating layer consisted of three layers. Before and after forming a 194 nm Ni layer, a 1 nm Au layer, a Cr layer, and a Sn layer were formed by sputtering. The other conditions were the same as in Example 1. In Example 4, concentration peaks of Au, Cr, and Sn were observed at different positions between the Ni and Ti interfaces.

[0063] (Comparative Example 1) In Comparative Example 1, when forming the internal electrode pattern, a 200 nm Ni film was formed, and no Au or Sn coating layer was formed. The other conditions were the same as in Example 1.

[0064] (Comparative Example 2) In Comparative Example 2, when forming the internal electrode pattern, a 198 nm Ni layer was formed, and a 1 nm Au layer of the first metal was formed before and after the Ni layer formation. Other conditions were the same as in Example 1.

[0065] For Examples 1 to 4 and Comparative Examples 1 and 2, a 125°C / 18V HALT (Highly Accelerated Lifetime) test was performed to measure the dielectric breakdown life. FIG. 9 is a Weibull plot showing the relationship between the time to failure and the cumulative failure rate for Example 1 and Comparative Examples 1 and 2. As shown in FIG. 9, it can be seen that the dielectric breakdown life is longer in Example 1 and Comparative Example 2 compared to Comparative Example 1. This is thought to be because both Au and Sn have the effect of improving life. The dielectric breakdown life is further extended in Example 1 compared to Comparative Example 2. This is thought to be because both Au and Sn coating layers are formed. However, since the difference between the dielectric breakdown life of Comparative Example 2 and Example 1 is larger than the difference between the dielectric breakdown life of Comparative Example 1 and Comparative Example 2, it is thought that a synergistic effect is obtained in the extension width due to the presence of concentration peaks of both Au and Sn at different positions between the dielectric layer and the internal electrode layer.

[0066] For Examples 1 to 4 and Comparative Examples 1 and 2, if the lifespan was at least one order of magnitude longer than that of Comparative Example 1, the reliability was judged to be very good (◎); if the lifespan was several times longer than that of Comparative Example 1, the reliability was judged to be good (◯); and if the lifespan was equal to or shorter than that of Comparative Example 1, the reliability was judged to be poor (×).

[0067] Next, the continuity ratios of the internal electrode layers were measured for Examples 1 to 4 and Comparative Examples 1 and 2. FIG. 10 is a diagram showing the continuity ratios. As illustrated in FIG. 10, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, . . . , Ln of the metal portions are measured and summed, and the ratio of the metal portions, ΣLn / L0, can be defined as the continuity ratio of that layer. FIG. 11(a) is a cross-sectional SEM image of Example 1. FIG. 11(b) is a cross-sectional SEM image of Example 4. In FIGS. 11(a) and 11(b), the shaded portions 19 are discontinuous portions of the internal electrode layers 12. Cr is known to be effective in suppressing fractures of the internal electrode layers 12. A comparison between FIG. 11(a) and FIG. 11(b) confirms a clear difference in the continuity ratios of the internal electrode layers 12, and it can be understood that the continuity ratio is improved by disposing Cr between the dielectric layer 11 and the internal electrode layer 12. In Example 1, the continuity ratio was measured to be 70%. In Example 2, the continuity ratio was measured to be 68%. In Example 3, the continuity ratio was measured to be 95%. In Example 4, the continuity ratio was measured to be 92%. In Comparative Example 1, the continuity ratio was measured to be 75%. In Comparative Example 2, the continuity ratio was measured to be 65%.

[0068] For Examples 1 to 4 and Comparative Examples 1 and 2, if at least the reliability was judged to be very good "◎", it was judged as passing. Even if the reliability was judged to be good "◯", if the continuity rate was above 65%, it was judged as passing. Even if the reliability was judged to be good "◯", if the continuity rate was 65% or less, or if the reliability was judged to be poor "×", it was judged as failing. The results are shown in Table 1. [Table 1]

[0069] Examples 1 to 4 were judged to be acceptable. For Example 1, it is believed that sufficient reliability was achieved because the concentration peaks of Au and Sn, which suppress degradation of insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer. For Example 2, it is believed that sufficient reliability was achieved because the concentration peaks of Au and Fe, which suppress degradation of insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer. For Example 3, it is believed that reliability was improved and the continuity rate was increased because Au and Cr were disposed between the dielectric layer and the internal electrode layer and their concentration peaks were located at different positions. For Example 4, it is believed that sufficient reliability was achieved because the concentration peaks of Au and Sn, which suppress degradation of insulation reliability, were located at different positions between the dielectric layer and the internal electrode layer, and furthermore, the continuity rate was increased because the concentration peak of Cr was located at different positions. Regarding the sputtering film formation method shown in each example, the order of sputtering of two or more metals used may be reversed.

[0070] In contrast, Comparative Example 1 was judged to be unsuccessful. This is thought to be because sufficient reliability was not obtained because a metal that suppresses a decrease in insulation reliability was not arranged between the dielectric layer and the internal electrode layer. Comparative Example 2 was judged to be unsuccessful. This is thought to be because sufficient reliability was not obtained because only one type of metal that suppresses a decrease in insulation reliability was arranged between the dielectric layer and the internal electrode layer.

[0071] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0072] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitors

Claims

1. The laminated chip is provided with dielectric layers and internal electrode layers alternately laminated, Between the dielectric layers and the internal electrode layers, concentration peaks of two or more types of metals different from the main component metal of the internal electrode layers are present at different positions in the lamination direction of the dielectric layers and the internal electrode layers, A ceramic electronic component characterized in that, between the dielectric layer and the internal electrode layer, a distance from the interface of the internal electrode layer to a concentration peak of a first metal among the two or more types of metals is equal to or greater than the atomic radius of the first metal and is 2 nm or less.

2. 2. The ceramic electronic component according to claim 1, wherein the interval between the dielectric layer and the internal electrode layer is a section from a minimum value of a differential value of a concentration of a main component metal of the internal electrode layer to a maximum value of a differential value of a concentration of a constituent metal of the main component ceramic of the dielectric layer, when the component element concentration is measured from the internal electrode layer toward the dielectric layer.

3. 3. The ceramic electronic component according to claim 1, wherein the thickness of the dielectric layer is 0.6 μm or less.

4. 4. The ceramic electronic component according to claim 1, wherein a distance from an interface of the internal electrode layer to a concentration peak of a first metal among the two or more types of metals between the dielectric layer and the internal electrode layer is 0.1 nm or more.

5. 5. The ceramic electronic component according to claim 4, wherein, between the dielectric layer and the internal electrode layer, a distance from a concentration peak of the first metal to a concentration peak of a second metal among the two or more types of metals is 0.1 nm or more and 2 nm or less.

6. 6. The ceramic electronic component according to claim 5, wherein a distance from the concentration peak of the second metal to an interface of the dielectric layer between the dielectric layer and the internal electrode layer is 0.1 nm or more and 2 nm or less.

7. 7. The ceramic electronic component according to claim 1, wherein the main component metal of the internal electrode layers is Ni.

8. 8. The ceramic electronic component according to claim 1, wherein the dielectric layer contains barium titanate.

9. 9. The ceramic electronic component according to claim 1, wherein the concentration peaks of the two or more metals include concentration peaks of Au and Sn.

10. The ceramic electronic component according to claim 1 , wherein the two or more types of metals include at least Ta or Ti.

11. 9. The ceramic electronic component according to claim 1, wherein the two or more types of metals include at least Cr, Ta, or Ti.

12. The ceramic electronic component according to claim 1 , wherein the two or more types of metals include at least Cu.

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