Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy

A synchronous digital system and delay compensation technology, applied in the field of communication, can solve the problems of high overhead time, complex operation timing, low compensation cache efficiency, etc., to achieve the effect of improving efficiency and reducing useless overhead

Inactive Publication Date: 2013-08-07
ZTE CORP
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Problems solved by technology

That is, due to the complex operation sequence of SDRAM, it may take a lot of overhead time during operation, resulting in generally low efficiency of compensation cache

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  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy
  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy
  • Method and device for improving virtual concatenation delay compensation caching efficiency in synchronous digital hierarchy

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Embodiment Construction

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

[0037] Embodiments of the present invention provide a method for delay compensation and alignment buffering of multipath transmitted VC members at the receiving end of VCG in SDH equipment, by establishing a corresponding relationship between the multiplexing path of VC and the Bank storage area in SDRAM, According to the VC multiplexing relationship, the read and write operation requests of each VC are polled and dispatched to the SDRAM controller for processing. The characteristics of concurrent operations in different Bank areas of SDRAM can be used...

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Abstract

A method for improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer is disclosed. The method comprises: mapping the virtual containers (VCs) to the Banks of the synchronous dynamic random access memory SDRAM; writing the SDRAM write requests of the VCs into the write request first in first out (FIFO) registers of the corresponding VCs respectively; polling the write request and the read request FIFO registers of the VCs. The present invention also provides an apparatus for improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer. The present invention can reduce the invalid overhead of the SDRAM operation; thereby improve the efficiency of the SDH virtual concatenation delay compensation buffer.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a method and device for improving VCG (Virtual Concatenation Group, Virtual Concatenation Group) delay compensation buffer efficiency in SDH (Synchronous Digital Hierarchy, Synchronous Digital Hierarchy) equipment. Background technique [0002] As the mainstream equipment of the current transport network, SDH equipment has been widely used in the communication field. Its standard VC12 (low-order virtual container), VC3 (high-order virtual container), and VC4 (high-order virtual container) containers can be used to carry E1, E3 / T3, E4 and other fixed-bandwidth TDM (time division multiplexing) services, so the demand for VC (Virtual Container, virtual container) cascading is not strong, but with the rapid development of data services, SDH equipment carries data services become a problem that must be solved. [0003] One of the characteristics of data services is the...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/46H04J3/16
CPCH04J3/0623H04J2203/0094G06F12/00H04J3/00
Inventor 冯景斌
Owner ZTE CORP
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