Flash memory and access control method for internal data of flash memory
A technology of access control and internal data, which is applied to the access control of internal data in flash memory, and in the field of flash memory, it can solve the problems of no flash data storage characteristics, additional and efficient use of flash memory storage space, etc.
Active Publication Date: 2019-11-05
BYD SEMICON CO LTD
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Problems solved by technology
[0003] However, the above-mentioned access control method of flash memory data has certain shortcomings: the efficiency of the current control method depends on the timing control characteristics of the flash memory body, and the fastest access speed must also meet the minimum access time requirement of the memory itself; at the same time , using the cache method to improve the access speed of the system requires additional data cache control algorithms and additional cache storage space, and improper cache control algorithms may reduce the access efficiency
Further, the above-mentioned control method limits the effective utilization of the storage space of the flash memory to a certain extent, and does not efficiently utilize the storage space of the flash memory according to the storage characteristics of the flash memory data
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[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
[0030] In the description of the present invention, it should be understood that the terms "first" and "second" are used for description purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.
[0031] In the descr...
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In a flash memory disclosed by the invention, first data and a first address of the first data are stored in a memory body, second data is stored in a data set unit, and a second address of the second data in the memory body is stored in an address table unit. A control module judges whether a visit address is matched with the first address or the second address, and if the visit address is matched with the first address, the control module reads the first data according to an access control logic of the memory. If the visit address is matched with the second address, the control module directly reads the second data. In the flash memory provided by the invention, the control module can rapidly read the second data, so that a flash memory data reading speed of the embedded system is enhanced, meanwhile direct interaction between an external system and the memory body can also be reduced, times and a process length of data relay are reduced, and an error probability of data transmission is reduced. The invention also discloses an access control method for the data in the memory.
Description
technical field [0001] The present invention relates to the field of data access, more specifically, to a flash memory and an access control method for internal data in the flash memory. Background technique [0002] The access speed and access space utilization of the internal flash memory of the embedded system often limit the performance and efficiency of the embedded system. An efficient flash memory data access control method can greatly improve the efficiency indicators of system program operation and data processing. The data access control method of flash memory in the current embedded system is generally unified, that is, according to the access timing characteristics of the flash memory itself, the corresponding memory access timing control logic is designed to perform general access read and write operations; the data access timing Try to design the minimum value of the timing time required by the memory to improve memory access efficiency. Or, add cache logic ou...
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IPC IPC(8): G06F12/02
Inventor 周博郭平日李奇峰杨云
Owner BYD SEMICON CO LTD