A memory word line selection circuit capable of reducing voltage difference, a chip and a memory

A word line selection and memory technology, used in static memory, read-only memory, information storage, etc., can solve the problems of large difference between positive and negative voltage, reduce circuit reliability and durability, and influence of MOS tube, and reduce the voltage difference. , The effect of improving circuit reliability and durability

Pending Publication Date: 2019-03-08
合肥博雅半导体有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In the memory circuit, the output voltage of the word line selection circuit can be positive voltage or negative voltage, while the output voltage range of the traditional word line selection circuit is relatively wide, and the difference between positive and negative voltages is large. When the output terminal (WordLine, referred to as WL) switches the voltage, it is easy to affect the MOS tube in the circuit, reducing the reliability and durability of the circuit

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  • A memory word line selection circuit capable of reducing voltage difference, a chip and a memory
  • A memory word line selection circuit capable of reducing voltage difference, a chip and a memory
  • A memory word line selection circuit capable of reducing voltage difference, a chip and a memory

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Embodiment Construction

[0017] refer to figure 1 One embodiment of the present invention provides a memory word line selection circuit for reducing voltage difference, including three P-type MOS transistors and three N-type MOS transistors, the three P-type MOS transistors are MP0, MP1 and MP2, the three N-type mos tubes are MN0, MN1 and MN2 respectively, the drain of the MP0 and the MP1 and the drain are connected to the source of the MP2, the drain of the MN0 and the MN1 and the drain Both are connected to the source of the MN2, the drain of the MP2 is connected to the drain of the MN2 and leads to the word line signal output terminal WL, and the gate of the MP2 and the gate of the MN2 are respectively used as the word line control input terminal PVmid and NVmind.

[0018] The three P-type MOS transistors and the three N-type MOS transistors in this embodiment are symmetrically distributed about the word line signal output end, and the turn-on and cut-off of the corresponding MOS transistors are c...

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Abstract

The invention discloses a memory word line selection circuit capable of reducing voltage difference, a chip and a memory. The circuit comprises three P-type mos tubes and three N-type mos tubes, the three P-type mos tubes are respectively MP0, MP1 and MP2, the three N-type mos tubes are respectively MN0, MN1 and MN2, the drain electrodes of the MP0 and the MP1 are both connected to the source electrode of the MP2; the drain electrode of the MN0, the drain electrode of the MN1 are both connected to the source electrode of the MN2, the drain electrode of the MP2 and the drain electrode of the MN2 are connected, a word line signal output end WL is led out, and the grid electrode of the MP2 and the grid electrode of the MN2 serve as the word line control input end PVmid and an NVmin respectively. The voltage difference of the MOS transistor in the circuit can be effectively reduced, and the MOS transistor is protected, so that the reliability and the durability of the circuit are improved.

Description

technical field [0001] The invention relates to a memory word line circuit, in particular to a memory word line selection circuit for reducing voltage difference, a chip and a memory. Background technique [0002] In the memory circuit, the output voltage of the word line selection circuit can be positive voltage or negative voltage, while the output voltage range of the traditional word line selection circuit is relatively wide, and the difference between positive and negative voltages is large. When the output terminal (WordLine, WL for short) switches the voltage, it is easy to affect the MOS tube in the circuit, reducing the reliability and durability of the circuit. Contents of the invention [0003] In order to solve the above problems, the present invention provides a memory word line selection circuit with reduced voltage difference, which can effectively reduce the voltage difference of MOS transistors in the circuit and protect the MOS transistors, thereby improv...

Claims

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Application Information

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IPC IPC(8): G11C16/08
CPCG11C16/08
Inventor张登军安友伟余作欢李建球杨小龙刘大海张亦锋李迪陈晓君逯钊琦
Owner合肥博雅半导体有限公司