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A dynamic shared buffer device for interconnected chips

A technology of dynamic sharing and buffering devices, applied in instruments, computers, calculations, etc., can solve problems such as layout and wiring difficulties

Active Publication Date: 2021-12-24
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a large number will cause great difficulty in the layout and routing of the back end

Method used

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  • A dynamic shared buffer device for interconnected chips
  • A dynamic shared buffer device for interconnected chips
  • A dynamic shared buffer device for interconnected chips

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Embodiment Construction

[0052] In order to reduce the complexity of high data bit width DAMQ in the back-end physical design, the present invention provides a dynamic shared buffer device for interconnected chips, which can reduce the difficulty of back-end layout and wiring by separating the control information and data in the message, and Reduce physical design costs.

[0053] Such as figure 2 As shown, the interconnection chip dynamic shared buffering device of the present invention includes: message splitting module, control code combination module, data DAMQ and control DAMQ; Note control DAMQ is DAMQ_CTRL, data DAMQ is DAMQ_DATA, has a data input port, a read A request input port and a data output port.

[0054] The message splitting module is connected with the data input port, the control code combination module, and DAMQ_DATA, receives the message from the data input port, splits the message into message data and message control information, and then outputs the message data to DAMQ_DATA ...

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Abstract

Aiming at the technical problem that the high data bit width DAMQ in the existing supercomputer high-speed interconnection network switch is too complex in the back-end physical design, the present invention provides an interconnection chip dynamic shared buffer device, including: message splitting module, control Code combination module, data DAMQ and control DAMQ, a data input port, a read request input port and a data output port; record the control DAMQ as DAMQ_CTRL, and the data DAMQ as DAMQ_DATA. In the present invention, by separating the control information and data in the message, the message will be split into two parts when written into DAMQ, wherein the message data part is written into DAMQ_DATA, and the control information and message data of the message are stored in DAMQ_DATA The addresses in the control code are combined and written into DAMQ_CTRL, and DAMQ_CTRL reads the message data from DAMQ_DATA through the address in the control code. The invention can reduce the number of registers required by DAMQ to about 2% of the prior art, greatly reduce the difficulty of back-end layout and wiring, and reduce the cost of physical design.

Description

technical field [0001] The invention relates to an input buffer of an input port of a high-speed interconnection network switch of a supercomputer, in particular to a dynamic sharing buffer device for an interconnection chip. Background technique [0002] The interconnection network is a key component of a supercomputer, which is used to realize high-speed data transmission and exchange among computing nodes, input and output nodes, and service nodes in a supercomputer. [0003] A switch is the core device of a high-speed interconnection network, and is generally realized by a crossbar switch. The internal structure of the switch mainly includes a data buffer and a crossbar. The data buffer is used to cache data that cannot be processed in time, and the crossbar is used to exchange data between different network ports. Commonly used data buffering methods in switches include: input buffering, output buffering, combined input and output buffering, cross-point buffering, etc....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/08G06F15/173G06F12/084
CPCG06F15/173G06F12/084H04L67/568
Inventor 肖立权黎渊常俊胜赖明澈齐星云戴艺肖灿文徐金波孙岩欧洋熊泽宇
Owner NAT UNIV OF DEFENSE TECH