Automatic test circuit for variable bit width memory in programmable logic device

Abstract

The present invention discloses an automatic test circuit for a variable bit width memory in a programmable logic, including an address data generator, a bit width selector and a variable bit width comparator; the address data generator is used to automatically generate a 15-bit sequence that can automatically flip address signals and data, write enable signals, and transmit them to the bit width selector; after the bit width selector receives the signal from the address data generator, it converts the received signal according to the bit width selection situation, and transmits the converted signal to each memory to be tested; the variable bit width comparator is used to receive the output data signal from the memory to be tested, convert the signal according to the selected bit width, and compare the converted signal, and output the result after obtaining the test result. The present invention can use less circuit structures to realize automatic full traversal test of programmable logic embedded memory, and can select a suitable bit width for testing according to the memory width, and has high test efficiency and flexibility.

Description

Technical Field

[0001] The invention relates to an automatic testing circuit for variable bit width memory in programmable logic, and in particular to a circuit for automatically testing a 36Kb memory configured with different bit widths in programmable logic using a MarchC algorithm, and belongs to the field of integrated circuits. Background Art

[0002] Memory resources are important resources in electronic systems. Memory is needed in the system for input data buffering, intermediate data temporary storage, output result storage and access, etc. A large number of variable bit width memories are usually configured on programmable logic devices to achieve flexible configuration of the device, high speed, and large-scale data processing tasks. It is the most important circuit module to ensure the high performance of the device.

[0003] After the programmable logic device completes the front-end design, tape-out production, packaging and other processes, the device needs to be tested to verify the accuracy of the front-end design, ensure the normal function of the device, and avoid the delivery of defective products to users. As the scale of programmable logic devices gradually increases, more and more memory modules are embedded. Usually, in order to achieve the flexible and configurable characteristics of the device, the embedded memory supports variable bit width functions. How to complete high coverage and high accuracy testing of all memories under different bit width configurations has become an urgent problem to be solved. In the case where manual testing is prone to errors, it is necessary to use automatic testing methods to complete the memory testing work.

[0004] Traditional testing methods include CRC check, Hamming code check, etc. These methods all use specific check algorithms to check whether there are errors in the memory output data. However, no matter which check algorithm is used, complex logic circuits will be used, and in order to ensure accuracy, the memory modules can only be tested one by one in serial mode, which takes up a lot of system resources and test time. In addition, the two test methods can only test one bit width of the memory. When the memory bit width changes, the test circuit needs to be redesigned, which cannot meet the flexibility requirements of programmable logic devices. Therefore, it is necessary to design an efficient test circuit that can run automatically to achieve fast and accurate testing of the memory in the programmable logic device. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects and provide an automatic testing circuit for variable bit width memories in programmable logic, which can realize automatic testing operations of memories with various bit widths, compare the test results, and output the final test results, thereby ensuring the accuracy of the device function and improving the efficiency of device testing, thereby meeting the needs of fast, accurate and comprehensive device testing.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] An automatic test circuit for a variable bit width memory in a programmable logic device, comprising an address data generator, a bit width selector and a variable bit width comparator;

[0008] The address data generator automatically generates the signals required for memory testing according to the externally input clock signal and reset signal and outputs them to the bit width selector; the signals required for memory testing include a 1-bit data signal, a 1-bit write enable signal and a 15-bit address signal;

[0009] The bit width selector selects an address signal, a data signal and a write enable signal corresponding to the memory bit width according to an external input selection signal, and transmits the selected address signal, data signal and write enable signal to the memory to be tested;

[0010] The variable bit width comparator reads a data signal corresponding to the memory bit width from the memory to be tested according to an external input selection signal, processes the data signal and compares the obtained processing results, and outputs the test results after obtaining them.

[0011] Furthermore, the address data generator changes the address signal from a positive sequence to a reverse sequence each time a cycle is completed.

[0012] Furthermore, the method for the address data generator to automatically generate the signal required for the memory test according to the externally input clock signal and reset signal is as follows:

[0013] When the reset signal RST is 0 and the clock signal CLK is a square wave, the address data generator starts working, generates continuous address signals, write enable signals and data signals and outputs them to the outside. When RST is 1, the address data generator is disabled and reset. When RST becomes 0, the address data generator starts generating signals again.

[0014] Furthermore, the input ports of the address data generator include a CLK input port and a RST input port, which are used to input a clock signal and a reset signal respectively; the output ports of the address data generator include an A[14:0] output port, a WE' output port and a DATA output port, which are used to output an address signal, a write enable signal and a data signal respectively.

[0015] Further, the address data generator includes 18 registers K4 to K21, 18 inverters K22 to K39 and 15 multiplexers K40 to K54;

[0016] The input port CLK is connected to the CLK port of register K4;

[0017] The input port RST is connected to the RST ports of registers K4 to K21 respectively;

[0018] The Q ports of registers K4 to K21 are respectively connected to the input terminals of inverters K22 to K39, and the Q ports of registers K4 to K18 are respectively connected to the first input terminals of multiplexers K40 to K54; the output terminals of inverters K22 to K39 are respectively connected to the D ports of registers K4 to K21, and the output terminals of inverters K22 to K36 are respectively connected to the second input terminals of multiplexers K40 to K54; the control ports of multiplexers K40 to K54 are connected to the Q port of register K21;

[0019] The D ports of registers K4 to K20 are connected to the CLK ports of registers K5 to K21 respectively;

[0020] The output ports of multiplexers K40 to K54 are output ports A

[14] to A[0] respectively;

[0021] The Q port of the register K19 is the output port WE', and the Q port of the register K20 is the output port DATA.

[0022] Furthermore, the bit width selector includes 6 control ports, 17 input ports and 52 output ports; the control port S[5:0] is used to input an external selection signal; the input ports include an A_in[14:0] input port, a WE' input port and a DATA input port, which are respectively used to receive an address signal, a write enable signal and a data signal generated by an address data generator; the output ports include an A_out[14:0] output port, a WE_out' output port and a DATA_out[35:0] output port, which are respectively used to output an address signal, a write enable signal and a data signal selected according to the external selection signal.

[0023] Further, the bit width of the memory to be tested may be 1, 2, 4, 9, 18 or 36; the value of the selection signal is S[5:0]; and the method in which the bit width selector selects a signal corresponding to the memory bit width according to the selection signal is:

[0024] When S[5] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 36-bit width, and A_out[9:0], WE_out', and DATA_out[35:0] are selected; when S[4] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 18-bit width, and A_out[10:0], WE_out', and DATA_out[35:0] are selected; when S[3] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 9-bit width, and A_out[11:0], WE_out', and DATA_out[35:0] are selected; When S[2] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 4-bit width, and A_out[12:0], WE_out', and DATA_out[35:0] are selected; when S[1] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 2-bit width, and A_out[13:0], WE_out', and DATA_out[35:0] are selected; when S[0] is 1 and other control bits are 0, the selected signal is the address bit corresponding to the 1-bit width, and A_out[14:0], WE_out', and DATA_out[35:0] are selected.

[0025] Further, the bit width selector includes 17 inverters K55, K57, K59, K61, K63, K65, K67, K69, K71, K73, K75, K77, K79, K81, K83 and K85, 17 transmission gates K56, K58, K60, K62, K64, K66, K68, K70, K72, K74, K76, K78, K80, K82, K84, K86 and K88, and 5 OR gates K89, K90, K91, K92 and OR gate K93;

[0026] The input end of the inverter K55 and the positive control end of the transmission gate K56 are connected to the control port S[0], the output end of the inverter K55 is connected to the negative control end of the transmission gate K56, the input end of the transmission gate K56 is the input port A_in

[14] , and the output end is A_out

[14] ; the two input ends of the AND gate K89 are connected to the control ports S[0] and S[1] respectively, the output end is connected to the input end of the inverter K57 and the positive control end of the transmission gate K58, the output end of the inverter K57 is connected to the negative control end of the transmission gate K58, the input end of the transmission gate K58 is the input port A_in

[13] , and the output end is A_out

[13] ; the three input ends of the AND gate K90 are connected to the control ports S[0], S[1 ], S[2], the output end is connected to the input end of the inverter K59 and the positive control end of the transmission gate K60, the output end of the inverter K59 is connected to the negative control end of the transmission gate K60, the input end of the transmission gate K60 is the input port A_in

[12] , and the output end is A_out

[12] ; the four input ends of the AND gate K91 are respectively connected to the control ports S[0], S[1], S[2], and S[3], the output end is connected to the input end of the inverter K61 and the positive control end of the transmission gate K62, the output end of the inverter K61 is connected to the negative control end of the transmission gate K62, the input end of the transmission gate K62 is the input port A_in

[11] , and the output end is A_out

[11] ; the five input ends of the AND gate K92 are respectively connected to the control ports S[0], S[1], S[2], and S[3] The AND gate K93 has six input terminals connected to the control ports S[0], S[1], S[2], S[3], and S[4], and an output terminal connected to the input terminal of the inverter K63 and the positive control terminal of the transmission gate K64. The output terminal of the inverter K63 is connected to the negative control terminal of the transmission gate K64. The input terminal of the transmission gate K64 is the input port A_in

[10] , and the output terminal is A_out

[10] . The AND gate K93 has six input terminals connected to the control ports S[0], S[1], S[2], S[3], S[4], and S[5], respectively. The output terminal is connected to the input terminal of the inverter K65 and the positive control terminal of the transmission gate K66. The output terminal of the inverter K65 is connected to the negative control terminal of the transmission gate K66. The input terminal of the transmission gate K66 is the input port A_in[9]. The output end is A_out[9]; the input ends of transmission gates K68, K70, K72, K74, K76, K78, K80, K82, K84, K86, and K88 are A_in[8:0], WE'_in, and DATA, respectively, and the output ends are A_out[8:0], WE'_out, and DATA_out, respectively, where DATA_out is expanded to a 36-bit DATA_out[35:0] output, the positive control ends are all connected to VCC, and the negative control ends are respectively connected to the output ends of inverters K67, K69, K71, K73, K75, K77, K79, K81, K83, K85, and K87, and the input ends of the above inverters are all connected to VCC.

[0027] Furthermore, the variable bit width comparator includes 36 input ports DOUT[35:0], 6 control ports S[5:0] and 1 Result test result output port.

[0028] Further, the bit width of the memory to be tested may be 1, 2, 4, 9, 18 or 36; the value of the selection signal is S[5:0]; the specific manner in which the variable bit width comparator reads a data signal corresponding to the memory bit width from the memory to be tested according to the external input selection signal is as follows:

[0029] When S[5] is 1 and other control bits are 0, the selected data width is 36 bits wide. At this time, DOUT[35:0] selects and receives the data output from the memory for result comparison; when S[4] is 1 and other control bits are 0, the selected data width is 18 bits wide. At this time, DOUT[17:0] selects and receives the data output from the memory for result comparison, and DOUT[35:18] turns off the selection and is internally pulled up to 1 to prevent comparison errors; when S[3] is 1 and other control bits are 0, the selected data width is 9 bits wide. At this time, DOUT[8:0] selects and receives the data output from the memory for result comparison, and DOUT[35:9] turns off the selection and is internally pulled up to 1 to prevent comparison errors; when S[2] is 1 and other control bits are When the S[1] bit is 1 and the other control bits are 0, the selected data width is 2 bits. At this time, DOUT[1:0] is selected and receives the data output from the memory for comparison. DOUT[35:2] is turned off and internally pulled up to 1 to prevent comparison errors. When S[0] is 1 and the other control bits are 0, the selected data width is 1 bit. At this time, DOUT[0] is selected and receives the data output from the memory for comparison. DOUT[35:1] is turned off and internally pulled up to 1 to prevent comparison errors.

[0030] Further, the variable bit width comparator includes 8 inverters K110 to K115, K123 and K124, 7 OR gates K116 to K120, K122 and K127, 3 AND gates K121, K125 and K126, and 36 pull-up transmission gates;

[0031] The input port DOUT[35:0] is connected to the input end of each pull-up transmission gate respectively, and the output end of each pull-up transmission gate is DOUT_select[35:0] respectively. The input end is connected to the positive control end of the pull-up transmission gate of DOUT[35:18], connected to the control port S[5], and the negative control end is connected to the output end of the inverter K110; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9], connected to the output end of the OR gate K116, and the negative control end is connected to the output end of the inverter K111; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9], connected to the output end of the OR gate K117, and the negative control end is connected to the output end of the inverter K112; the input end is connected to DOUT The positive control end of the pull-up transmission gate of DOUT[8:4] is connected to the output end of the OR gate K118, and the negative control end is connected to the output end of the inverter K113; the positive control end of the pull-up transmission gate of DOUT[3:2] is connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; the positive control end of the pull-up transmission gate of DOUT[1] is connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; the positive control end of the pull-up transmission gate of DOUT[0] is connected to the output end of the OR gate K120, and the negative control end is connected to the output end of the inverter K115; the two input ends of the OR gate K116 are connected to the control port S[5:4], and the OR gate The three input ends of K117 are connected to the control port S[5:3]; the four input ends of the OR gate K118 are connected to the control port S[5:2], the five input ends of the OR gate K119 are connected to the control port S[5:1], and the six input ends of the OR gate K120 are connected to the control port S[5:0]; the input end of the inverter K110 is connected to the control port S[5]; the input end of the inverter K110 is connected to the control port S[5], the input end of the inverter K111 is connected to the output end of the OR gate K116, the input end of the inverter K112 is connected to the output end of the OR gate K117, the input end of the inverter K113 is connected to the output end of the OR gate K118, the input end of the inverter K114 is connected to the output end of the OR gate K119, and the input end of the inverter K115 is connected to the output end of the OR gate K116. The input end is connected to the output end of the OR gate K120; the 36 input ends of the AND gate K121 are respectively connected to DOUT_select[35:0], and the output end is connected to the input end of the inverter K123 and one input end of the AND gate K126; the 36 input ends of the OR gate K122 are respectively connected to DOUT_select[35:0], and the output end is connected to the input end of the inverter K124 and one input end of the AND gate K125; the output end of the inverter K123 is connected to the other input end of the AND gate K125, the output end of the inverter K124 is connected to the other input end of the AND gate K126, the output ends of the AND gates K125 and K126 are connected to the two input ends of the OR gate K127, and the output end is the output port Result.

[0032] Furthermore, the signal generated by the address data generator conforms to the MarchC algorithm, and can automatically complete the following operation sequence on the memory: write all positive addresses to 0, read all positive addresses to 0, write all positive addresses to 1, read all positive addresses to 1, write all reverse addresses to 0, read all reverse addresses to 0, write all reverse addresses to 1, and read all reverse addresses to 1.

[0033] Furthermore, the method for the variable bit width comparator to process the data signal and compare the obtained processing results is that all the data signals are bitwise ANDed and bitwise ORed, and the results of the ANDed and ORed are compared. When the two are the same, Result outputs 1, indicating that all memories are not faulty; when the two are different, Result outputs 0, indicating that a memory has a fault.

[0034] The advantages of the present invention compared with the prior art are:

[0035] (1) The present invention can automatically perform read and write test operations on common bit width memories in the prior art. In a preferred embodiment, the present invention can automatically perform read and write test operations on memories with a width of 1, 2, 4, 9, 18, or 36 bits, and can automatically compare the memory output data and output the result. The entire test process only requires input of a clock signal, a reset signal, and a bit width selection signal. The memory test can be automatically completed without manual operation, and has high test efficiency and flexibility.

[0036] (2) The present invention is based on the MarchC algorithm, and can automatically generate address and data signals through circuits, which can completely cover the reading and writing of all storage bits of the memory, and has high traversal and test coverage;

[0037] (3) The present invention has a simple structure and can be implemented using only logic gate circuits. It has a small circuit area and is suitable for large-scale programmable logic device applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural schematic diagram of the variable bit width memory automatic test circuit of the present invention;

[0039] Figure 2 is a circuit diagram of an address data generator of the present invention;

[0040] Figure 3 is a circuit diagram of a bit width selector of the present invention;

[0041] Figure 4 It is a circuit diagram of a variable bit width comparator of the present invention. DETAILED DESCRIPTION

[0042] The following detailed description of the present invention will make the features and advantages of the present invention more clear and explicit.

[0043] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0044] like Figure 1 As shown, the present invention proposes an automatic test circuit for a variable bit width memory in a programmable logic, the circuit is divided into an address data generator K1, a bit width selector K2 and a variable bit width comparator K3, the address data generator K1 can automatically generate a 15-bit address signal, a 1-bit data signal, and a 1-bit write enable signal, the bit width selector K2 is used to select a signal suitable for the bit width of the current memory, and transmit the converted signal to each memory to be tested, the variable bit width comparator K3 is used to receive the output data signal from the memory to be tested, convert the signal according to the selected bit width, and compare the converted signal, and output the result after obtaining the test result. The present invention can use less circuit structure to realize automatic full traversal test of the embedded memory of the programmable logic, and can select a suitable bit width for testing according to the memory width, with high test efficiency and flexibility.

[0045] The address data generator has two input ports, CLK and RST, and 17 output ports, A[14:0], WE', and DATA. The input port CLK inputs the clock signal, and the control port RST inputs the reset signal. It can automatically generate a 15-bit address signal that can be automatically flipped, a 1-bit data signal, and a 1-bit write enable signal. It can also change the address signal from positive sequence to reverse sequence when completing a cycle of the signal cycle. The automatically generated signal will be transmitted to the bit width selector.

[0046] The specific implementation method is: the input port CLK is used to provide a clock signal for the state machine in the address data generator, and the input port RST is used to provide a reset signal for the state machine in the address data generator. When RST is 0 and CLK is a square wave, the address data generator starts working, generates a continuous signal and outputs it to the outside. When RST is 1, the address data generator is disabled and reset. When RST becomes 0, the address data generator starts generating signals again.

[0047] The bit width selector has 27 input ports including A_in[14:0], WE', and DATA, 6 control ports including S[5:0], and 52 output ports including A_out[14:0], WE_out', and DATA_out[35:0]. The control port S[5:0] inputs a bit width selection signal, and the address signal of the address bit corresponding to the memory width can be selected according to the selection signal, that is, the number of address bits output to the memory under test can be selected according to the selection signal. The selectable address bits are 15, 14, 13, 12, 11, and 10, which are selected through S[5:0], and the selected address signal, data signal, and write enable signal are transmitted to the memory under test.

[0048] The specific method of setting the value of S[5:0] to select the corresponding signals of the memory bit widths of 1, 2, 4, 9, 18, and 36 is as follows: when S[5] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 36-bit width. At this time, A_out[9:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory; when S[4] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 18-bit width. At this time, A_out[10:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory; when S[3] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 9-bit width. At this time, A_out[11:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory. TA_out[35:0] is selected and data is output to the memory; when S[2] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 4-bit width, and A_out[12:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory; when S[1] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 2-bit width, and A_out[13:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory; when S[0] is 1 and other control bits are 0, the selected address bit is the address bit corresponding to the 1-bit width, and A_out[14:0], WE_out', and DATA_out[35:0] are selected and data is output to the memory.

[0049] The variable bit width comparator has 36 input ports DOUT[35:0], 6 control ports S[5:0], and one Result test result output port. It can select a signal suitable for the current memory bit width according to the selection signal, process and compare the data output by the memory according to the selected bit width, and output 1 according to the comparison result to indicate that all memories are functioning normally, and output 0 to indicate that a memory is faulty.

[0050] The specific method of setting the value of S[5:0] to select the data signal corresponding to the memory bit width of 1, 2, 4, 9, 18, and 36 is as follows: when S[5] is 1 and other control bits are 0, the selected data bit width is 36 bits. At this time, DOUT[35:0] selects and receives the data output by the memory for result comparison; when S[4] is 1 and other control bits are 0, the selected data bit width is 18 bits. At this time, DOUT[17:0] selects and receives the data output by the memory for result comparison, and DOUT[35:18] turns off the selection and is internally pulled up to 1 to prevent comparison errors; when S[3] is 1 and other control bits are 0, the selected data bit width is 9 bits. At this time, DOUT[8:0] selects and receives the data output by the memory for result comparison, and DOUT[35:9] turns off the selection and is internally pulled up to 1 to prevent comparison errors. The internal pull-up is 1 to prevent comparison errors; when S[2] is 1 and other control bits are 0, the selected data bit width is 4 bits wide. At this time, DOUT[3:0] is selected and receives the data output by the memory for result comparison, and DOUT[35:4] is turned off and internally pulled up to 1 to prevent comparison errors; when S[1] is 1 and other control bits are 0, the selected data bit width is 2 bits wide. At this time, DOUT[1:0] is selected and receives the data output by the memory for result comparison, and DOUT[35:2] is turned off and internally pulled up to 1 to prevent comparison errors; when S[0] is 1 and other control bits are 0, the selected data bit width is 1 bit wide. At this time, DOUT[0] is selected and receives the data output by the memory for result comparison, and DOUT[35:1] is turned off and internally pulled up to 1 to prevent comparison errors.

[0051] The signal generated by the address data generator conforms to the MarchC algorithm and can automatically complete the following operation sequence for the memory: write all positive addresses to 0, read all positive addresses to 0, write all positive addresses to 1, read all positive addresses to 1, write all reverse addresses to 0, read all reverse addresses to 0, write all reverse addresses to 1, and read all reverse addresses to 1.

[0052] The signal output by the memory enters the optional bit width comparator. After the bit width is selected, all the signals are bitwise ANDed and bitwise ORed. The results of the AND and OR are compared. When the two are the same, Result outputs 1, indicating that all memories are not faulty; when the two are different, Result outputs 0, indicating that a memory is faulty.

[0053] like Figure 2As shown in FIG. 1 , the address data generator is composed of 18 registers, 18 inverters, and 15 multiplexers; the 18 registers are: register K4, register K5, register K6, register K7, register K8, register K9, register K10, register K11, register K12, register K13, register K14, register K15, register K16, register K17, register K18, register K19, register K20, and register K21; the 18 inverters are: inverter K22, inverter K23, inverter K24, inverter K25, inverter K26, inverter K27, inverter K28, inverter K29, inverter K30, and inverter K31. The inverters are: inverter K27, inverter K28, inverter K29, inverter K30, inverter K31, inverter K32, inverter K33, inverter K34, inverter K35, inverter K36, inverter K37, inverter K38, inverter K39; the 15 multiplexers are: multiplexer K40, multiplexer K41, multiplexer K42, multiplexer K43, multiplexer K44, multiplexer K45, multiplexer K46, multiplexer K47, multiplexer K48, multiplexer K49, multiplexer K50, multiplexer K51, multiplexer K52, multiplexer K53, multiplexer K54; the connection relationship is as follows:

[0054] The input port CLK is connected to the CLK port of register K4, the input port Reset is connected to the RST ports of all registers respectively, the Q port of each register is connected to the input end of an inverter and an input end of a multiplexer respectively, the output end of the inverter is connected to the D port of the register and another input port of the multiplexer respectively, and the control port of the multiplexer is connected to the Q port of register K21.

[0055] The D port of register K4 is connected to the CLK port of register K5, the D port of register K5 is connected to the CLK port of register K6, the D port of register K6 is connected to the CLK port of register K7, the D port of register K7 is connected to the CLK port of register K8, the D port of register K8 is connected to the CLK port of register K9, the D port of register K9 is connected to the CLK port of register K10, the D port of register K10 is connected to the CLK port of register K11, the D port of register K11 is connected to the CLK port of register K12, and register K The D port of register K12 is connected to the CLK port of register K13, the D port of register K13 is connected to the CLK port of register K14, the D port of register K14 is connected to the CLK port of register K15, the D port of register K15 is connected to the CLK port of register K16, the D port of register K16 is connected to the CLK port of register K17, the D port of register K17 is connected to the CLK port of register K18, the D port of register K18 is connected to the CLK port of register K19, and the D port of register K19 is connected to the CLK port of register K20. The output port of multiplexer K40 is output port A

[14] , the output port of multiplexer K41 is output port A

[13] , the output port of multiplexer K42 is output port A

[12] , the output port of multiplexer K43 is output port A

[11] , the output port of multiplexer K44 is output port A

[10] , the output port of multiplexer K45 is output port A[9], the output port of multiplexer K46 is output port A[8], the output port of multiplexer K47 is output port A

[10] , the output port of multiplexer K48 is output port A

[11] , the output port of multiplexer K49 is output port A

[12] , the output port of multiplexer K40 is output port A

[14] , the output port of multiplexer K41 is output port A

[13] , the output port of multiplexer K42 is output port A

[12] , the output port of multiplexer K43 is output port A

[11] , the output port of multiplexer K44 is output port A

[10] , the output port of multiplexer K45 is output port A[9], the output port of multiplexer K46 is output port A[8], the output port of multiplexer K47 is output port A

[11] , the output port of multiplexer K48 is output port A

[11] , the output port of multiplexer K49 ... The output port of multiplexer K48 is output port A[6], the output port of multiplexer K49 is output port A[5], the output port of multiplexer K50 is output port A[4], the output port of multiplexer K51 is output port A[3], the output port of multiplexer K52 is output port A[2], the output port of multiplexer K53 is output port A[1], the output port of multiplexer K54 is output port A[0], the Q port of register K19 is output port WE', and the Q port of register K20 is output port DATA.

[0056] like Figure 3As shown: the bit width selector is composed of 17 inverters, 17 transmission gates, and 5 OR gates. The 17 inverters are: inverter K55, inverter K57, inverter K59, inverter K61, inverter K63, inverter K65, inverter K67, inverter K69, inverter K71, inverter K73, inverter K75, inverter K77, inverter K79, inverter K81, inverter K83, inverter K85, 17 transmission gates They are: transmission gate K56, transmission gate K58, transmission gate K60, transmission gate K62, transmission gate K64, transmission gate K66, transmission gate K68, transmission gate K70, transmission gate K72, transmission gate K74, transmission gate K76, transmission gate K78, transmission gate K80, transmission gate K82, transmission gate K84, transmission gate K86, transmission gate K88. The 5 OR gates are: OR gate K89, OR gate K90, OR gate K91, OR gate K92, and OR gate K93.

[0057] The connection relationship is as follows: the input end of the inverter K55 and the positive control end of the transmission gate K56 are connected to the control port S[0], the output end of the inverter K55 is connected to the negative control end of the transmission gate K56, the input end of the transmission gate K56 is the input port A_in

[14] , and the output end is A_out

[14] ; the two input ends of the AND gate K89 are connected to the control ports S[0] and S[1], the output end is connected to the input end of the inverter K57 and the positive control end of the transmission gate K58, the output end of the inverter K57 is connected to the negative control end of the transmission gate K58, the input end of the transmission gate K58 is the input port A_in

[13] , and the output end is A_out

[13] ; the three input ends of the AND gate K90 are connected to the control ports S[0], The output end of the AND gate K91 is connected to the input end of the inverter K59 and the positive control end of the transmission gate K60. The output end of the inverter K59 is connected to the negative control end of the transmission gate K60. The input end of the transmission gate K60 is the input port A_in

[12] , and the output end is A_out

[12] . The four input ends of the AND gate K91 are connected to the control ports S[0], S[1], S[2], and S[3]. The output end is connected to the input end of the inverter K61 and the positive control end of the transmission gate K62. The output end of the inverter K61 is connected to the negative control end of the transmission gate K62. The input end of the transmission gate K62 is the input port A_in

[11] , and the output end is A_out

[11] . The five input ends of the AND gate K92 are connected to the control ports S[0], S[1], S[2], and S[3]. The six input ends of the AND gate K93 are connected to the control ports S[0], S[1], S[2], S[3], and S[4], and the output end is connected to the input end of the inverter K63 and the positive control end of the transmission gate K64. The output end of the inverter K63 is connected to the negative control end of the transmission gate K64. The input end of the transmission gate K64 is the input port A_in

[10] , and the output end is A_out

[10] . The six input ends of the AND gate K93 are connected to the control ports S[0], S[1], S[2], S[3], S[4], and S[5]. The output end is connected to the input end of the inverter K65 and the positive control end of the transmission gate K66. The output end of the inverter K65 is connected to the negative control end of the transmission gate K66. The input end of the transmission gate K66 is the input port A_in[9], and the output end is A_out

[10] . The output end is A_out[9]; the input ends of transmission gates K68, K70, K72, K74, K76, K78, K80, K82, K84, K86, and K88 are A_in[8:0], WE'_in, and DATA, respectively, and the output ends are A_out[8:0], WE'_out, and DATA_out, respectively, where DATA_out is expanded to a 36-bit DATA_out[35:0] output, the positive control ends are all connected to VCC, and the negative control ends are respectively connected to the output ends of inverters K67, K69, K71, K73, K75, K77, K79, K81, K83, K85, and K87, and the input ends of the above inverters are all connected to VCC.

[0058] like Figure 4 As shown in FIG. 1 , the variable bit width comparator is composed of 8 inverters, 7 OR gates, 3 AND gates, and 36 pull-up transmission gates. The 8 inverters are: inverter K110, inverter K111, inverter K112, inverter K113, inverter K114, inverter K115, inverter K123, inverter K124; the 7 OR gates are OR gate K116, OR gate K117, OR gate K118, OR gate K119, OR gate K120, OR gate K122, OR gate K127; the 3 AND gates are: AND gate K121, AND gate K125, AND gate K126, 36 pull-up transmission gates are: transmission gate K94, transmission gate K95, transmission gate K96, transmission gate K97, transmission gate K98, transmission gate K99, transmission gate K100, transmission gate K101, transmission gate K102, transmission gate K103, transmission gate K104, transmission gate K105, transmission gate K106, transmission gate K107, transmission gate K108, transmission gate K109 (only 16 are listed here due to layout reasons).

[0059] The connection relationship is as follows: each input port DOUT[35:0] is connected to the input end of a pull-up transmission gate, and the output end of each pull-up transmission gate is DOUT_select[35:0]. The input end is connected to the positive control end of the pull-up transmission gate of DOUT[35:18], connected to the control port S[5], and the negative control end is connected to the output end of the inverter K110; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9], connected to the output end of the OR gate K116, and the negative control end is connected to the output end of the inverter K111; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9], connected to the output end of the OR gate K117, and the negative control end is connected to the output end of the inverter K112; the input end The positive control end of the pull-up transmission gate connected to DOUT[8:4] is connected to the output end of the OR gate K118, and the negative control end is connected to the output end of the inverter K113; the positive control end of the pull-up transmission gate connected to DOUT[3:2] is connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; the positive control end of the pull-up transmission gate connected to DOUT[1] is connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; the positive control end of the pull-up transmission gate connected to DOUT[0] is connected to the output end of the OR gate K120, and the negative control end is connected to the output end of the inverter K115; the two input ends of the OR gate K116 are connected to the control port S[5:4 ], the three input ends of the OR gate K117 are connected to the control port S[5:3]; the four input ends of the OR gate K118 are connected to the control port S[5:2], the five input ends of the OR gate K119 are connected to the control port S[5:1], and the six input ends of the OR gate K120 are connected to the control port S[5:0]; the input end of the inverter K110 is connected to the control port S[5]; the input end of the inverter K110 is connected to the control port S[5], the input end of the inverter K111 is connected to the output end of the OR gate K116, the input end of the inverter K112 is connected to the output end of the OR gate K117, the input end of the inverter K113 is connected to the output end of the OR gate K118, the input end of the inverter K114 is connected to the output end of the OR gate K119, and the input end of the inverter K11 The input end of the AND gate K121 is connected to the output end of the OR gate K120; the 36 input ends of the AND gate K121 are respectively connected to DOUT_select[35:0], and the output end is connected to the input end of the inverter K123 and one input end of the AND gate K126; the 36 input ends of the OR gate K122 are respectively connected to DOUT_select[35:0], and the output end is connected to the input end of the inverter K124 and one input end of the AND gate K125; the output end of the inverter K123 is connected to the other input end of the AND gate K125, the output end of the inverter K124 is connected to the other input end of the AND gate K126, the output ends of the AND gates K125 and K126 are connected to the two input ends of the OR gate K127, and the output end is the output port Result.

[0060] The present invention has been described in detail above in conjunction with specific implementations and exemplary examples, but these descriptions cannot be understood as limiting the present invention. Those skilled in the art understand that, without departing from the spirit and scope of the present invention, a variety of equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its implementation methods, all of which fall within the scope of the present invention. The scope of protection of the present invention shall be subject to the attached claims.

[0061] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. An automatic test circuit for a variable bit width memory in a programmable logic device, characterized in that: It includes an address data generator, a bit width selector and a variable bit width comparator; The address data generator automatically generates the signals required for memory testing according to the externally input clock signal and reset signal and outputs them to the bit width selector; the signals required for memory testing include a 1-bit data signal, a 1-bit write enable signal and a 15-bit address signal; The bit width selector selects an address signal, a data signal and a write enable signal corresponding to the memory bit width according to an external input selection signal, and transmits the selected address signal, data signal and write enable signal to the memory to be tested; The variable bit width comparator reads a data signal corresponding to the memory bit width from the memory to be tested according to an external input selection signal, processes the data signal and compares the obtained processing results, and outputs the test results after obtaining them; The input port of the address data generator includes a CLK input port and a RST input port, which are used to input a clock signal and a reset signal respectively; the output port of the address data generator includes an A[14:0] output port, a WE' output port and a DATA output port, which are used to output an address signal, a write enable signal and a data signal respectively; The address data generator includes 18 registers K4-K21, 18 inverters K22-K39 and 15 multiplexers K40-K54; The input port CLK is connected to the CLK port of register K4; The input port RST is connected to the RST ports of registers K4 to K21 respectively; The Q ports of registers K4 to K21 are respectively connected to the input terminals of inverters K22 to K39, and the Q ports of registers K4 to K18 are respectively connected to the first input terminals of multiplexers K40 to K54; the output terminals of inverters K22 to K39 are respectively connected to the D ports of registers K4 to K21, and the output terminals of inverters K22 to K36 are respectively connected to the second input terminals of multiplexers K40 to K54; the control ports of multiplexers K40 to K54 are connected to the Q port of register K21; The D ports of registers K4 to K20 are connected to the CLK ports of registers K5 to K21 respectively; The output ports of multiplexers K40 to K54 are output ports A[14] to A[0] respectively; The Q port of the register K19 is the output port WE', and the Q port of the register K20 is the output port DATA.

2. An automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The address data generator changes the address signal from positive sequence to reverse sequence each time a cycle is completed.

3. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The method by which the address data generator automatically generates the signals required for memory testing according to the external input clock signal and reset signal is as follows: When the reset signal RST is 0 and the clock signal CLK is a square wave, the address data generator starts working, generates continuous address signals, write enable signals and data signals and outputs them to the outside. When RST is 1, the address data generator is disabled and reset. When RST becomes 0, the address data generator starts generating signals again.

4. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The bit width selector includes 6 control ports, 17 input ports and 52 output ports; the control port S[5:0] is used to input an external selection signal; the input ports include A_in[14:0] input port, WE' input port and DATA input port, which are respectively used to receive the address signal, write enable signal and data signal generated by the address data generator; the output ports include A_out[14:0] output port, WE_out' output port and DATA_out[35:0] output port, which are respectively used to output the address signal, write enable signal and data signal selected according to the external selection signal.

5. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 4, characterized in that: The bit width of the memory to be tested can be 1, 2, 4, 9, 18 or 36; the value of the selection signal is S[5:0]; the method in which the bit width selector selects a signal that matches the memory bit width according to the selection signal is: When S[5] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 36-bit width, and A_out[9:0], WE_out', and DATA_out[35:0] are selected; when S[4] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 18-bit width, and A_out[10:0], WE_out', and DATA_out[35:0] are selected; when S[3] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 9-bit width, and A_out[11:0], WE_out', and DATA_out[35:0] are selected; When S[2] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 4-bit width, and A_out[12:0], WE_out', and DATA_out[35:0] are selected; when S[1] is 1 and other control bits are 0, the selected signal is the signal corresponding to the 2-bit width, and A_out[13:0], WE_out', and DATA_out[35:0] are selected; when S[0] is 1 and other control bits are 0, the selected signal is the address bit corresponding to the 1-bit width, and A_out[14:0], WE_out', and DATA_out[35:0] are selected.

6. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 5, characterized in that: The bit width selector includes 17 inverters K55, K57, K59, K61, K63, K65, K67, K69, K71, K73, K75, K77, K79, K81, K83 and K85, 17 transmission gates K56, K58, K60, K62, K64, K66, K68, K70, K72, K74, K76, K78, K80, K82, K84, K86 and K88, and 5 OR gates K89, K90, K91, K92 and OR gate K93; The input end of the inverter K55 and the positive control end of the transmission gate K56 are connected to the control port S[0], the output end of the inverter K55 is connected to the negative control end of the transmission gate K56, the input end of the transmission gate K56 is the input port A_in[14], and the output end is A_out[14]; the two input ends of the AND gate K89 are connected to the control ports S[0] and S[1] respectively, the output end is connected to the input end of the inverter K57 and the positive control end of the transmission gate K58, the output end of the inverter K57 is connected to the negative control end of the transmission gate K58, the input end of the transmission gate K58 is the input port A_in[13], and the output end is A_out[13]; the three input ends of the AND gate K90 are connected to the control ports S[0], S[1 ], S[2], the output end is connected to the input end of the inverter K59 and the positive control end of the transmission gate K60, the output end of the inverter K59 is connected to the negative control end of the transmission gate K60, the input end of the transmission gate K60 is the input port A_in[12], and the output end is A_out[12]; the four input ends of the AND gate K91 are respectively connected to the control ports S[0], S[1], S[2], and S[3], the output end is connected to the input end of the inverter K61 and the positive control end of the transmission gate K62, the output end of the inverter K61 is connected to the negative control end of the transmission gate K62, the input end of the transmission gate K62 is the input port A_in[11], and the output end is A_out[11]; the five input ends of the AND gate K92 are respectively connected to the control ports S[0], S[1], S[2], and S[3] The AND gate K93 has six input terminals connected to the control ports S[0], S[1], S[2], S[3], and S[4], and an output terminal connected to the input terminal of the inverter K63 and the positive control terminal of the transmission gate K64. The output terminal of the inverter K63 is connected to the negative control terminal of the transmission gate K64. The input terminal of the transmission gate K64 is the input port A_in[10], and the output terminal is A_out[10]. The AND gate K93 has six input terminals connected to the control ports S[0], S[1], S[2], S[3], S[4], and S[5], respectively. The output terminal is connected to the input terminal of the inverter K65 and the positive control terminal of the transmission gate K66. The output terminal of the inverter K65 is connected to the negative control terminal of the transmission gate K66. The input terminal of the transmission gate K66 is the input port A_in[9]. The output end is A_out[9]; the input ends of transmission gates K68, K70, K72, K74, K76, K78, K80, K82, K84, K86, and K88 are A_in[8:0], WE'_in, and DATA, respectively, and the output ends are A_out[8:0], WE'_out, and DATA_out, respectively, where DATA_out is expanded to a 36-bit DATA_out[35:0] output, the positive control ends are all connected to VCC, and the negative control ends are respectively connected to the output ends of inverters K67, K69, K71, K73, K75, K77, K79, K81, K83, K85, and K87, and the input ends of the above inverters are all connected to VCC.

7. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The variable bit width comparator includes 36 input ports DOUT[35:0], 6 control ports S[5:0] and 1 Result test result output port.

8. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 7, characterized in that: The bit width of the memory to be tested can be 1, 2, 4, 9, 18 or 36; the value of the selection signal is S[5:0]; the specific manner in which the variable bit width comparator reads the data signal corresponding to the memory bit width from the memory to be tested according to the external input selection signal is as follows: When S[5] is 1 and other control bits are 0, the selected data width is 36 bits wide. At this time, DOUT[35:0] selects and receives the data output from the memory for result comparison; when S[4] is 1 and other control bits are 0, the selected data width is 18 bits wide. At this time, DOUT[17:0] selects and receives the data output from the memory for result comparison, and DOUT[35:18] turns off the selection and is internally pulled up to 1 to prevent comparison errors; when S[3] is 1 and other control bits are 0, the selected data width is 9 bits wide. At this time, DOUT[8:0] selects and receives the data output from the memory for result comparison, and DOUT[35:9] turns off the selection and is internally pulled up to 1 to prevent comparison errors; when S[2] is 1 and other control bits are When the S[1] bit is 1 and the other control bits are 0, the selected data width is 2 bits. At this time, DOUT[1:0] is selected and receives the data output from the memory for comparison. DOUT[35:2] is turned off and internally pulled up to 1 to prevent comparison errors. When S[0] is 1 and the other control bits are 0, the selected data width is 1 bit. At this time, DOUT[0] is selected and receives the data output from the memory for comparison. DOUT[35:1] is turned off and internally pulled up to 1 to prevent comparison errors.

9. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 7, characterized in that: The variable bit width comparator includes 8 inverters K110-K115, K123 and K124, 7 OR gates K116-K120, K122 and K127, 3 AND gates K121, K125 and K126, and 36 pull-up transmission gates; The input port DOUT[35:0] is connected to the input end of each pull-up transmission gate respectively, and the output end of each pull-up transmission gate is DOUT_select[35:0] respectively. The input end is connected to the positive control end of the pull-up transmission gate of DOUT[35:18], which is connected to the control port S[5], and the negative control end is connected to the output end of the inverter K110; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9], which is connected to the output end of the OR gate K116, and the negative control end is connected to the output end of the inverter K111; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[17:9] The output end of the OR gate K117 is connected, and the negative control end is connected to the output end of the inverter K112; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[8:4], connected to the output end of the OR gate K118, and the negative control end is connected to the output end of the inverter K113; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[3:2], connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; the input end is connected to the positive control end of the pull-up transmission gate of DOUT[1], connected to the output end of the OR gate K119, and the negative control end is connected to the output end of the inverter K114; The positive control end of the pull-up transmission gate whose input end is connected to DOUT[0] is connected to the output end of the OR gate K120, and the negative control end is connected to the output end of the inverter K115; the two input ends of the OR gate K116 are connected to the control port S[5:4], and the three input ends of the OR gate K117 are connected to the control port S[5:3]; the four input ends of the OR gate K118 are connected to the control port S[5:2], the five input ends of the OR gate K119 are connected to the control port S[5:1], and the six input ends of the OR gate K120 are connected to the control port S[5:0]; the input end of the inverter K110 is connected to the control port S[5]; The input end of the inverter K110 is connected to the control port S[5], the input end of the inverter K111 is connected to the output end of the OR gate K116, the input end of the inverter K112 is connected to the output end of the OR gate K117, the input end of the inverter K113 is connected to the output end of the OR gate K118, the input end of the inverter K114 is connected to the output end of the OR gate K119, and the input end of the inverter K115 is connected to the output end of the OR gate K120; The 36 input terminals of the AND gate K121 are respectively connected to DOUT_select[35:0], and the output terminal is connected to the input terminal of the inverter K123 and one input terminal of the AND gate K126; the 36 input terminals of the OR gate K122 are respectively connected to DOUT_select[35:0], and the output terminal is connected to the input terminal of the inverter K124 and one input terminal of the AND gate K125; the output terminal of the inverter K123 is connected to the other input terminal of the AND gate K125, the output terminal of the inverter K124 is connected to the other input terminal of the AND gate K126, the output terminals of the AND gates K125 and K126 are connected to the two input terminals of the OR gate K127, and the output terminal is the output port Result.

10. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The signal generated by the address data generator conforms to the MarchC algorithm and can automatically complete the following operation sequence on the memory: write all positive addresses to 0, read all positive addresses to 0, write all positive addresses to 1, read all positive addresses to 1, write all reverse addresses to 0, read all reverse addresses to 0, write all reverse addresses to 1, and read all reverse addresses to 1.

11. The automatic test circuit for a variable bit width memory in a programmable logic device according to claim 1, characterized in that: The method for the variable bit width comparator to process the data signal and compare the obtained processing results is that all the data signals are bitwise ANDed and bitwise ORed, and the results of the AND and OR are compared. When the two are the same, Result outputs 1, indicating that all memories are not faulty; when the two are different, Result outputs 0, indicating that a memory is faulty.

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