Memristor positive and negative three-value 9-line-2-line encoder circuit based on 3-line-1-line encoder

Abstract

The present invention relates to a memristor positive and negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder. The 3-line-1-line encoder of the present invention is used to input three binary signals and output a three-value signal; each three-value three-input maximum value gate is used to output the logical maximum value of three input terminals, the three-value three-input minimum value gate is used to output the logical minimum value of three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of two inputs, the three-value two-input OR gate is used to complete the "OR" operation of two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation; the present invention uses a three-value digital signal to communicate at the same frequency, which will have a higher transmission rate, and the corresponding logic function circuit interconnection will also be reduced, and the digital chip can also be smaller and the cost is lower. Combined with the characteristics of the memristor, the efficiency of information storage, processing, and transmission is further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and relates to a three-value digital logic circuit, and specifically to a memristor positive and negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder. Background Art

[0002] Integrated circuit technology is the foundation of today's entire digital information society. However, as the size of traditional complementary metal oxide semiconductor (CMOS) devices gradually shrinks to its limit, the continuation of Moore's Law has encountered difficulties, and the traditional architecture that separates information storage and processing has also encountered the "von Neumann bottleneck". The emergence of memristors is expected to bring new opportunities for the development of the information technology industry. It combines information storage and logical operations in a single device and can be used as the core device of the future non-von Neumann computer architecture that integrates information storage and computing. It has great significance in the fields of ultra-high density information storage, brain-like neural networks, etc.

[0003] In 2008, the preparation of actual physical devices of memristors triggered a wave of related research. Memristors are regarded as the next generation of non-volatile memory technology, with low power consumption, easy integration, nanometer size, non-volatility, and compatibility with traditional CMOS technology. They can meet the performance requirements of the new generation of high-density information storage and high-performance computing for general-purpose electronic memory. In addition, memristors have begun to be applied to research in various fields, such as nonlinear circuits, non-volatile storage, neuromorphic networks, digital logic circuits, etc., due to their unique characteristics.

[0004] In today's big data era, data information is growing explosively. While pursuing higher and higher data processing efficiency, information logic systems are finding it increasingly difficult to process such huge amounts of data. As a multi-valued logic, three-valued logic has attracted the attention of researchers due to its advantages such as higher single-line information carrying capacity and more logical functions.

[0005] There are two ways to represent three-valued logic: unbalanced three-valued and balanced three-valued. Unbalanced three-valued includes positive three-valued {0,1,2} and negative three-valued {0,-1,-2}, and balanced three-valued is represented by {-1,0,1}. Since three-valued digital signals contain more information per bit than binary digital signals, using three-valued digital signals for communication will have a higher transmission rate at the same frequency, and the interconnection of corresponding logic function circuits will also be reduced, and digital chips can be smaller and less expensive. Combined with the characteristics of memristors, which are nano-sized, easy to integrate, and compatible with CMOS technology, memristor three-valued digital logic circuits can further improve the efficiency of information storage, processing, and transmission, bringing new breakthroughs to the manufacture of high-density information logic systems. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention proposes a memristor positive and negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder.

[0007] A memristor positive three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder comprises a first 3-line-1-line encoder U1, a second 3-line-1-line encoder U2, a third 3-line-1-line encoder U3, a three-value three-input minimum gate U4, a first three-value three-input maximum gate U5, a second three-value three-input maximum gate U6, a standard three-value NOT gate U7, a positive three-value NOT gate U8, a three-value two-input AND gate U9, and a three-value two-input OR gate U10. 10 ;

[0008] The 3-line-1-line encoder is used to input three binary signals and output one three-value signal; each three-value three-input maximum value gate is used to output the logical maximum value of the three input terminals, the three-value three-input minimum value gate is used to output the logical minimum value of the three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of the two inputs, the three-value two-input OR gate is used to complete the "OR" operation of the two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation;

[0009] The input ends of the first 3-line-1-line encoder U1, the second 3-line-1-line encoder U2 and the third 3-line-1-line encoder U3 are respectively used as the 9-way input ends X8, X7, X6, X5, X4, X3, X2, X1, X0 of the 9-line-2-line encoder from the high position I2 to the low position I0; the output end of the first 3-line-1-line encoder U1 is connected to one of the input ends of the three-value three-input minimum gate U4, the output end of the second 3-line-1-line encoder U2 is connected to the second input end of the three-value three-input minimum gate U4, and the output end of the third 3-line-1-line encoder U3 is connected to the third input end of the three-value three-input minimum gate U4; the output end of the first three-value three-input minimum gate U4 serves as the first output end Y0;

[0010] The three input ends of the first three-value three-input maximum gate U5 are connected to the input ends X8, X7, and X6 respectively, and the three input ends of the second three-value three-input maximum gate U6 are connected to the input ends X5, X4, and X3 respectively; the output end of the first three-value three-input maximum gate U5 is connected to the input end of the standard three-value NOT gate U7, and the output end of the standard three-value NOT gate U7 is connected to the input end of the positive three-value NOT gate U8; the two input ends of the three-value two-input AND gate U9 are respectively connected to the output end of the second three-value three-input maximum gate U6 and the voltage source V DD / 2 connection; three-value two-input OR gate U 10 The two input ends of the positive three-value NOT gate U8 and the output end of the three-value two-input AND gate U9 are connected respectively. 10The output terminal of is used as the second output terminal Y1;

[0011] Depending on the logical state of the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0}, the output state of the two output ends of the encoder is different.

[0012] The 3-wire-1-wire encoder includes seven memristors and four MOS tubes. The negative electrode of the first memristor M1 is connected to the voltage source V DD The positive electrode of the first memristor M1 and the drain of the first MOS tube T1 are connected to the positive electrode of the fifth memristor M5; the gates of the first MOS tube T1 of the three 3-line-1-line encoders are respectively used as the input terminals X8, X5, X2, of the 9-line-2-line encoder, and the source of the first MOS tube T1 is connected to the ground; the negative electrode of the second memristor M2 is connected to the voltage source V DD The positive electrode of the second memristor M2, the negative electrode of the third memristor M3, and the drain of the third MOS tube T3 are connected to the positive electrode of the sixth memristor M6; the gate of the second MOS tube T2 of the three 3-line-1-line encoders is connected to the gate of the third MOS tube T3, and they are respectively used as the input terminals X7, X4, and X1 of the 9-line-2-line encoder, the drain of the second MOS tube T2 is connected to the positive electrode of the third memristor M3, the source of the second MOS tube T2 is grounded, and the source of the third MOS tube T3 is grounded; the negative electrode of the fourth memristor M4 is connected to the voltage source V DD The positive electrode of the fourth memristor M4 and the drain of the fourth MOS tube T4 are connected to the positive electrode of the seventh memristor M7; the gates of the fourth MOS tube T4 of the three 3-line-1-line encoders serve as the input terminals X6, X3, and X0 of the 9-line-2-line encoder, and the source of the fourth MOS tube T4 is grounded; the negative electrode of the fifth memristor M5, the negative electrode of the sixth memristor M6, and the negative electrode of the seventh memristor M7 are connected as the output terminal of the 3-line-1-line encoder; the three-value three-input minimum gate includes three memristors, the negative electrodes of the three memristors are respectively used as the input terminals of the three-value three-input minimum gate, connected to the output terminals of the three 3-line-1-line encoders, and the positive electrodes of the three memristors are used as the output terminal of the three-value three-input minimum gate.

[0013] The first three-value three-input maximum value gate U5 and the second three-value three-input maximum value gate U6 each include three memristors, the positive electrodes of the three memristors are respectively used as the input ends of each three-value three-input maximum value gate, and are connected to the input ends X8, X7, X6, X5, X4, and X3 of the 9-line-2-line encoder, and the negative electrodes of the three memristors are used as the output ends of each three-value three-input maximum value gate;

[0014] The standard three-value NOT gate U7 includes two memristors and two MOS tubes. The gate of one MOS tube is connected to the gate of another MOS tube and serves as the input of the standard three-value NOT gate U7. The positive electrode of one memristor is connected to the drain of one MOS tube. The positive electrode of another memristor, the negative electrode of one memristor, and the drain of another MOS tube are connected to serve as the output of the standard three-value NOT gate U7. The positive electrode of another memristor is connected to the voltage source V DD , the sources of the two MOS tubes are grounded; the input end of the standard three-value NOT gate U7 is connected to the output end of a three-value three-input maximum value gate;

[0015] The positive three-value NOT gate U8 includes a memristor and a MOS tube. The negative electrode of the memristor is connected to the voltage source V DD , the positive electrode of the memristor is connected to the drain of the MOS tube as the output end of the positive three-value NOT gate U8; the gate of the MOS tube is used as the input end of the positive three-value NOT gate U8, and the source of the MOS tube is grounded; the input end of the positive three-value NOT gate U8 is connected to the output end of the standard three-value NOT gate U7;

[0016] The three-value two-input AND gate U9 includes two memristors, the negative electrode of one memristor is connected to the output terminal of another three-value three-input maximum gate, and the negative electrode of the other memristor is connected to the voltage source V DD / 2; the positive electrodes of the two memristors serve as the output terminals of the three-value two-input AND gate U9;

[0017] Three-value two-input OR gate U 10 It includes two memristors, the positive electrode of one memristor is connected to the output end of the positive three-value NOT gate U8; the positive electrode of the other memristor is connected to the output end of the three-value two-input AND gate U9, and the negative electrodes of the two memristors are used as the three-value two-input OR gate U 10 The output terminal.

[0018] The MOS tube involved in the positive three-value 9-line-2-line encoder is an NMOS tube.

[0019] A memristor negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder, comprising three 3-line-1-line encoders, a three-value three-input maximum gate, two three-value three-input minimum gates, a standard three-value NOT gate, a negative three-value NOT gate, a three-value two-input OR gate, and a three-value two-input AND gate;

[0020] The 3-line-1-line encoder is used to input three binary signals and output one three-value signal; the three-value three-input maximum value gate is used to output the logical maximum value of the three input terminals, each three-value three-input minimum value gate is used to output the logical minimum value of the three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of the two inputs, the three-value two-input OR gate is used to complete the "OR" operation of the two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation;

[0021] The input ends of the first 3-line-1-line encoder, the second 3-line-1-line encoder and the third 3-line-1-line encoder are respectively used as the 9-way input ends X8, X7, X6, X5, X4, X3, X2, X1, and X0 of the 9-line-2-line encoder; the output end of the first 3-line-1-line encoder is connected to one of the input ends of the three-value three-input maximum value gate, the output end of the second 3-line-1-line encoder is connected to the second input end of the three-value three-input maximum value gate, and the output end of the third 3-line-1-line encoder is connected to the third input end of the three-value three-input maximum value gate; the output end of the three-value three-input maximum value gate U4 is used as the first output end Y0;

[0022] The three input ends of the first three-value three-input minimum gate are connected to the input ends X8, X7, and X6 respectively, and the three input ends of the second three-value three-input minimum gate are connected to the input ends X5, X4, and X3 respectively; the output end of the first three-value three-input minimum gate is connected to the input end of the standard three-value NOT gate, and the output end of the standard three-value NOT gate is connected to the input end of the negative three-value NOT gate; the two input ends of the three-value two-input OR gate are respectively connected to the output end of the second three-value three-input minimum gate and the voltage source -V DD / 2 connection; the two input ends of the three-value two-input AND gate are respectively connected to the output end of the negative three-value NOT gate and the output end of the three-value two-input OR gate, and the output end of the three-value two-input AND gate serves as the second output end Y1;

[0023] Depending on the logical state of the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0}, the output state of the two output ends of the encoder is different.

[0024] The 3-wire-1-wire encoder includes seven memristors and four MOS tubes. The negative electrode of the first memristor M1 is connected to the voltage source -V DD The positive electrode of the first memristor M1 and the drain of the first MOS tube T1 are connected to the negative electrode of the fifth memristor M5; the gates of the first MOS tube T1 of the three 3-line-1-line encoders are respectively used as the input terminals X8, X5, and X2 of the 9-line-2-line encoder, and the source of the first MOS tube T1 is connected to the ground; the negative electrode of the second memristor M2 is connected to the voltage source -V DD The positive electrode of the second memristor M2, the negative electrode of the third memristor M3, and the drain of the third MOS tube T3 are connected to the negative electrode of the sixth memristor M6; the gate of the second MOS tube T2 of the three 3-line-1-line encoders is connected to the gate of the third MOS tube T3, and they are respectively used as the input terminals X7, X4, and X1 of the 9-line-2-line encoder, the drain of the second MOS tube T2 is connected to the positive electrode of the third memristor M3, the source of the second MOS tube T2 is grounded, and the source of the third MOS tube T3 is grounded; the negative electrode of the fourth memristor M4 is connected to the voltage source -V DDThe positive electrode of the fourth memristor M4 and the drain of the fourth MOS tube T4 are connected to the negative electrode of the seventh memristor M7; the gates of the fourth MOS tubes T4 of the three 3-line-1-line encoders serve as the input terminals X6, X3, and X0 of the 9-line-2-line encoder, and the source of the fourth MOS tube T4 is grounded; the positive electrode of the fifth memristor M5, the positive electrode of the sixth memristor M6, and the positive electrode of the seventh memristor M7 are connected as the output terminal of the 3-line-1-line encoder;

[0025] The three-value three-input minimum gate U4 includes three memristors, the positive electrodes of the three memristors are respectively used as input terminals of the three-value three-input minimum gate, connected to the output terminals of three 3-wire-1-wire encoders, and the negative electrodes of the three memristors are used as output terminals of the three-value three-input minimum gate.

[0026] The first three-value three-input minimum gate and the second three-value three-input minimum gate each include three memristors, the negative electrodes of the three memristors are respectively used as the input end of each three-value three-input minimum gate, and are connected to the input ends X8, X7, X6, X5, X4, and X3 of the 9-line-2-line encoder, and the positive electrodes of the three memristors are used as the output end of each three-value three-input minimum gate;

[0027] The standard three-value NOT gate includes two memristors and two MOS tubes. The gate of one MOS tube is connected to the gate of another MOS tube as the input of the standard three-value NOT gate; the positive electrode of one memristor is connected to the drain of one MOS tube; the positive electrode of another memristor, the negative electrode of one memristor, and the drain of another MOS tube are connected as the output of the standard three-value NOT gate; the negative electrode of the other memristor is connected to the voltage source -V DD , the sources of the two MOS tubes are grounded; the input of the standard three-value NOT gate is connected to the output of a three-value three-input minimum gate;

[0028] The negative three-value NOT gate includes a memristor and a MOS tube. The negative electrode of the memristor is connected to the voltage source -V DD , the positive electrode of the memristor is connected to the drain of the MOS tube as the output end of the negative three-value NOT gate; the gate of the MOS tube is used as the input end of the negative three-value NOT gate, and the source of the MOS tube is grounded; the input end of the negative three-value NOT gate is connected to the output end of the standard three-value NOT gate;

[0029] The three-value two-input OR gate includes two memristors, the positive electrode of one memristor is connected to the output terminal of another three-value three-input minimum gate, and the positive electrode of the other memristor is connected to the voltage source -V DD / 2; the negative electrodes of the two memristors serve as the output terminals of the three-value two-input OR gate;

[0030] The three-value two-input AND gate includes two memristors, the negative electrode of one memristor is connected to the output end of the negative three-value NOT gate; the negative electrode of the other memristor is connected to the output end of the three-value two-input OR gate, and the positive electrodes of the two memristors serve as the output ends of the three-value two-input AND gate.

[0031] The MOS tube involved in the negative three-value 9-line-2-line encoder is a PMOS tube.

[0032] The present invention designs a positive / negative three-value 9-line-2-line encoder circuit, which is composed of a memristor and a MOS tube. The non-volatility, nanometer size and compatibility with CMOS technology of the memristor have great advantages in the design of a three-value digital logic circuit. Compared with the circuit designed using only transistors, the circuit area is smaller, the data density is higher, the structure is simpler, the power consumption is lower and it is more conducive to integration. The three-value digital signal contains more information per bit than the two-value digital signal. Using the three-value digital signal for communication will have a higher transmission rate at the same frequency, and the interconnection of the corresponding logic function circuit will also be reduced, and the digital chip can also be smaller and the cost is lower. Combined with the characteristics of the nanometer size of the memristor, easy integration and compatibility with CMOS technology, the memristor three-value digital logic circuit can further improve the efficiency of information storage, processing and transmission, and bring new breakthroughs to the manufacture of high-density information logic systems. It is of great significance to the application research in many fields such as multi-value digital logic circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a circuit block diagram of a memristor positive three-value 9-line-2-line encoder based on a 3-line-1-line encoder of the present invention;

[0034] Figure 2a It is a circuit schematic diagram of the Y0 output part of the memristor positive three-value 9-line-2-line encoder based on the 3-line-1-line encoder of the present invention;

[0035] Figure 2b It is a circuit schematic diagram of the output part Y1 of the memristor positive three-value 9-line-2-line encoder based on the 3-line-1-line encoder of the present invention. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Due to the logical relativity of the memristor positive and negative three-value 9-line-2-line encoder circuit based on the 3-line-1-line encoder designed in the present invention, the implementation method is described in detail below using the 9-line-2-line positive three-value encoder.

[0038] like Figure 1 As shown, the memristor positive three-value 9-line-2-line encoder circuit based on the 3-line-1-line encoder includes three 3-line-1-line three-value encoders U1, U2, U3, a three-value three-input minimum gate U4, two three-value three-input maximum gates U5, U6, a standard three-value NOT gate U7, a positive three-value NOT gate U8, a three-value two-input AND gate U9 and a three-value two-input OR gate U10. 10 .

[0039] The logic state in the positive three-value 9-wire-2-wire encoder circuit is a voltage value, where the voltage V is defined DD is 1V, corresponding to logic "2"; V DD / 2 is 0.5V, corresponding to logic "1"; GND is 0V, corresponding to logic "0".

[0040] The 3-wire-1-wire encoder is implemented by seven memristors and four MOS tubes. Its function is to input three binary signals and output one three-value signal. The specific input and output logic relationship is shown in the following table:

[0041]

[0042] Among them, I2, I1, I0 are input signals, and Y is the output signal.

[0043] That is, if inputs I2 and I1 are logic "0", I0 is logic "1", and the Y output is logic "0"; if inputs I2 and I0 are logic "0", I1 is logic "1", and the Y output is logic "1"; if inputs I1 and I0 are logic "0", I2 is logic "1", and the Y output is logic "2".

[0044] Each three-value three-input maximum value gate is implemented by three memristors, and its function is to find the logical maximum value of the three input terminals.

[0045] The three-value three-input minimum gate is implemented by three memristors, and its function is to find the logical minimum value of the three input terminals.

[0046] The three-value two-input AND gate is implemented by two memristors, and its function is to perform the “AND” operation of two inputs.

[0047] The three-value two-input OR gate is implemented by two memristors, and its function is to calculate the "OR" operation of two inputs.

[0048] The standard three-value NOT gate is composed of two memristors and two MOS tubes, which can complete the standard three-value logic "NOT" operation.

[0049] The positive three-value NOT gate is composed of a memristor and a MOS tube, which can complete the positive three-value logic "NOT" operation.

[0050] The input-output relationship table of the memristor positive and negative three-value 9-line-2-line encoder circuit based on the 3-line-1-line encoder of the present invention is shown in the following table:

[0051]

[0052] Among them, X8, X7, X6, X5, X4, X3, X2, X1, and X0 are nine input signals, and Y1 and Y0 are two output signals.

[0053] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 0, 0, 0, 0, 0, 1}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "2", and "0" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "0", that is, the first output terminal Y0 outputs logic "0"; the first three-value three-input maximum gate U5 and the second three-value three-input maximum gate U6 both output logic "0", the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "0", that is, the second output terminal Y1 outputs logic "0".

[0054] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 0, 0, 0, 0, 1, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "2", and "1" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "1", that is, the first output terminal Y0 outputs logic "1"; the first three-value three-input maximum gate U5 and the second three-value three-input maximum gate U6 both output logic "0", the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "0", that is, the second output terminal Y1 outputs logic "0".

[0055] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 0, 0, 0, 1, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "2", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "2", that is, the first output terminal Y0 outputs logic "2"; the first three-value three-input maximum gate U5 and the second three-value three-input maximum gate U6 both output logic "0", the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "0", that is, the second output terminal Y1 outputs logic "0".

[0056] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 0, 0, 1, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "0", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "0", that is, the first output terminal Y0 outputs logic "0"; the first three-value three-input maximum gate U5 outputs logic "0", the second three-value three-input maximum gate U6 outputs logic "1", and the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "1", and finally the first three-value two-input OR gate U9 outputs logic "1", that is, the second output terminal Y1 outputs logic "1".

[0057] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 0, 1, 0, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "1", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "1", that is, the first output terminal Y0 outputs logic "1"; the first three-value three-input maximum gate U5 outputs logic "0", the second three-value three-input maximum gate U6 outputs logic "1", and the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "1", and finally the first three-value two-input OR gate U9 outputs logic "1", that is, the second output terminal Y1 outputs logic "1".

[0058] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 0, 1, 0, 0, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "2", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "2", that is, the first output terminal Y0 outputs logic "2"; the first three-value three-input maximum gate U5 outputs logic "0", the second three-value three-input maximum gate U6 outputs logic "1", and the first standard three-value NOT gate U7 outputs logic "2", then the first positive three-value NOT gate U8 outputs logic "0", the first three-value two-input AND gate U9 outputs logic "1", and finally the first three-value two-input OR gate U9 outputs logic "1", that is, the second output terminal Y1 outputs logic "1".

[0059] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 0, 1, 0, 0, 0, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "0", "2", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "0", that is, the first output terminal Y0 outputs logic "0"; the first three-value three-input maximum gate U5 outputs logic "1", the second three-value three-input maximum gate U6 outputs logic "0", and the first standard three-value NOT gate U7 outputs logic "1", then the first positive three-value NOT gate U8 outputs logic "2", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "2", that is, the second output terminal Y1 outputs logic "2".

[0060] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {0, 1, 0, 0, 0, 0, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "1", "2", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "1", that is, the first output terminal Y0 outputs logic "1"; the first three-value three-input maximum gate U5 outputs logic "1", the second three-value three-input maximum gate U6 outputs logic "0", and the first standard three-value NOT gate U7 outputs logic "1", then the first positive three-value NOT gate U8 outputs logic "2", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "2", that is, the second output terminal Y1 outputs logic "2".

[0061] When the input signal {X8, X7, X6, X5, X4, X3, X2, X1, X0} is logic {1, 0, 0, 0, 0, 0, 0, 0, 0}, the three 3-line-1-line encoders U1, U2, and U3 output logic "2", "2", and "2" respectively. At this time, the first three-value three-input minimum gate U4 outputs logic "2", that is, the first output terminal Y0 outputs logic "2"; the first three-value three-input maximum gate U5 outputs logic "1", the second three-value three-input maximum gate U6 outputs logic "0", and the first standard three-value NOT gate U7 outputs logic "1", then the first positive three-value NOT gate U8 outputs logic "2", the first three-value two-input AND gate U9 outputs logic "0", and finally the first three-value two-input OR gate U9 outputs logic "2", that is, the second output terminal Y1 outputs logic "2".

[0062] The detailed circuit schematic diagram corresponding to the above circuit block diagram is shown in Figure 2, where the Y0 output circuit part corresponds to Figure 2a , the Y1 output circuit part corresponds to Figure 2b .

[0063] The first 3-line-1-line encoder is composed of a first memristor M1, a second memristor M2, a third memristor M3, a fourth memristor M4, a fifth memristor M5, a sixth memristor M6, a seventh memristor M7, a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, and a fourth MOS transistor T4. The negative electrode of the first memristor M1 is connected to the voltage source V DD The positive electrode of the first memristor M1 and the drain of the first MOS transistor T1 are connected to the negative electrode of the fifth memristor M5. The gate of the first MOS transistor T1 serves as the input terminal X8 of the 9-wire-2-wire encoder of the present invention, and the source of the first MOS transistor T1 is connected to the ground. The negative electrode of the second memristor M2 is connected to the voltage source V DD The positive electrode of the second memristor M2, the negative electrode of the third memristor M3, and the drain of the third MOS tube T3 are connected to the negative electrode of the sixth memristor M6. The gate of the second MOS tube T2 is connected to the gate of the third MOS tube T3 and serves as the input terminal X7 of the 9-line-2-line encoder of the present invention. The drain of the second MOS tube T2 is connected to the positive electrode of the third memristor M3. The source of the second MOS tube T2 is grounded, and the source of the third MOS tube T3 is grounded. The negative electrode of the fourth memristor M4 is connected to the voltage source V DD The positive electrode of the fourth memristor M4 and the drain of the fourth MOS tube T4 are connected to the negative electrode of the seventh memristor M7. The gate of the fourth MOS tube T4 serves as the input terminal X6 of the 9-line-2-line encoder of the present invention, and the source of the fourth MOS tube T4 is grounded. The positive electrode of the fifth memristor M5, the positive electrode of the sixth memristor M6, and the positive electrode of the seventh memristor M7 are connected to the twenty-second memristor M 22 and serves as the output end of the first positive three-value 3-line-1-line encoder.

[0064] The second positive three-value 3-line-1-line encoder is composed of the eighth memristor M8, the ninth memristor M9, the tenth memristor M 10 、The eleventh memristor M 11 , the twelfth memristor M 12 、The thirteenth memristor M 13 、The fourteenth memristor M 14 The negative electrode of the eighth memristor M8 is connected to the voltage source V DD The positive electrode of the eighth memristor M8, the drain of the fifth MOS tube T5 and the twelfth memristor M 12 The gate of the fifth MOS transistor T5 serves as the input terminal X5 of the 9-line-2-line encoder of the present invention, and the source of the fifth MOS transistor T5 is connected to the ground. The negative electrode of the ninth memristor M9 is connected to the voltage source V DD The positive electrode of the ninth memristor M9 and the tenth memristor M 10The negative electrode of the seventh MOS tube T7, the drain of the seventh MOS tube T7 and the thirteenth memristor M 13 The gate of the sixth MOS transistor T6 is connected to the gate of the seventh MOS transistor T7 and serves as the input terminal X4 of the 9-line-2-line encoder of the present invention. The drain of the sixth MOS transistor T6 is connected to the negative electrode of the tenth memristor M 10 The positive electrode of the sixth MOS tube T6 is connected to the ground, the source of the seventh MOS tube T7 is grounded. 11 The negative terminal of the DD connected, the eleventh memristor M 11 The positive electrode of the eighth MOS tube T8, the drain of the fourth memristor M 14 The gate of the eighth MOS transistor T8 serves as the input terminal X3 of the 9-line-2-line encoder of the present invention, and the source of the eighth MOS transistor T8 is grounded. 12 The positive electrode of the thirteenth memristor M 13 The positive electrode of the fourteenth memristor M 14 The positive electrode of the twenty-third memristor M 23 and serves as the output end of the second positive three-value 3-line-1-line encoder.

[0065] The third positive three-value 3-line-1-line encoder is composed of the fifteenth memristor M 15 、16th memristor M 16 、The seventeenth memristor M 17 , the eighteenth memristor M 18 、Nineteenth memristor M 19 、The twentieth memristor M 20 、The twenty-first memristor M 21 , the ninth MOS tube T9, the tenth MOS tube T 10 、Eleventh MOS tube T 11 、Twelfth MOS tube T 12 The fifteenth memristor M 15 The negative terminal of the voltage source V DD Connected, the fifteenth memristor M 15 The positive electrode, the drain electrode of the ninth MOS tube T9 and the nineteenth memristor M 19 The gate of the ninth MOS transistor T9 serves as the input terminal X2 of the 9-line-2-line encoder of the present invention, and the source of the ninth MOS transistor T9 is connected to the ground. 16 The negative terminal of the DD Connected, the sixteenth memristor M 16 The positive electrode of the seventeenth memristor M 17 The negative pole of the eleventh MOS tube T 11 The drain of the twentieth memristor M 20 The tenth MOS tube T10 The gate of the eleventh MOS tube T 11 The gate of the MOS tube T is connected to the input terminal X1 of the 9-line-2-line encoder of the present invention. 10 The drain of the seventeenth memristor M 17 The positive electrode of the tenth MOS tube T 10 The source of the eleventh MOS tube T is grounded. 11 The source of the eighteenth memristor M is grounded. 18 The negative terminal of the voltage source V DD Connected, the eighteenth memristor M 18 The positive electrode of the twelfth MOS tube T 12 The drain of the twenty-first memristor M 21 The twelfth MOS tube T 12 The gate of the 12th MOS tube T is used as the input terminal X0 of the 9-line-2-line encoder of the present invention. 12 The source of the nineteenth memristor M is grounded. 19 The positive electrode of the twentieth memristor M 20 The positive electrode of the twenty-first memristor M 21 The positive electrode of the twenty-fourth memristor M 24 and serves as the output end of the third positive three-value 3-line-1-line encoder.

[0066] The twenty-second memristor M 22 、The twenty-third memristor M 23 With the twenty-fourth memristor M 24 A three-value three-input minimum gate is formed. 22 The positive electrode of the twenty-third memristor M 23 The positive electrode of the twenty-fourth memristor M 24 and serves as the output terminal Y0 of the 9-line-2-line encoder of the present invention.

[0067] The twenty-fifth memristor M 25 、Twenty-sixth memristor M 26 and the twenty-seventh memristor M 27 The first three-value three-input maximum gate U5 and the twenty-eighth memristor M 28 、The twenty-ninth memristor M 29 and the 30th memristor M 30 The second three-value three-input maximum gate U6 is formed, and the thirty-first memristor M 31 、32nd memristor M 32 、Thirteenth MOS tube T 13 And the fourteenth MOS tube T 14 Construct a standard three-value NOT gate U7, the thirty-third memristor M 33 And the fifteenth MOS tube T15 Constitute a positive three-value NOT gate U8, the thirty-fourth memristor M 34 、35th memristor M 35 A two-input three-value AND gate U9 is formed, and the thirty-sixth memristor M 36 、37th memristor M 37 Construct a two-input three-value OR gate U 10 . The twenty-fifth memristor M 25 The positive electrode of the twenty-sixth memristor M 26 The positive electrode of the twenty-seventh memristor M 27 The positive electrode of the twenty-eighth memristor M 28 The positive electrode of the twenty-ninth memristor M 29 The positive electrode and the 30th memristor M 30 The positive electrodes are respectively connected to the input terminals X8, X7, X6, X5, X4, and X3 of the 9-line-2-line encoder of the present invention. 25 The negative electrode of the twenty-sixth memristor M 26 The negative electrode of the twenty-seventh memristor M 27 The negative pole of the 13th MOS tube T 13 The gate of the fourteenth MOS tube T 14 The gate of the twenty-eighth memristor M 28 The negative electrode of the twenty-ninth memristor M 29 The negative electrode of the 30th memristor M 30 The negative electrode and the thirty-fourth memristor M 34 The thirty-first memristor M 31 The negative terminal of the DD Connected, the thirty-first memristor M 31 The positive electrode of the thirty-second memristor M 32 The negative electrode of the fourteenth MOS tube T 14 The drain of the fifteenth MOS tube T 15 The gate of the thirty-second memristor M 32 The positive electrode and the thirteenth MOS tube T 13 The drain of the thirteenth MOS tube T 13 The source of the fourteenth MOS tube T is grounded. 14 The source of the fifteenth MOS tube T is grounded. 15 The source of is grounded. 33 The negative terminal of the DD Connected, the thirty-third memristor M 33 The positive electrode of the fifteenth MOS tube T 15 The drain of the thirty-sixth memristor M 36 The thirty-fifth memristor M 35 The negative terminal is connected to the voltage source VDD / 2, the thirty-fifth memristor M 35 The positive electrode of the thirty-fourth memristor M 34 The positive electrode and the thirty-seventh memristor M 37 The thirty-sixth memristor M 36 The negative electrode and the thirty-seventh memristor M 37 and serves as the output terminal Y1 of the 9-line-2-line encoder of the present invention.

[0068] For the negative three-value 9-wire-2-wire encoder circuit, just change Figure 1 The 3-line-1-line encoder is replaced with a negative three-value 3-line-1-line encoder, the three-input minimum gate is replaced with a negative three-value three-input maximum gate, the three-input maximum gate is replaced with a negative three-value minimum gate, the standard three-value NOT gate is replaced with a negative three-value standard three-value NOT gate, the positive three-value NOT gate is replaced with a negative three-value negative three-value NOT gate, the two-input AND gate is replaced with a negative three-value two-input OR gate, and the two-input OR gate is replaced with a negative three-value two-input AND gate. Due to the logical relativity of positive three-value and negative three-value, the detailed principle will not be repeated here.

[0069] Similarly, for the negative three-value 9-line-2-line encoder circuit, all NMOS tubes in FIG. 2 are replaced with PMOS tubes, and the first memristor M1, the second memristor M2, the fourth memristor M4, the eighth memristor M8, the ninth memristor M9, the eleventh memristor M 11 、15th memristor M 15 、16th memristor M 16 , the eighteenth memristor M 18 、The thirty-first memristor M 31 、33rd memristor M 33 The negative poles of the DD , the thirty-fifth memristor M 35 The positive terminal is connected to the voltage source -V DD / 2, the logical function of the negative three-value 9-line-2-line encoder can be completed. The specific working principle is similar to that of the positive three-value 9-line-2-line encoder, which will not be repeated here.

[0070] For the 9-wire-2-wire negative three-value encoder circuit, according to the different logic states of the input signals {X8, X7, X6, X5, X4, X3, X2, X1, X0}, the two output terminals of the memristor-based 9-wire-2-wire negative three-value encoder are in different states:

[0071] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, 0, 0, 0, 0, 0, -1}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {0, 0};

[0072] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, 0, 0, 0, 0, -1, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {0, -1};

[0073] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, 0, 0, 0, -1, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {0, -2};

[0074] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, 0, 0, -1, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-1, 0};

[0075] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, 0, -1, 0, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-1, -1};

[0076] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, 0, -1, 0, 0, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-1, -2};

[0077] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, 0, -1, 0, 0, 0, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-2, 0};

[0078] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {0, -1, 0, 0, 0, 0, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-2, -1};

[0079] The input {X8, X7, X6, X5, X4, X3, X2, X1, X0} of the 9-line-2-line negative three-value encoder is logic {-1, 0, 0, 0, 0, 0, 0, 0}, and the output end {Y1, Y0} of the 9-line-2-line encoder circuit is {-2, -2};

[0080] Those skilled in the art should realize that the above embodiments are only used to verify the present invention, and are not intended to limit the present invention. As long as they are within the scope of the present invention, any changes or modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. A memristor positive three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder, characterized in that: The encoder comprises a first 3-line-1-line encoder U1, a second 3-line-1-line encoder U2 and a third 3-line-1-line encoder U3, a three-value three-input minimum gate U4, a first three-value three-input maximum gate U5, a second three-value three-input maximum gate U6, a standard three-value NOT gate U7, a positive three-value NOT gate U8, a three-value two-input AND gate U9 and a three-value two-input OR gate U10. 10 ; The 3-line-1-line encoder is used to input three binary signals and output one three-value signal; each three-value three-input maximum value gate is used to output the logical maximum value of the three input terminals, the three-value three-input minimum value gate is used to output the logical minimum value of the three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of the two inputs, the three-value two-input OR gate is used to complete the "OR" operation of the two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation; The input terminals of the first 3-line-1-line encoder U1, the second 3-line-1-line encoder U2 and the third 3-line-1-line encoder U3 are from high I 2 to low I 0 as 9-way input terminal of 9-line-2-line encoder X 8. X 7. X 6. X 5. X 4. X 3. X 2. X 1. X 0; the output end of the first 3-line-1-line encoder U1 is connected to one of the input ends of the three-value three-input minimum gate U4, the output end of the second 3-line-1-line encoder U2 is connected to the second input end of the three-value three-input minimum gate U4, and the output end of the third 3-line-1-line encoder U3 is connected to the third input end of the three-value three-input minimum gate U4; the output end of the first three-value three-input minimum gate U4 is used as the first output end Y 0; The three input terminals of the first three-value three-input maximum gate U5 are respectively connected to the input terminals X 8. X 7. X 6, the three input terminals of the second three-value three-input maximum gate U6 are respectively connected to the input terminals X 5. X 4. X 3 connection; the output end of the first three-value three-input maximum gate U5 is connected to the input end of the standard three-value NOT gate U7, and the output end of the standard three-value NOT gate U7 is connected to the input end of the positive three-value NOT gate U8; the two input ends of the three-value two-input AND gate U9 are respectively connected to the output end of the second three-value three-input maximum gate U6 and the voltage source V DD / 2 connection; three-value two-input OR gate U 10 The two input ends of the positive three-value NOT gate U8 and the output end of the three-value two-input AND gate U9 are connected respectively. 10 The output terminal is used as the second output terminal Y 1; According to the input signal { X 8. X 7. X 6. X 5. X 4. X 3. X 2. X 1. X 0}, the output states of the two output terminals of the encoder are different; The 3-wire-1-wire encoders each include seven memristors and four MOS tubes. M The negative terminal of 1 is connected to the voltage source V DD Connected, the first memristor M 1's positive electrode, the first MOS tube T 1 and the drain of the fifth memristor M 5 is connected to the negative pole; the first MOS tube of the three 3-wire-1-wire encoders T The gate of 1 is used as the input terminal of the 9-line-2-line encoder X 8. X 5. X 2. The first MOS tube T 1's source is connected to ground; the second memristor M The negative terminal of 2 is connected to the voltage source V DD Connected, the second memristor M 2's positive electrode, the third memristor M 3's negative pole, the third MOS tube T The drain of 3 and the sixth memristor M The negative pole of 6 is connected; the second MOS tube of the three 3-wire-1-wire encoders T 2 and the gate of the third MOS tube T 3 and serve as the input terminals of the 9-wire-2-wire encoder. X 7 、X 4. X 1. Second MOS tube T 2 and the drain of the third memristor M 3 is connected to the positive pole, the second MOS tube T 2's source is grounded, and the third MOS tube T The source of 3 is grounded; the fourth memristor M The negative terminal of 4 is connected to the voltage source V DD Connected, the fourth memristor M 4's positive electrode, the fourth MOS tube T The drain of 4 and the seventh memristor M 7 is connected to the negative pole; the fourth MOS tube of the three 3-wire-1-wire encoders T The gate of 4 is used as the input of the 9-wire-2-wire encoder X 6. X 3. X 0, the fourth MOS tube T The source of 4 is grounded; the fifth memristor M The positive electrode of 5, the sixth memristor M The positive electrode of 6, the seventh memristor M The positive electrode of 7 is connected as the output end of the 3-line-1-line encoder; the three-value three-input minimum gate U4 includes three memristors, the negative electrodes of the three memristors are respectively used as the input ends of the three-value three-input minimum gate, connected to the output ends of the three 3-line-1-line encoders, and the positive electrodes of the three memristors are used as the output ends of the three-value three-input minimum gate; The first three-value three-input maximum gate U5 and the second three-value three-input maximum gate U6 each include three memristors, the positive electrodes of the three memristors are respectively used as the input terminals of each three-value three-input maximum gate, and connected to the input terminals of the 9-line-2-line encoder. X 8. X 7. X 6. X 5. X 4. X 3 are connected, and the negative electrodes of the three memristors serve as the output terminals of each three-value three-input maximum value gate; The standard three-value NOT gate U7 includes two memristors and two MOS tubes. The gate of one MOS tube is connected to the gate of another MOS tube and serves as the input of the standard three-value NOT gate U7. The positive electrode of one memristor is connected to the drain of one MOS tube. The positive electrode of another memristor, the negative electrode of one memristor, and the drain of another MOS tube are connected to serve as the output of the standard three-value NOT gate U7. The negative electrode of the other memristor is connected to the voltage source V DD , the sources of the two MOS tubes are grounded; the input end of the standard three-value NOT gate U7 is connected to the output end of a three-value three-input maximum value gate; The positive three-value NOT gate U8 includes a memristor and a MOS tube. The negative electrode of the memristor is connected to the voltage source V DD , the positive electrode of the memristor is connected to the drain of the MOS tube as the output end of the positive three-value NOT gate U8; the gate of the MOS tube is used as the input end of the positive three-value NOT gate U8, and the source of the MOS tube is grounded; the input end of the positive three-value NOT gate U8 is connected to the output end of the standard three-value NOT gate U7; The three-value two-input AND gate U9 includes two memristors, the negative electrode of one memristor is connected to the output terminal of another three-value three-input maximum gate, and the negative electrode of the other memristor is connected to the voltage source V DD / 2; the positive electrodes of the two memristors serve as the output terminals of the three-value two-input AND gate U9; Three-value two-input OR gate U 10 It includes two memristors, the positive electrode of one memristor is connected to the output end of the positive three-value NOT gate U8; the positive electrode of the other memristor is connected to the output end of the three-value two-input AND gate U9, and the negative electrodes of the two memristors are used as the three-value two-input OR gate U 10 The output terminal.

2. A memristor positive three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder as claimed in claim 1, characterized in that: The MOS tube is an NMOS tube.

3. A memristor negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder, characterized in that: It includes a first 3-line-1-line encoder, a second 3-line-1-line encoder and a third 3-line-1-line encoder, a three-value three-input maximum value gate, a first three-value three-input minimum value gate, a second three-value three-input minimum value gate, a standard three-value NOT gate, a negative three-value NOT gate, a three-value two-input OR gate, and a three-value two-input AND gate; The 3-line-1-line encoder is used to input three binary signals and output one three-value signal; the three-value three-input maximum value gate is used to output the logical maximum value of the three input terminals, each three-value three-input minimum value gate is used to output the logical minimum value of the three input terminals, the three-value two-input AND gate is used to complete the "AND" operation of the two inputs, the three-value two-input OR gate is used to complete the "OR" operation of the two inputs, the standard three-value NOT gate is used to complete the standard three-value logic "NOT" operation, and the positive three-value NOT gate is used to complete the positive three-value logic "NOT" operation; The input ends of the first 3-line-1-line encoder, the second 3-line-1-line encoder and the third 3-line-1-line encoder are respectively used as 9-way input ends of the 9-line-2-line encoder X 8. X 7. X 6. X 5. X 4. X 3. X 2. X 1. X 0; the output end of the first 3-line-1-line encoder is connected to one of the input ends of the three-value three-input maximum value gate, the output end of the second 3-line-1-line encoder is connected to the second input end of the three-value three-input maximum value gate, and the output end of the third 3-line-1-line encoder is connected to the third input end of the three-value three-input maximum value gate; the output end of the three-value three-input maximum value gate U4 is used as the first output end Y 0; The three input terminals of the first three-value three-input minimum gate are respectively connected to the input terminals X 8. X 7. X 6, the three input terminals of the second three-value three-input minimum gate are connected to the input terminals X 5. X 4. X 3 connections; the output end of the first three-value three-input minimum gate is connected to the input end of the standard three-value NOT gate, and the output end of the standard three-value NOT gate is connected to the input end of the negative three-value NOT gate; the two input ends of the three-value two-input OR gate are respectively connected to the output end of the second three-value three-input minimum gate and the voltage source -V DD / 2 connection; the two input ends of the three-value two-input AND gate are respectively connected to the output end of the negative three-value NOT gate and the output end of the three-value two-input OR gate, and the output end of the three-value two-input AND gate is used as the second output end Y 1; According to the input signal { X 8. X 7. X 6. X 5. X 4. X 3. X 2. X 1. X 0}, the output states of the two output terminals of the encoder are different; The 3-wire-1-wire encoders each include seven memristors and four MOS tubes. M The negative terminal of 1 is connected to the voltage source -V DD Connected, the first memristor M 1's positive electrode, the first MOS tube T 1 and the drain of the fifth memristor M 5 is connected to the positive pole; the first MOS tube of the three 3-wire-1-wire encoders T The gate of 1 is used as the input terminal of the 9-line-2-line encoder X 8. X 5. X 2. The first MOS tube T 1's source is connected to ground; the second memristor M The negative terminal of 2 is connected to the voltage source -V DD Connected, the second memristor M 2's positive electrode, the third memristor M 3's negative pole, the third MOS tube T The drain of 3 and the sixth memristor M The positive pole of 6 is connected to the second MOS tube of the three 3-wire-1-wire encoders T 2 and the gate of the third MOS tube T 3 and serve as the input terminals of the 9-wire-2-wire encoder. X 7 、X 4. X 1. Second MOS tube T 2 and the drain of the third memristor M 3 is connected to the positive pole, the second MOS tube T 2's source is grounded, and the third MOS tube T The source of 3 is grounded; the fourth memristor M The negative terminal of 4 is connected to the voltage source -V DD Connected, the fourth memristor M 4's positive electrode, the fourth MOS tube T The drain of 4 and the seventh memristor M The positive pole of 7 is connected; the fourth MOS tube of the three 3-wire-1-wire encoders T The gate of 4 is used as the input of the 9-wire-2-wire encoder X 6. X 3. X 0, the fourth MOS tube T The source of 4 is grounded; the fifth memristor M Negative electrode of 5, sixth memristor M Negative electrode of 6, seventh memristor M 7 is connected to the negative electrode as the output end of the 3-line-1-line encoder; the three-value three-input minimum gate U4 includes three memristors, the positive electrodes of the three memristors are respectively used as the input ends of the three-value three-input minimum gate, connected to the output ends of the three 3-line-1-line encoders, and the negative electrodes of the three memristors are used as the output ends of the three-value three-input minimum gate; The first three-value three-input minimum gate and the second three-value three-input minimum gate each include three memristors, and the negative electrodes of the three memristors are respectively used as the input terminals of each three-value three-input minimum gate and connected to the input terminals of the 9-line-2-line encoder. X 8. X 7. X 6. X 5. X 4. X 3 are connected, and the positive electrodes of the three memristors serve as the output terminals of each three-value three-input minimum gate; The standard three-value NOT gate includes two memristors and two MOS tubes. The gate of one MOS tube is connected to the gate of another MOS tube as the input of the standard three-value NOT gate; the positive electrode of one memristor is connected to the drain of one MOS tube; the positive electrode of another memristor, the negative electrode of one memristor, and the drain of another MOS tube are connected as the output of the standard three-value NOT gate; the negative electrode of the other memristor is connected to the voltage source -V DD , the sources of the two MOS tubes are grounded; the input of the standard three-value NOT gate is connected to the output of a three-value three-input minimum gate; The negative three-value NOT gate includes a memristor and a MOS tube. The negative electrode of the memristor is connected to the voltage source -V DD , the positive electrode of the memristor is connected to the drain of the MOS tube as the output end of the negative three-value NOT gate; the gate of the MOS tube is used as the input end of the negative three-value NOT gate, and the source of the MOS tube is grounded; the input end of the negative three-value NOT gate is connected to the output end of the standard three-value NOT gate; The three-value two-input OR gate includes two memristors, the positive electrode of one memristor is connected to the output terminal of another three-value three-input minimum gate, and the positive electrode of the other memristor is connected to the voltage source -V DD / 2; the negative electrodes of the two memristors serve as the output terminals of the three-value two-input OR gate; The three-value two-input AND gate includes two memristors, the negative electrode of one memristor is connected to the output end of the negative three-value NOT gate; the negative electrode of the other memristor is connected to the output end of the three-value two-input OR gate, and the positive electrodes of the two memristors serve as the output ends of the three-value two-input AND gate.

4. A memristor negative three-value 9-line-2-line encoder circuit based on a 3-line-1-line encoder as claimed in claim 3, characterized in that: The MOS tube is a PMOS tube.

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