Display panel and display device

Abstract

An embodiment of the present invention provides a display panel and a display device. The display panel includes a scan line extending along a first direction and a longitudinal reset line extending along a second direction, and the first direction and the second direction intersect each other; the display panel includes a display area, and adjacent longitudinal reset lines in the display area are disconnected from each other. The present invention can improve display unevenness and enhance display uniformity.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) has many advantages such as self-luminescence, fast response time, wide viewing angle, low cost, simple manufacturing process, good resolution and high brightness, which can meet consumers' new demands for display products. Current OLED display products have the problem of uneven display, which affects the user's visual experience. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the problem of uneven display in the prior art and improve the display effect.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising scan lines extending along a first direction and longitudinal reset lines extending along a second direction, wherein the first direction and the second direction intersect with each other; the display panel comprises a display area, wherein adjacent longitudinal reset lines in the display area are disconnected from each other.

[0005] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided by any embodiment of the present invention.

[0006] The display panel and display device provided by the embodiment of the present invention have the following beneficial effects: a longitudinal reset line is set in the display panel, the extension direction of the longitudinal reset line intersects with the extension direction of the scanning line, and adjacent longitudinal reset lines are disconnected from each other in the display area. When displaying by row driving, in the same period of driving a row of pixel circuits, part of the pixel circuits in a row of pixel circuits connected thereto are reset by the longitudinal reset line, and the number of pixel circuits reset by a longitudinal reset line is reduced, the voltage drop on the longitudinal reset line is significantly reduced, and the reset conditions of the pixel circuits connected to the same longitudinal reset line in a row of pixel circuits are relatively different. And because the longitudinal reset lines are disconnected from each other in the display area, the pixel circuits in a row of pixel circuits respectively coupled to the adjacent longitudinal reset lines will not affect each other when resetting, so that the reset conditions of the pixel circuits at different positions in the pixel circuit row are relatively different, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits at different positions in the pixel circuit row, and improving the display unevenness problem. In addition, the reset conditions of pixel circuits in a row of pixel circuits connected to the same vertical reset line are less different, which can also reduce the occurrence of insufficient reset of the pixel circuits and avoid dark-state luminescence. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0008] Figure 1 It is a schematic diagram of a pixel circuit in the prior art;

[0009] Figure 2 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0010] Figure 3 A schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention;

[0011] Figure 4 A schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention;

[0012] Figure 5 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0013] Figure 6 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 7 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 8 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0016] Fig. 9 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0017] Fig.10 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0018] Fig.11 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0019] Fig.12 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Fig.13 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Fig.14 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Fig.15 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Fig.16 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] Fig.17 for Fig.10 Schematic diagram of the cross section at the midline A-A';

[0025] Fig.18 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.19 for Fig.18 Schematic diagram of the cross section at the midline BB';

[0027] Fig. 20 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0028] Fig.21 for Fig. 20 Schematic diagram of the cross section at the midline C-C';

[0029] Fig. 22 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0030] Fig.23 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0031] Fig.24 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0032] Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0035] In OLED display technology, OLED devices are driven by current, and a pixel circuit is provided in the display panel to provide driving current for the OLED. Figure 1 Schematic diagram of a pixel circuit in the prior art, such as Figure 1 As shown, the pixel circuit at least includes a driving module 01, a data writing module 02, and a first reset module 03. The working cycle of the pixel circuit at least includes a reset phase, a data writing phase, and a light-emitting phase. In the reset phase, the first reset module 03 is turned on to reset the driving module 01; in the data writing phase, the data writing module 02 is turned on to write a data voltage to the driving module 01; in the light-emitting phase, the driving module 01 generates a driving current and provides the driving current to the light-emitting device 04.

[0036] The inventors analyzed the reasons for uneven display of the display panel based on the working process of the pixel circuit, and believed that the reset of the driving module 01 in the reset stage will affect the magnitude of the driving current in the subsequent light-emitting stage, thereby affecting the brightness of the light-emitting device 04. When there are differences in the reset conditions of the pixel circuits in the display panel, the brightness of the light-emitting device 04 will be different, resulting in uneven display.

[0037] In some display panels, the pixel circuit further includes a second reset module, which is coupled to the light emitting device 04 and is used to reset the electrodes of the light emitting device 04. The reset condition of the electrodes of the light emitting device 04 will also affect the light emission of the light emitting device 04. When there are differences in the reset conditions of the pixel circuits in the display panel, the brightness of the light emitting device 04 will also be different, resulting in uneven display.

[0038] In addition, insufficient reset of the pixel circuit may lead to inaccurate pixel brightness, especially when displaying low grayscale dark state, dark state luminescence may occur, which not only causes uneven display but also reduces contrast.

[0039] The display panel is provided with a plurality of pixel circuit rows, a plurality of reset lines and a plurality of scan lines, the reset lines and the scan lines have the same extension direction, a reset line is coupled to a plurality of pixel circuits in a row of pixel circuit rows, and a scan line is coupled to a plurality of pixel circuits in a row of pixel circuit rows. Among them, the reset line is used to provide a reset signal to the pixel circuit. In the prior art, the display panel is displayed in a row-by-row driving mode. In the same period when a row of pixel circuit rows is driven to work, a reset line provides a reset signal to all pixel circuits in a row of pixel circuit rows. Since the reset line needs to be connected to all pixel circuits in a row of pixel circuit rows, the length of the reset line is long and the voltage drop is large. The reset signal on the reset line is usually transmitted from both ends of the line to the middle, or the reset signal is transmitted from one end of the reset line to the other end. Due to the existence of the voltage drop, the reset conditions of the pixel circuits at the near and far positions of the pixel circuit row from the reset signal input end are different, so that there is a brightness difference between the pixels driven by the pixel circuits at different positions in the pixel circuit row, resulting in uneven display. In addition, the pixel circuit at the far end position of the reset signal input end may have the problem of insufficient reset, resulting in dark state luminescence.

[0040] For large-size products, the length of the reset line will be relatively longer, and the reset line will cause different pixel circuit reset conditions at different positions in the pixel circuit row, which will cause more serious display unevenness. For high-frequency display products, the high-frequency display will shorten the row drive time, and the reset time will be shortened, which will also aggravate the display unevenness caused by different pixel circuit reset conditions at different positions in the pixel circuit row.

[0041] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a display panel, which designs the wiring method of the reset line in the display area, changes the reset line originally extending in the horizontal direction to extend in the vertical direction, and sets the reset line extending in the vertical direction to be unconnected in the display area. Then, when displaying by row, in the same period of driving a row of pixel circuits, the pixel circuits connected to it are reset through the vertical reset line, instead of resetting all the pixel circuits in a row of pixel circuits through a horizontally extending reset line. In the same period, the number of pixel circuits reset by a vertical reset line is small, so the voltage drop on the vertical reset line is significantly reduced, and the reset conditions of the pixel circuits connected to the same vertical reset line in a row of pixel circuits are relatively small, thereby improving the problem of uneven display.

[0042] Figure 2 A schematic diagram of a display panel provided by an embodiment of the present invention, such as Figure 2As shown, the display panel includes a display area AA and a non-display area NA. The display panel includes a plurality of pixel circuits 10, and the plurality of pixel circuits 10 are arranged in an array, wherein the pixel circuits 10 are arranged into pixel circuit rows 10H along a first direction x, and the pixel circuits 10 are arranged into pixel circuit columns 10L along a second direction y, and the first direction x and the second direction y intersect each other; the first direction x can be considered as a horizontal direction, and the second direction y can be considered as a vertical direction. The pixel circuit 10 is only illustrated in a block diagram, and the structure of the pixel circuit 10 will be illustrated in the following specific embodiments.

[0043] The display area AA of the display panel further includes a light emitting device, and a pixel circuit 10 is coupled to at least one light emitting device, and the pixel circuit 10 is used to drive the light emitting device to emit light. The light emitting device may be an organic light emitting device or an inorganic light emitting device.

[0044] The display panel includes a scan line 20 extending along a first direction x and a longitudinal reset line 30 extending along a second direction y. The longitudinal reset line 30 is insulated and crosses the scan line 20. A row of pixel circuits 10H is connected to the same scan line 20, that is, the scan line 20 drives a plurality of pixel circuits 10 in a row of pixel circuits 10H.

[0045] The adjacent longitudinal reset lines 30 in the display area AA are disconnected from each other. In the present invention, "disconnected from each other" means not connected. The adjacent longitudinal reset lines 30 in the display area AA are disconnected from each other, indicating that the display panel includes at least two longitudinal reset lines 30, and the adjacent longitudinal reset lines 30 are not connected in the display area AA. The adjacent longitudinal reset lines 30 are not electrically connected in the display area AA. In the embodiment of the present invention, a row of pixel circuits 10H is driven by at least two longitudinal reset lines 30.

[0046] Figure 2 In the figure, a vertical reset line 30 is used to electrically connect three pixel circuit columns 10L. For a pixel circuit row 10H, a vertical reset line 30 connects three pixel circuits 10 in a pixel circuit row 10H. In the embodiment of the present invention, there is no specific limitation on the number of pixel circuits 10 belonging to the same pixel circuit row 10H connected by a vertical reset line 30. Different schemes will be described in detail in the following specific embodiments.

[0047] In the prior art, during the same period of driving a row of pixel circuits, a horizontally extending reset line is used to reset all pixel circuits in a row of pixel circuits. When the reset line writes a reset signal into the pixel circuit, a reset current is generated on the reset line, and the reset current causes a voltage drop in the reset signal. As a result, the reset conditions of the pixel circuits at different positions in the row of pixel circuits are different due to the horizontally extending reset line, resulting in uneven display.

[0048] A longitudinal reset line 30 is provided in the display panel provided by the embodiment of the present invention, and the extension direction of the longitudinal reset line 30 intersects with the extension direction of the scan line 20, and adjacent longitudinal reset lines 30 are disconnected from each other in the display area AA. A row of pixel circuits 10H is driven by a scan line 20, and a row of pixel circuits 10H is driven by at least two longitudinal reset lines 30. When displaying by row-by-row driving, in the same period of driving a row of pixel circuits 10H, part of the pixel circuits 10 in a row of pixel circuits 10H connected thereto are reset by the longitudinal reset line 30, and the number of pixel circuits 10 reset by a longitudinal reset line 30 is reduced, the voltage drop on the longitudinal reset line 30 is significantly reduced, and the reset conditions of the pixel circuits 10 connected to the same longitudinal reset line 30 in a row of pixel circuits 10H are relatively small. Furthermore, since the longitudinal reset lines 30 are disconnected from each other in the display area AA, the pixel circuits 10 correspondingly coupled to the adjacent longitudinal reset lines 30 in a row of pixel circuits 10H will not affect each other during resetting, so that the reset conditions of the pixel circuits 10 at different positions in the pixel circuit row 10H are relatively small, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H and improving the display unevenness problem. In addition, the reset conditions of the pixel circuits 10 connected to the same longitudinal reset line 30 in a row of pixel circuits 10H are relatively small, which can also reduce the occurrence of insufficient reset of the pixel circuits 10 and avoid dark-state light emission.

[0049] In some embodiments, Figure 3 FIG. 1 is a schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention. Figure 3As shown, the pixel circuit includes a driving transistor Tm, a data writing transistor T1, a threshold compensation transistor T2, a first reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, and a storage capacitor Cst. The gate of the driving transistor Tm is connected to the first node N1, the first electrode of the driving transistor Tm is connected to the second node N2, and the second electrode thereof is connected to the third node N3. The driving transistor Tm is connected in series between the first light-emitting control transistor T4 and the second light-emitting control transistor T5, and the gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 both receive a light-emitting control signal E, one electrode of the first light-emitting control transistor T4 receives a positive power supply signal Pvdd, and the other electrode is connected to the second node N2, one electrode of the second light-emitting control transistor T5 is connected to the third node N3, and the other electrode is connected to the first electrode of the light-emitting device P, and the second electrode of the light-emitting device P receives a negative power supply signal Pvee. Optionally, the first electrode of the light-emitting device P is an anode, and the second electrode is a cathode. The gate of the data writing transistor T1 and the gate of the threshold compensation transistor T2 receive the first scanning signal Sc1, one electrode of the data writing transistor T1 receives the data signal Vdata and the other electrode is connected to the second node N2, and the threshold compensation transistor T2 is connected in series between the first node N1 and the third node N3. The gate of the first reset transistor T3 receives the second scanning signal Sc2, one electrode of the first reset transistor T3 receives the reset signal Ref and the other electrode is connected to the first node N1.

[0050] In some embodiments, the display panel includes Figure 3 In the pixel circuit shown, the first reset transistor T3 is connected to the vertical reset line 30 , and the vertical reset line 30 provides a reset signal Ref to the pixel circuit 10 .

[0051] In other embodiments, Figure 4 A schematic diagram of another pixel circuit in a display panel provided by an embodiment of the present invention. Figure 3 In terms of the embodiments, Figure 4 The embodiment further includes a second reset transistor T6, the gate of the second reset transistor T6 receives the second scan signal Sc2, one electrode of the second reset transistor T6 receives the second reset signal Ref2, the other electrode is connected to the fourth node N4, and the light emitting device P is connected to the fourth node N4. One electrode of the first reset transistor T3 receives the first reset signal Ref1. In this embodiment, the first reset transistor T3 and the second reset transistor T6 both receive the reset signal.

[0052] Figure 3 and Figure 4 In the embodiments, the transistors are all p-type for illustration. Optionally, the transistors in the pixel circuit may also be n-type transistors.

[0053] In one embodiment, Figure 4In the circuit diagram, the first reset signal Ref1 and the second reset signal Ref2 are the same signal, and the first reset transistor T3 and the second reset transistor T6 are both connected to the vertical reset line 30. That is, the first electrode of the first reset transistor T3 is electrically connected to the gate of the driving transistor Tm, and the second electrode of the first reset transistor T3 is electrically connected to the vertical reset line 30; the first electrode of the second reset transistor T6 is electrically connected to the anode of the light emitting device P, and the second electrode of the second reset transistor T6 is electrically connected to the vertical reset line 30.

[0054] In another embodiment, Figure 4 In the circuit diagram, the voltage values ​​of the first reset signal Ref1 and the second reset signal Ref2 are different. The first reset transistor T3 is coupled to a longitudinal reset line 30, and the second reset transistor T6 is coupled to a row reset line extending along the first direction x, and the row reset line is coupled to all pixel circuits 10 in a row of pixel circuits 10H. In this embodiment, the longitudinal reset line 30 provides the first reset signal Ref1, and the row reset line provides the second reset signal Ref2.

[0055] In another embodiment, Figure 4 In the circuit diagram, the voltage values ​​of the first reset signal Ref1 and the second reset signal Ref2 are different. The second reset transistor T6 is coupled to a longitudinal reset line 30, and the first reset transistor T3 is coupled to a row reset line extending along the first direction x, and the row reset line is coupled to all pixel circuits 10 in a row of pixel circuits 10H. In this embodiment, the longitudinal reset line 30 provides the second reset signal Ref2, and the row reset line provides the first reset signal Ref1.

[0056] In another embodiment, the voltage values ​​of the first reset signal Ref1 and the second reset signal Ref2 are different. The display panel includes a first reset line and a second reset line, the first reset line provides the first reset signal Ref1, the second reset line provides the second reset signal Ref2, the first reset transistor T3 is coupled to the first reset line, and the second reset transistor T6 is coupled to the second reset line. The same pixel circuit 10 is electrically connected to two longitudinal reset lines 30, wherein the first reset line includes one of the two longitudinal reset lines 30, and the second reset line includes the other of the two longitudinal reset lines 30.

[0057] In some embodiments, Figure 2As shown, the longitudinal reset line 30 includes a first longitudinal reset line 31. The display panel includes a transverse reset line 40 extending along the first direction x, and one transverse reset line 40 is coupled to one first longitudinal reset line 31 correspondingly; wherein one transverse reset line 40 is coupled to at least two pixel circuits 10 in a row of pixel circuits 10H, and the number of pixel circuits 10 coupled to the same transverse reset line 40 in the same row of pixel circuits 10H is less than the total number of pixel circuits 10 in the pixel circuit row 10H. Figure 2 In the figure, a horizontal reset line 40 is coupled to three pixel circuits 10 for illustration. In the embodiment of the present invention, a horizontal reset line 40 coupled to the first vertical reset line 31 is provided, and the extension direction of the horizontal reset line 40 is the same as the extension direction of the scanning line 20. The provision of the horizontal reset line 40 enables the first vertical reset line 31 to be coupled to at least two pixel circuits 10 in a row of pixel circuits 10H, and the number of pixel circuits 10 belonging to the same row of pixel circuits 10H coupled to the first vertical reset line 31 is less than the total number of pixel circuits 10 in the pixel circuit row 10H. In the same period of driving a row of pixel circuits 10H, a part of the pixel circuits 10 in a row of pixel circuits 10H connected thereto are reset through a first vertical reset line 31. If the number of pixel circuits 10 reset by a first vertical reset line 31 is small, the voltage drop on the first vertical reset line 31 is significantly reduced, and the reset conditions of the pixel circuits 10 connected to the same first vertical reset line 31 in a row of pixel circuits 10H are less different. The pixel circuit row 10H is jointly driven by at least two longitudinal reset lines 30, so that the reset conditions of the pixel circuits 10 at different positions in the pixel circuit row 10H are less different, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and improving the display unevenness problem.

[0058] In addition, a horizontal reset line 40 is provided to be coupled to a first vertical reset line 31; and a horizontal reset line 40 is coupled to at least two pixel circuits 10 in a row of pixel circuits 10H, which can reduce the number of vertical reset lines 30, save wiring space in the first direction x, increase the number of pixel circuits 10 arranged in the first direction x, and increase the number of pixels set in a unit area accordingly. In some embodiments, when the number of pixels set in a unit area remains unchanged, the first vertical reset line 31 of the present invention is combined with the horizontal reset line 40 to reduce the number of vertical reset lines 30, thereby improving the light transmittance of the display panel to a certain extent.

[0059] It should be noted that in Figure 2The overlap of the horizontal reset line 40 and the pixel circuit 10 indicates that the horizontal reset line 40 is electrically connected to the pixel circuit 10, and the black solid dot at the intersection of the horizontal reset line 40 and the first vertical reset line 31 indicates that the horizontal reset line 40 is electrically connected to the first vertical reset line 31. In the following embodiments, unless otherwise specified, they can be understood by reference.

[0060] In some embodiments, Figure 5 Another partial schematic diagram of a display panel provided by an embodiment of the present invention is provided to clearly illustrate the arrangement of the longitudinal reset line 30 and the transverse reset line 40. Figure 5 The scanning line 20 is not shown. Figure 5 As shown, the first longitudinal reset line 31 includes a first sub-longitudinal reset line 31a; the transverse reset line 40 includes a first transverse reset line 41, the first transverse reset line 41 is coupled to the first sub-longitudinal reset line 31a, and the first transverse reset line 41 is disconnected from the longitudinal reset line 30 adjacent to the first sub-longitudinal reset line 31a in the display area AA. The first transverse reset line 41 is arranged so that the first sub-longitudinal reset line 31a is coupled to at least two pixel circuits 10 in a row of pixel circuits 10H, and the first sub-longitudinal reset line 31a and the longitudinal reset line 30 adjacent to it are not electrically connected in the display area AA. In the same period of driving a row of pixel circuits 10H, the first sub-longitudinal reset line 31a is used to reset part of the pixel circuits 10 in a row of pixel circuits 10H connected thereto, and the number of pixel circuits 10 reset by the first sub-longitudinal reset line 31a is small, so that the voltage drop on the first sub-longitudinal reset line 31a is significantly reduced, and the reset conditions of the pixel circuits 10 connected to the first sub-longitudinal reset line 31a in a row of pixel circuits 10H are relatively small. This is beneficial to reducing the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and can improve the display unevenness problem.

[0061] like Figure 5As shown, the first longitudinal reset line 31 also includes a second sub-longitudinal reset line 31b adjacent to the first sub-longitudinal reset line 31a. The transverse reset line 40 includes a second transverse reset line 42, and the second transverse reset line 42 is coupled to the second sub-longitudinal reset line 31b; wherein the first transverse reset line 41 and the second transverse reset line 42 are respectively coupled to different pixel circuits 10 in the same row of pixel circuits 10H, and the second transverse reset line 42 and the first transverse reset line 41 are disconnected in the display area AA. That is, the second transverse reset line 42 and the first transverse reset line 41 are not connected in the display area AA, so that the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b are not connected in the display area AA. In this embodiment, in the same period of driving a row of pixel circuits 10H, the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b respectively reset the pixel circuits 10 connected thereto, and the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b will not affect each other in the reset conditions of the pixel circuits 10. And the voltage drops on the first sub-vertical reset line 31a and the second sub-vertical reset line 31b are significantly reduced, so the reset conditions of the pixel circuits 10 connected to the first sub-vertical reset line 31a in a row of pixel circuits 10H are relatively different, and the reset conditions of the pixel circuits 10 connected to the second sub-vertical reset line 31b in a row of pixel circuits 10H are relatively different, so that the reset condition difference between the pixel circuits 10 connected to the first sub-vertical reset line 31a and the pixel circuits 10 connected to the second sub-vertical reset line 31b is also relatively small. The embodiment of the present invention can reduce the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and improve the display unevenness problem.

[0062] In other embodiments, Figure 6 Another partial schematic diagram of a display panel provided by an embodiment of the present invention is provided to clearly illustrate the arrangement of the longitudinal reset line 30 and the transverse reset line 40. Figure 6 The scanning line 20 is not shown. Figure 6As shown, the first longitudinal reset line 31 includes a first sub-longitudinal reset line 31a, and the first transverse reset line 41 is coupled to the first sub-longitudinal reset line 31a. The longitudinal reset line 30 includes a second longitudinal reset line 32, and one second longitudinal reset line 32 is coupled to a pixel circuit 10 in a row of pixel circuits 10H. The first sub-longitudinal reset line 31a is adjacent to the second longitudinal reset line 32, and the first transverse reset line 41 is disconnected from the second longitudinal reset line 32 in the display area AA. In the same period of driving a row of pixel circuits 10H, the first sub-vertical reset line 31a resets the pixel circuits 10 connected thereto, and the second vertical reset line 32 resets the pixel circuits 10 connected thereto. The first sub-vertical reset line 31a and the second vertical reset line 32 do not affect each other in resetting the pixel circuits 10. The voltage drops on the first sub-vertical reset line 31a and the second vertical reset line 32 are significantly reduced. Therefore, the reset conditions of the pixel circuits 10 connected to the first sub-vertical reset line 31a in a row of pixel circuits 10H are relatively different, and the reset conditions of the pixel circuits 10 connected to the first sub-vertical reset line 31a and the pixel circuits 10 connected to the second vertical reset line 32 are also relatively different. This embodiment can reduce the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and improve the display unevenness problem.

[0063] Figure 6 In the embodiment, the longitudinal reset line 30 includes a first longitudinal reset line 31 and a second longitudinal reset line 32. The embodiment of the present invention does not limit the arrangement of the first longitudinal reset line 31 and the second longitudinal reset line 32 in the first direction x.

[0064] In some embodiments, Figure 5 As shown, the pixel circuits 10 coupled to the first horizontal reset line 41 are arranged in sequence in the first direction x, and the pixel circuits 10 coupled to the second horizontal reset line 42 are arranged in sequence in the first direction x. The first horizontal reset line 41 is coupled to at least two pixel circuits 10 arranged in sequence in a row of pixel circuits 10H, and the second horizontal reset line 42 is coupled to at least two pixel circuits 10 arranged in sequence in a row of pixel circuits 10H. This embodiment can ensure that the length of the horizontal reset line 40 is the shortest when the number of pixel circuits 10 coupled to the horizontal reset line 40 is determined, which is conducive to reducing the impedance on the horizontal reset line 40, and can also reduce the voltage drop of the reset signal on the first vertical reset line 31 coupled to the horizontal reset line 40, thereby reducing the reset difference between the pixel circuits 10 coupled to a first vertical reset line 31 in the same row of pixel circuits 10H, and improving the display unevenness problem.

[0065] In another embodiment, Figure 7Another partial schematic diagram of a display panel provided by an embodiment of the present invention is provided to clearly illustrate the connection relationship between the horizontal reset line 40 and the pixel circuit 10. Figure 7 In the figure, the horizontal reset line 40 overlaps with the pixel circuit 10 and has a black solid dot to indicate that the horizontal reset line 40 is electrically connected to the pixel circuit 10. Figure 7 As shown, at least one pixel circuit 10 coupled to the first horizontal reset line 41 is located between two pixel circuits 10 coupled to the second horizontal reset line 42. That is to say, the pixel circuits 10 respectively connected to the adjacent first sub-vertical reset line 31a and the second sub-vertical reset line 31b in the same row of pixel circuits 10H are arranged alternately. With the design of the embodiment of the present invention, when driving a row of pixel circuits 10H, the reset conditions of the pixel circuits 10 coupled to the first horizontal reset line 41 are substantially the same, and the reset conditions of the pixel circuits 10 coupled to the second horizontal reset line 42 are substantially the same. The pixel circuits 10 respectively connected to the adjacent first sub-vertical reset line 31a and the second sub-vertical reset line 31b in the pixel circuit row 10H are arranged alternately, which can also reduce the reset difference between the plurality of pixel circuits 10 arranged in sequence and improve the display unevenness problem.

[0066] In some embodiments, Figure 5 As shown, the connection point of the first longitudinal reset line 31 and the transverse reset line 40 is the first connection point W1; Figure 5 The black solid dot at the intersection of the first longitudinal reset line 31 and the transverse reset line 40 shown in the figure is the first connection point W1. The first connection point W1 is the physical connection point between the first longitudinal reset line 31 and the transverse reset line 40. The first connection point W1 will also be marked in the following embodiments involving circuit layouts. In an embodiment of the present invention, the difference in the number of pixel circuits 10 coupled to the transverse reset line 40 and located on both sides of the first connection point W1 in the first direction x is less than or equal to the first preset number. When driving a row of pixel circuits 10H, the reset signal transmitted by the first longitudinal reset line 31 is transmitted to the transverse reset line 40 via the first connection point W1, and then the reset signal is transmitted from the first connection line W1 to the left and right ends of the transverse reset line 40 along the first direction x. The embodiment of the present invention limits the difference in the number of pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1, so that the difference in the number of pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 will not be too large. In this way, the reset conditions of the pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 are less different, which can reduce the reset difference between multiple pixel circuits 10 coupled to the same first vertical reset line 31 in a row of pixel circuits 10H, thereby improving display unevenness.

[0067] Figure 5It is illustrated in the figure that for the pixel circuits 10 coupled to the same horizontal reset line 40, the number of pixel circuits 10 located on the left side of the first connection point W1 in the first direction x is 1, and the number of pixel circuits 10 located on the right side of the first connection point W1 in the first direction x is 1, and the difference in the number of pixel circuits 10 located on both sides of the first connection point W1 is 0.

[0068] In some embodiments, the first preset number is 2. That is, the maximum difference in the number of pixel circuits 10 coupled to the horizontal reset line 40 and located on the left and right sides of the first connection point W1 is 2. If the difference in the number of pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 is set to be smaller, the reset conditions of the pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 are basically the same, which can reduce the reset difference between multiple pixel circuits 10 coupled to the same first vertical reset line 31 in a row of pixel circuits 10H, thereby improving display unevenness.

[0069] Figure 5 In the figure, it is shown that the first longitudinal reset line 31 overlaps with the pixel circuit 10, and the first point W1 overlaps with a pixel circuit 10. In the embodiment of the present invention, the first point W1 overlaps with the pixel circuit 10, which means that the first point W1 overlaps with the area area enclosed by the transistors in the pixel circuit 10. At this time, the pixel circuit 10 overlapping with the first point W1 does not participate in the calculation of the quantity difference.

[0070] In some other embodiments, the first connection point W1 does not overlap with the pixel circuit 10 , and the first connection point W1 is located between adjacent pixel circuits 10 .

[0071] In another embodiment, Figure 8 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Figure 8 As shown, the connection point between the first longitudinal reset line 31 and the transverse reset line 40 is the first connection point W1; the first connection point W1 is located between two pixel circuits 10 coupled to the same transverse reset line 40. The transverse reset line 40 is coupled to four pixel circuits 10, and the difference in the number of pixel circuits 10 coupled to the transverse reset line 40 and located on the left and right sides of the first connection point W1 is 0.

[0072] In another embodiment, Fig. 9 A partial schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig. 9 As shown, the connection point between the first longitudinal reset line 31 and the transverse reset line 40 is the first connection point W1 ; the first connection point W1 overlaps with the pixel circuit 10 . Fig. 9In the figure, the horizontal reset line 40 is coupled to four pixel circuits 10 in a row of pixel circuits 10H, the number of pixel circuits 10 located on the left side of the first connection point W1 in the first direction x is 2, and the number of pixel circuits 10 located on the right side of the first connection point W1 in the first direction x is 1, and the difference in the number of pixel circuits 10 located on both sides of the first connection point W1 is 1.

[0073] In some embodiments, Fig.10 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.10 FIG. 1 shows three pixel circuits 10 arranged in sequence in a pixel circuit row 10H. The connection relationship of each transistor in the pixel circuit 10 can be referred to the above Figure 4 For understanding, see the embodiments. Fig.10 As shown, the display panel includes a data line 21 and a power line 22 extending along the second direction y, the data line 21 is used to provide a data signal Vdata to the pixel circuit 10, and the power line 22 is used to provide a positive power signal Pvdd to the pixel circuit 10. The display panel also includes a light emitting control line 23 extending along the first direction x, and the light emitting control line 23 is used to provide a light emitting control signal E to the pixel circuit 10. The scan line 20 extending along the first direction x includes a first scan line and a second scan line. Fig.10 Schematically shows a first scan line 20a_p, a second scan line 20b_p and a second scan line 20b_p-1, where p is a positive integer. Fig.10 Schematically, the pixel circuit 10 is located in the p-th pixel circuit row 10H. The first scan line 20a_p is coupled to the data writing transistor T1 of the pixel circuit 10 in the p-th pixel circuit row 10H, the second scan line 20b_p is coupled to the second reset transistor T6 of the pixel circuit 10 in the p-th pixel circuit row 10H, and the first reset transistor T3 of the pixel circuit 10 in the p-th pixel circuit row 10H is coupled to the second scan line 20b_p-1. Figure 4 The difference between the circuits is that the first reset transistor T3 and the second reset transistor T6 belonging to the same pixel circuit 10 receive different scanning signals, wherein the first reset transistor T3 of the pixel circuit 10 of the p-th pixel circuit row 10H and the second reset transistor T6 of the pixel circuit 10 of the p-1-th pixel circuit row 10H are controlled by the same second scanning line 20b_p-1, and it can be understood that the second reset transistor T6 of the pixel circuit 10 of the p-th pixel circuit row 10H and the first reset transistor T3 of the pixel circuit 10 of the p+1-th pixel circuit row 10H are controlled by the same second scanning line 20b_p.

[0074] Fig.10 is a schematic diagram of a top view of a display panel, the display panel includes a substrate, and it can be understood that the top view direction is parallel to the direction perpendicular to the plane where the substrate is located. Fig.10 It can be seen that at least one first longitudinal reset line 31 and the data line 21 at least partially overlap in the direction perpendicular to the plane where the substrate is located. Such an arrangement allows the first longitudinal reset line 31 and the data line 21 to overlap to form a capacitor, which can increase the parasitic capacitance on the first longitudinal reset line 31. When the parasitic capacitance on the first longitudinal reset line 31 is large, when the gate of the driving transistor Tm is reset by the reset signal provided by the first longitudinal reset line 31 (that is, when the first node N1 in the pixel circuit is reset, the storage capacitor Cst in the pixel circuit is connected to the first node N1), it is equivalent to using the large capacitor on the first longitudinal reset line 31 to charge the small capacitor in the pixel circuit, so there is almost no current in the first longitudinal reset line 31, and there is almost no voltage drop on the first longitudinal reset line 31, which can make the reset conditions of the pixel circuit 10 coupled to the first longitudinal reset line 31 basically the same, and can improve the display unevenness. In this embodiment, the first longitudinal reset line 31 can fully reset the pixel circuit 10 coupled thereto, and there will be no problem of dark state not being dark due to insufficient reset.

[0075] in addition, Fig.10 Schematically shows a first connection point W1 where the first longitudinal reset line 31 and the transverse reset line 40 cross-connect. In this embodiment, the first connection point W1 is located between two adjacent pixel circuits 10, and the number of pixel circuits 10 coupled to the same transverse reset line 40 and located on both sides of the first connection point W1 in the first direction x is 1.

[0076] In another embodiment, Fig.11 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.11 The pixel circuit structure and signal lines can be referred to Fig.10 Understand. Fig.11 As shown, in a direction perpendicular to the plane where the substrate is located, at least one first longitudinal reset line 31 and the power line 22 at least partially overlap. This arrangement allows the first longitudinal reset line 31 and the power line 22 to overlap to form a capacitor, thereby increasing the parasitic capacitance on the first longitudinal reset line 31. When the parasitic capacitance on the first longitudinal reset line 31 is large, the gate of the driving transistor Tm is reset using the reset signal provided by the first longitudinal reset line 31, which is equivalent to using the large capacitance on the first longitudinal reset line 31 to charge the small capacitance in the pixel circuit. In this way, there is almost no current on the first longitudinal reset line 31, and there is almost no voltage drop on the first longitudinal reset line 31, which can make the reset conditions of the pixel circuit 10 coupled to the first longitudinal reset line 31 the same, can improve the display unevenness, and will not cause the problem of dark state not being dark due to incomplete reset.

[0077] in addition, Fig.11FIG. 3 illustrates a first connection point W1 where the first longitudinal reset line 31 and the transverse reset line 40 cross each other. The first longitudinal reset line 31 overlaps with the second pixel circuit 10 located among the three pixel circuits 10, and the first longitudinal reset line 31 overlaps with the power line 22 driving the second pixel circuit 10. Fig.11 In the embodiment, the difference in the number of pixel circuits 10 coupled to the same transverse reset line 40 and located on both sides of the first connection point W1 in the first direction x is zero.

[0078] In some embodiments, at least one horizontal reset line 40 is coupled to n pixel circuits 10, where n is an odd number greater than 1; the n pixel circuits 10 are arranged in a first direction x; that is, the n pixel circuits 10 coupled to the same horizontal reset line 40 are located in the same pixel circuit row 10H. In a direction perpendicular to the plane where the substrate is located, at least one first vertical reset line 31 and the (n+1) / 2 th pixel circuit 10 among the n pixel circuits 10 at least partially overlap. Fig.11 As shown, n=3, and the first longitudinal reset line 31 overlaps with the second pixel circuit 10 among the three pixel circuits 10 arranged in the first direction x.

[0079] In another embodiment, Fig.12 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.12 As shown, a horizontal reset line 40 is coupled to three pixel circuits 10 arranged in the first direction x, and a first vertical reset line 31 overlaps with the second pixel circuit 10 among the three pixel circuits 10 arranged in the first direction x. Fig.12 It is indicated that the routing direction of the first longitudinal reset line 31 is the second direction y, and the first longitudinal reset line 31 may be a folded line at a local position, so that the structure in the pixel circuit 10 that is made in the same layer as the first longitudinal reset line 31 can be avoided. For example, in some embodiments, the connection electrode of the pixel circuit connected to the anode of the light-emitting device is located in the same layer as the first longitudinal reset line 31, and the first longitudinal reset line 31 is set as a folded line at a local position, so that the first longitudinal reset line 31 can be prevented from being short-circuited with the connection electrode.

[0080] In the embodiment of the present invention, the horizontal reset line 40 is coupled to the odd number of pixel circuits 10 arranged in the first direction x, and the first vertical reset line 31 is arranged to overlap the pixel circuit 10 located at the middle position among the odd number of pixel circuits 10. When driving a row of pixel circuits 10H, the reset signal provided by the first vertical reset line 31 is transmitted to both sides of the first vertical reset line 31 in the first direction x through the horizontal reset line 40. When the first vertical reset line 31 is basically located in the middle position of the odd number of pixel circuits 10, the distance of the reset signal transmitted to the left and right sides of the first vertical reset line 31 is basically the same, so that the reset signals received by the pixel circuits 10 on both sides of the first vertical reset line 31 in the first direction x are basically the same, which also makes the reset conditions of the pixel circuits 10 on both sides of the first vertical reset line 31 in the first direction x basically the same, thereby further improving the display unevenness problem and improving the display uniformity.

[0081] Fig.11 and Fig.12 All are illustrated with n=3. In one embodiment, n=5, the first longitudinal reset line 31 is set to overlap the third pixel circuit 10 among the five pixel circuits 10 arranged in the first direction x. In one embodiment, n=7, the first longitudinal reset line 31 is set to overlap the seventh pixel circuit 10 among the seven pixel circuits 10 arranged in the first direction x.

[0082] In some embodiments, Fig.13 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.13 As shown, the display panel includes a first light emitting device P1, a second light emitting device P2 and a third light emitting device P3, each emitting light of different colors. Fig.13 Only the position of the anode of each light-emitting device is shown. The pixel circuit 10 in the pixel circuit row includes a first pixel circuit 10-1, a second pixel circuit 10-2 and a third pixel circuit 10-3; the first light-emitting device P1 is coupled to the first pixel circuit 10-1, the second light-emitting device P2 is coupled to the second pixel circuit 10-1, and the third light-emitting device P3 is coupled to the third pixel circuit 10-1. Fig.13It can be seen that the area of ​​the storage capacitor Cst in the first pixel circuit 10-1 is greater than the area of ​​the storage capacitor Cst in the second pixel circuit 10-2, and the area of ​​the storage capacitor Cst in the first pixel circuit 10-1 is greater than the area of ​​the storage capacitor Cst in the third pixel circuit 10-3. That is, the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is greater than the capacitance value of the storage capacitor Cst in the second pixel circuit 10-2, and the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is greater than the capacitance value of the storage capacitor Cst in the third pixel circuit 10-3. In the direction perpendicular to the plane where the substrate is located, at least one first longitudinal reset line 31 and the first pixel circuit 10-1 at least partially overlap. That is, the first pixel circuit 10-1 is closest to the first longitudinal reset line 31, and the distance for the first longitudinal reset line 31 to provide the reset signal transmission to the first pixel circuit 10-1 is the shortest.

[0083] When the gate of the driving transistor Tm in the pixel circuit 10 is reset by using the first longitudinal reset line 31, the gate of the driving transistor Tm is coupled to the storage capacitor Cst, and the larger the capacitance of the storage capacitor Cst in the pixel circuit 10, the larger the reset current generated when resetting the gate of the driving transistor Tm, and the larger the voltage drop on the corresponding first longitudinal reset line 31, thereby affecting the reset conditions of multiple pixel circuits 10 coupled to the first longitudinal reset line 31 in the same row of pixel circuits 10H. In the embodiment of the present invention, the first longitudinal reset line 31 is set to overlap with the first pixel circuit 10-1 with the largest capacitance value of the storage capacitor Cst, so that the reset signal transmission distance provided by the first longitudinal reset line 31 to the first pixel circuit 10-1 is the shortest. In the same period of driving a row of pixel circuits 10H, the first longitudinal reset line 31 can be used to quickly reset the first pixel circuit 10-1, reducing the influence of the reset current on the voltage drop on the first longitudinal reset line 31, so as to try to ensure that the reset conditions of the first longitudinal reset line 31 to each pixel circuit 10 connected thereto in the same period are basically the same, thereby improving display unevenness.

[0084] In some embodiments, the light emitting color of the first light emitting device P1 is red. The light emitting colors of the second light emitting device P2 and the third light emitting device P3 are respectively one of green and blue. That is to say, among the devices of three light emitting colors, the first pixel circuit 10-1 drives the first light emitting device P1, and the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is set to be larger, while the capacitance value of the storage capacitor Cst in the second pixel circuit 10-2 and the third pixel circuit 10-3 is smaller.

[0085] In one embodiment, the light color of the second light emitting device P2 is green, and the light color of the third light emitting device P3 is blue. The storage capacitor Cst in the second pixel circuit 10-2 is set to have a smaller capacitance value, so that the threshold compensation of the driving transistor Tm can be more fully performed when the pixel circuit operates in the threshold compensation stage, and the light brightness of the second light emitting device P2 driven by the second pixel circuit 10-2 is more accurate. Since the human eye is more sensitive to green light, the light brightness of the second light emitting device P2 is more accurate, which can improve the overall visual effect and help improve the problem of uneven display. In addition, when the pixel unit composed of three color light emitting devices emits white light, the light emitting current required by the third light emitting device P3 emitting blue light is greater than the light emitting current of the first light emitting device P1 and the second light emitting device P2. When the pixel unit emits white light, the data voltage value provided to the third pixel circuit 10-3 will be low, resulting in increased power consumption. In the embodiment of the present invention, the capacitance value of the storage capacitor Cst in the third pixel circuit 10-3 is reduced. When the third light-emitting device P3 is driven to emit light, the data voltage provided to the third pixel circuit 10-3 can be appropriately increased so that the data voltage is close to the data voltage provided to the first pixel circuit 10-1 and the second pixel circuit 10-2, thereby reducing display power consumption.

[0086] In one embodiment, Fig.14 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.14 As shown, the pixel circuit 10 includes a first pixel circuit 10-1, a second pixel circuit 10-2 and a third pixel circuit 10-3; the display panel includes a first light-emitting device, a second light-emitting device and a third light-emitting device having different light-emitting colors, wherein the first light-emitting device is coupled to the first pixel circuit 10-1, the second light-emitting device is coupled to the second pixel circuit 10-2, and the third light-emitting device is coupled to the third pixel circuit 10-3. Fig.14 The light-emitting device is not shown in the figure, and the embodiment of the present invention does not limit the arrangement of the light-emitting device. A plurality of first pixel circuits 10-1 are arranged into a first circuit column 10L1 in the second direction y, a plurality of second pixel circuits 10-2 are arranged into a second circuit column 10L2 in the second direction y, and a plurality of third pixel circuits 10-3 are arranged into a third circuit column 10L3 in the second direction y; in the first direction x, the first circuit column 10L1, the second circuit column 10L2, and the third circuit column 10L3 are arranged alternately. In this embodiment, the light-emitting devices driven by the plurality of pixel circuits 10 in a circuit column have the same light-emitting color.

[0087] Fig.14 The figure also shows the first longitudinal reset lines 31 extending along the second direction y and the transverse reset lines 40 of different colors extending along the first direction x. One transverse reset line 40 is coupled to one first longitudinal reset line 31 . Fig.14In the figure, only one horizontal reset line 40 is coupled to three pixel circuits 10 in one pixel circuit row for illustration.

[0088] In another embodiment, Fig.15 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.15 As shown, the pixel circuit 10 includes a first pixel circuit 10-1, a second pixel circuit 10-2 and a third pixel circuit 10-3; the display panel includes a first light-emitting device, a second light-emitting device and a third light-emitting device having different light-emitting colors, wherein the first light-emitting device is coupled to the first pixel circuit 10-1, the second light-emitting device is coupled to the second pixel circuit 10-2, and the third light-emitting device is coupled to the third pixel circuit 10-3. Fig.15 The light-emitting device is not shown in the figure, and the embodiment of the present invention does not limit the arrangement of the light-emitting device. The first pixel circuit 10-1 and the second pixel circuit 10-2 are alternately arranged in the second direction y to form a fourth circuit column 10L4, and a plurality of third pixel circuits 10-3 are arranged in the second direction y to form a fifth circuit column 10L5; in the first direction x, the fourth circuit column 10L4 and the fifth circuit column 10L5 are alternately arranged; wherein, in two adjacent fourth circuit columns 10L4, one of the two pixel circuits 10 belonging to the same pixel circuit row 10H is a first pixel circuit 10-1, and the other is a second pixel circuit 10-2. In this implementation, in the pixel circuit row 10H, the first pixel circuit 10-1 and the second pixel circuit 10-2 are alternately arranged in the first direction x, and there is a third pixel circuit 10-3 between the adjacent first pixel circuits 10-1 and the second pixel circuit 10-2.

[0089] Fig.15 The figure also shows the first longitudinal reset lines 31 extending along the second direction y and the transverse reset lines 40 of different colors extending along the first direction x. One transverse reset line 40 is coupled to one first longitudinal reset line 31 . Fig.15 In the figure, only one horizontal reset line 40 is coupled to two pixel circuits 10 in a pixel circuit row 10H for illustration.

[0090] In some embodiments, as described above Figure 5 or Figure 6As shown, at least two horizontal reset lines 40 are respectively coupled to different pixel circuits 10 in the same row of pixel circuit row 10H; in the same period of driving a row of pixel circuit row 10H, the pixel circuits 10 in the pixel circuit row 10H are reset by at least two horizontal reset lines 40. Among them, the difference in the number of pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same row of pixel circuit row 10H is less than or equal to the second preset number. In the same period of driving a row of pixel circuit row 10H, the reset conditions of the pixel circuits 10 connected to each horizontal reset line 40 are not much different, which can reduce the reset difference between the pixel circuits 10 connected to different horizontal reset lines 40 in a row of pixel circuit row 10H, improve the brightness uniformity of the light-emitting device driven by the pixel circuit row 10H, and improve the display unevenness.

[0091] In some embodiments, the second preset number is 3. That is, the maximum difference in the number of pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same pixel circuit row 10H is 3. Figure 5 As shown in FIG. 1 , the number of pixel circuits 10 coupled to each horizontal reset line 40 is 3, and the difference in the number of pixel circuits 10 coupled to two horizontal reset lines 40 corresponding to the same pixel circuit row 10H is 0. Figure 6 It is shown that among the horizontal reset lines 40 corresponding to the same row of pixel circuits 10H, there are horizontal reset lines 40 coupled to two pixel circuits 10, and there are also horizontal reset lines 40 coupled to three pixel circuits 10, and the difference in the number of pixel circuits 10 coupled to the two horizontal reset lines 40 is 1. The embodiment of the present invention limits the second preset number so that the difference in the number of pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same row of pixel circuits 10H is small. In the same period of driving a row of pixel circuits 10H, the reset conditions of the pixel circuits 10 connected to each horizontal reset line 40 are not much different, so that the reset conditions of the pixel circuits 10 connected to different horizontal reset lines 40 in a row of pixel circuits 10H are basically the same, thereby improving the brightness uniformity of the light-emitting devices driven by the pixel circuit row 10H and improving display unevenness.

[0092] In some embodiments, Figure 5 As shown, a row of pixel circuits 10H is driven by a plurality of horizontal reset lines 40, and the number of pixel circuits 10 coupled to each horizontal reset line 40 corresponding to the same row of pixel circuits 10H is equal. In the same period of driving a row of pixel circuits 10H, each horizontal reset line 40 resets the same number of pixel circuits 10, so that the reset conditions of the pixel circuits 10 connected to different horizontal reset lines 40 in a row of pixel circuits 10H are basically the same, thereby improving the brightness uniformity of the light-emitting devices driven by the pixel circuit row 10H and improving display unevenness.

[0093] In some embodiments, Figure 5 As shown, a first longitudinal reset line 31 is coupled to a plurality of transverse reset lines 40 arranged in the second direction y, and the same number of pixel circuits 10 are coupled to each transverse reset line 40 coupled to the same first longitudinal reset line 31. That is, a first longitudinal reset line 31 is coupled to the pixel circuits 10 in a plurality of pixel circuit rows 10H, and the number of pixel circuits 10 in each pixel circuit row 10H coupled to the first longitudinal reset line 31 is equal. When display is performed by row-by-row driving, the scanning line 20 provides scanning signals row by row to drive the plurality of pixel circuit rows 10H row by row, and after the first longitudinal reset line 31 completes the resetting of the pixel circuits coupled thereto in a row of pixel circuit rows 10H, it resets the pixel circuits coupled thereto in the next row of pixel circuit rows 10H after a certain period of time. During the time interval when the first longitudinal reset line 31 resets the pixel circuits in two pixel circuit rows 10H, the reset bus continuously provides a voltage signal to the first longitudinal reset line 31, which can compensate for the voltage drop on the first longitudinal reset line 31, so that the first longitudinal reset line 31 provides the same reset voltage to the pixel circuits 10 in each pixel circuit row 10H. The horizontal reset lines 40 coupled to the same first longitudinal reset line 31 are arranged to couple the same number of pixel circuits 10, so that the reset conditions of the pixel circuits 10 in different pixel circuit rows 10H coupled to the first longitudinal reset line 31 are also substantially the same, thereby further improving display unevenness and enhancing display uniformity.

[0094] In some embodiments, Fig.16 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.16As shown, a plurality of pixel circuits 10 are arranged into a pixel circuit row 10H in a first direction x, and a plurality of pixel circuits 10 are arranged into a circuit column 10L in a second direction y; the longitudinal reset line 30 includes a second longitudinal reset line 32, and one second longitudinal reset line 32 is coupled to one pixel circuit 10 in a row of pixel circuit rows 10H, and a plurality of pixel circuits 10 in a circuit column 10L are coupled to the same second longitudinal reset line 32. In the display panel provided by this embodiment, in the same period of driving a row of pixel circuit rows 10H, one second longitudinal reset line 32 only resets one pixel circuit 10, and the parasitic capacitance on the second longitudinal reset line 32 is sufficient to complete the reset of the pixel circuit 10, so there is almost no current and no voltage drop on the second longitudinal reset line 32, and the pixel circuit 10 can be fully reset, and there will be no problem of dark state not being dark due to incomplete reset. The pixel circuits 10 in a row of pixel circuit rows 10H that are respectively connected to different second longitudinal reset lines 32 can all be fully reset. When the pixel circuit row 10H is driven row by row, each pixel circuit 10 in the circuit column 10L coupled to the second longitudinal reset line 32 can also be fully reset. This embodiment can ensure that each pixel circuit 10 is fully reset, effectively improve display unevenness, and enhance display uniformity.

[0095] In some embodiments, a second longitudinal reset line 32 is coupled to a pixel circuit 10 in a pixel circuit row 10H, a plurality of pixel circuits 10 in a circuit column 10L are coupled to the same second longitudinal reset line 32, and the second longitudinal reset line 32 at least partially overlaps with a data line or a power line, thereby increasing the parasitic capacitance on the second longitudinal reset line 32. No further drawings are provided for illustration.

[0096] In some embodiments, the data line 21 and the power line 22 are both extended along the second direction y, and the longitudinal reset line 30 is located at a different layer from at least one of the data line 21 and the power line 22. Then, the longitudinal reset line 30 and the data line 21 (or the power line 22) located at a different layer may be arranged to at least partially overlap, so as to increase the parasitic capacitance on the longitudinal reset line 30, and the large capacitance on the longitudinal reset line 30 is used to reset the pixel circuit, so that there is almost no current on the longitudinal reset line 30, and there is almost no voltage drop on the longitudinal reset line 30, so that the reset conditions of the pixel circuits 10 coupled to the longitudinal reset line 30 are the same, so that each pixel circuit 10 can be fully reset, and the display unevenness can be improved, and there will be no problem of dark state luminescence caused by insufficient reset.

[0097] In one embodiment, the vertical reset line 30 and the data line 21 are located in different layers. Fig.17 for Fig.10 Schematic diagram of the cross section at the midline A-A'. Fig.17As shown, the display panel includes a semiconductor layer 020 , a first metal layer 030 , a second metal layer 040 , a third metal layer 050 and a fourth metal layer 060 which are located on one side of a substrate 010 and are sequentially away from the substrate 010 . Fig.17 The driving transistor Tm is shown in the figure, the active layer of the driving transistor Tm is located in the semiconductor layer 020, the scanning line 20 is located in the first metal layer 030, the first electrode of the storage capacitor Cst is located in the first metal layer 030, and the second electrode of the storage capacitor Cst is located in the second metal layer 040; the data line 21 and the power line 22 are located in the third metal layer 050; wherein the vertical reset line 30 is located in the fourth metal layer 060. In this embodiment, the vertical reset line 30 is located in a different layer from the data line 21 and the power line 22, and in the direction e perpendicular to the plane where the substrate 010 is located, the vertical reset line 30 and the data line 21 are at least partially overlapped. In this way, the parasitic capacitance on the vertical reset line 30 can be increased, and the large capacitance on the vertical reset line 30 is used to reset the pixel circuit, so there is almost no current on the vertical reset line 30, and there is almost no voltage drop on the vertical reset line 30, so that the reset conditions of the pixel circuit 10 coupled to the vertical reset line 30 can be the same.

[0098] In some embodiments, Fig.17 As shown, the longitudinal reset line 30 and the transverse reset line 40 are located in the same layer. The longitudinal reset line 30 and the transverse reset line 40 can be manufactured by the same process, and the two are directly connected. Fig.17 The circled area Q1 represents the connection point between the pixel circuit and the horizontal reset line 40. In addition, the vertical reset line 30 and the horizontal reset line 40 are arranged in the same layer. Then, the arrangement positions of the vertical reset line 30 and the horizontal reset line 40 are more flexible, and the vertical reset line 30 can be arranged to overlap with other signal lines to increase the parasitic capacitance on the vertical reset line 30. Fig.17 In the embodiment, the longitudinal reset line 30 and the data line 21 are overlapped. In another embodiment, as Fig.11 As shown, the longitudinal reset line 30 and the transverse reset line 40 are located in the same layer, and in the direction perpendicular to the plane of the substrate 010, the longitudinal reset line 30 overlaps with the power line 22. The setting of the transverse reset line 40 will not affect the original signal line of the display panel extending in the first direction x. Setting the longitudinal reset line 30 and the transverse reset line 40 in the same layer can reduce the impact on the wiring space in the display panel.

[0099] In some embodiments, the longitudinal reset line 30 and the transverse reset line 40 are located in different layers. Under the condition that the two are electrically connected through the vias on the insulating layer, at least one of the longitudinal reset line 30 and the transverse reset line 40 can be set to be located in the same layer as other conductive structures in the display panel. For example, if the transverse reset line 40 is set to be located in the same layer as other conductive structures in the display panel, the setting position of the longitudinal reset line 30 will also be relatively flexible at this time, and the longitudinal reset line 30 can be set to overlap with the data line 21 or the power line 22 as needed, or the longitudinal reset line 30 can be set between adjacent pixel circuits as needed. In addition, the longitudinal reset line 30 and the transverse reset line 40 are located in different layers. For example, part of the line segments of the original reset line extending along the first direction x in the prior art can be retained as the transverse reset line 40 in the present invention, and an additional longitudinal reset line 30 extending along the second direction y can be added. In this way, the design of the longitudinal reset line 30 in the embodiment of the present invention can be realized by making relatively small changes to the existing display panel wiring method.

[0100] In one embodiment, Fig.18 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.19 for Fig.18 Schematic diagram of the cross section at the midline B-B'. Fig.18 and Fig.19 From the above, it can be seen that the longitudinal reset line 30 and the transverse reset line 40 are located in different layers. Among them, the longitudinal reset line 30 is located in the fourth metal layer 060, and the transverse reset line 40 is located in the second metal layer 040. The longitudinal reset line 30 and the transverse reset line 40 are electrically connected through a via that penetrates the insulating layer. Among them, one plate of the storage capacitor Cst in the pixel circuit 10 is located in the second metal layer 040, and the transverse reset line 40 is set in the second metal layer 040, so that the second metal layer 040 can be utilized. The scan line 20 in the display panel is located in the first metal layer 030, and the extension direction of the transverse reset line 40 is the same as the extension direction of the scan line 20. Setting the transverse reset line 40 and the scan line 20 in different layers can help to improve the arrangement compactness of the wiring with the same extension direction and save the space occupied by the pixel circuit.

[0101] In another embodiment, the longitudinal reset line 30 and the transverse reset line 40 are located in different layers, wherein the longitudinal reset line 30 is located in the fourth metal layer 060, the transverse reset line 40 is located in the semiconductor layer 020, and the longitudinal reset line 30 and the transverse reset line 40 are electrically connected through a via penetrating the insulating layer.

[0102] In another embodiment, the longitudinal reset line 30 and the transverse reset line 40 are located in different layers, wherein the longitudinal reset line 30 and the data line 21 are located in the same layer, and the transverse reset line 40 is located in the semiconductor layer 020 or the second metal layer 040 .

[0103] In another embodiment, the longitudinal reset line 30 and the transverse reset line 40 are located in different layers, wherein the longitudinal reset line 30 and the data line and the power line are located in the same layer.

[0104] In some embodiments, along a direction perpendicular to the plane of the substrate 010 , at least one metal layer is spaced between the film layer where the transverse reset line 40 is located and the film layer where the longitudinal reset line 30 is located. Fig. 20 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.21 for Fig. 20 Schematic diagram of the cross section at the midline C-C'. Fig. 20 and Fig.21 From the perspective of the embodiment, the display panel further includes a metal pad 50, the horizontal reset line 40 is coupled to the metal pad 50 through a via hole penetrating the insulating layer, and the metal pad 50 is coupled to the vertical reset line 30 through a via hole penetrating the insulating layer; the metal pad 50 is located in a metal layer between the film layer where the horizontal reset line 40 is located and the film layer where the vertical reset line 30 is located. In this embodiment, it is shown that the horizontal reset line 40 is located in the second metal layer 040, the vertical reset line 30 is located in the fourth metal layer 060, and a third metal layer 050 is spaced between the film layer where the horizontal reset line 40 is located and the film layer where the vertical reset line 30 is located, wherein the metal pad 50 is located in the third metal layer 050. Since there is at least one metal layer between the film layer where the horizontal reset line 40 is located and the film layer where the vertical reset line 30 is located, the distance between the horizontal reset line 40 and the vertical reset line 30 is relatively large along the direction e perpendicular to the plane where the substrate 010 is located. If a hole is directly punched on the insulating layer to achieve the connection between the two, the punching depth will be deep and the hole area will be large, which will not only affect the electrical connection reliability between the horizontal reset line 40 and the vertical reset line 30, but also cause the punching to occupy a large wiring space. In the embodiment of the present invention, the metal pad 50 is provided to achieve the film layer where the horizontal reset line 40 is located and the vertical reset line 30, so the depth of the connection via between the metal pad 50 and the horizontal reset line 40 will not be too deep, the hole area of ​​the via will not be too large, and the depth of the connection via between the metal pad 50 and the vertical reset line 30 will not be too deep, and the hole area of ​​the via will not be too large, so that the electrical connection reliability between the horizontal reset line 40 and the vertical reset line 30 can be guaranteed, and the influence of the via on the wiring space can be reduced.

[0105] In one embodiment, Fig. 22 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig. 22 The pixel circuit 10 shown in the figure can be combined with the above Figure 4 The circuit diagram in the figure can be used to understand the circuit diagram. Fig. 22As shown, the display panel includes a first reset line 25 and a second reset line 26, and the voltage values ​​transmitted by the first reset line 25 and the second reset line 26 are different; the second electrode of the first reset transistor T3 is coupled to the first reset line 25, and the second electrode of the second reset transistor T6 is coupled to the second reset line 26; the first reset line 25 provides a first reset signal Ref1, and the second reset line 26 provides a second reset signal Ref2. The display panel includes two longitudinal reset lines 30, and the two longitudinal reset lines 30 are respectively a first type of longitudinal reset line 31-1 and a second type of longitudinal reset line 31-2. Among them, the first reset line 25 includes a first type of longitudinal reset line 31-1, and the second reset line 26 includes a second type of longitudinal reset line 31-2. That is, the first reset transistor T3 in the pixel circuit 10 is coupled to the first type of longitudinal reset line 31-1, and the second reset transistor T6 in the pixel circuit 10 is coupled to the second type of longitudinal reset line 31-2. This embodiment can use reset lines that transmit different voltage values ​​to reset the first reset transistor T3 and the second reset transistor T6 respectively, meeting the different requirements of the two reset transistors for the reset signal voltage value. Two types of longitudinal reset lines are provided, and the first reset transistor T3 and the second reset transistor T6 are coupled to their respective corresponding longitudinal reset lines. Both types of longitudinal reset lines are connected to part of the pixel circuits 10 in a row of pixel circuits 10H. In the same period of driving a row of pixel circuits 10H, the number of pixel circuits 10 reset by the two types of longitudinal reset lines is small, so that the reset difference between the pixel circuits 10 is small, and the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H can be reduced, thereby improving the display unevenness problem.

[0106] in addition, Fig. 22 It is also shown that the transverse reset line 40 includes a first type of transverse reset line 40-1 and a second type of transverse reset line 40-2, wherein the first type of transverse reset line 40-1 is coupled to the first type of longitudinal reset line 31-1, and the second type of transverse reset line 40-2 is coupled to the second type of longitudinal reset line 31-2.

[0107] In some embodiments, Fig.23 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.23As shown, the non-display area NA includes a reset bus 60; the reset bus 60 is located on one side of the display area AA in the second direction y; the longitudinal reset line 30 extends from the display area AA to the non-display area NA and then connects to the reset bus 60. In this embodiment, the reset bus 60 is set on one side of the display area AA, and the reset bus 60 is used to provide a reset signal to multiple longitudinal reset lines 30, and then the reset bus 60 leads out a wire to connect to the reset signal port (the reset signal port is used to connect to the display driver chip), so there is no need to set a reset signal port for each longitudinal reset line 30, which can reduce the number of reset signal ports set in the non-display area NA and save space in the non-display area NA. It can also reduce the number of output ports set on the display driver chip and reduce the size of the display driver chip.

[0108] Compared with the prior art method of setting a reset bus around the display area, the setting method of the longitudinal reset line 30 and the reset bus 60 in the embodiment of the present invention can also save space in the non-display area NA on both sides of the display area AA in the first direction x, which is conducive to narrowing the frame.

[0109] In the embodiment of the present invention, a longitudinal reset line 30 is coupled to only part of the pixel circuits 10 in a row of pixel circuit rows 10H. In the same period of driving a row of pixel circuit rows 10H, a longitudinal reset line 30 only resets the pixel circuits 10 connected thereto, rather than resetting all the pixel circuits 10 in a row of pixel circuit rows 10H. The voltage drop generated by a longitudinal reset line 30 resetting the pixel circuits 10 in the same period is small, so that the reset conditions of the pixel circuits 10 coupled to the same longitudinal reset line 30 in a row of pixel circuit rows 10H are basically the same. In addition, since the voltage drop generated by a longitudinal reset line 30 resetting the pixel circuits 10 in the same period is small, in the time interval of driving two rows of pixel circuit rows 10H row by row, the reset bus 60 can compensate the voltage on the longitudinal reset line 30 to a certain extent, so that the reset conditions of the pixel circuits 10 in the two adjacent rows of pixel circuit rows 10H driven by a longitudinal reset line 30 are also small, and the brightness difference of the light-emitting devices driven by the two rows of pixel circuit rows 10H is also small, thereby improving the display uniformity.

[0110] In some embodiments, Fig.24 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig.24As shown, the display area AA has a notch K, and the edge of the notch K is recessed toward the inside of the display area AA along the second direction y; the display area AA includes a first display area AA1 and a second display area AA2; in the second direction y, the first display area AA1 is located on one side of the notch K; in the first direction x, the second display area AA2 is located on both sides of the notch K. The longitudinal reset line 30 includes a third sub-longitudinal reset line 30c and a fourth sub-longitudinal reset line 30d; in the display area AA: along the second direction y, the length of the third sub-longitudinal reset line 30c is less than the length of the fourth sub-longitudinal reset line 30d, the third sub-longitudinal reset line 30c is located in the first display area AA1, and the fourth sub-longitudinal reset line 30d is located in the second display area AA2.

[0111] In a display panel having a notch K in the display area AA, if the reset line adopts a conventional design, and a reset line extending along a first direction x is arranged to be coupled to all pixel circuits in a row of pixel circuits, then due to the presence of the notch K, the length of the reset line in the display area on both sides of the notch K becomes shorter, and the length difference between the reset line at the long and short ends and the reset line in other display areas is large, resulting in a large voltage drop difference, which leads to a large difference in brightness between the display area on both sides of the notch K and the other display area, and there will be a serious display split screen problem.

[0112] According to the design of the embodiment of the present invention, a longitudinal reset line 30 extending in the second direction y is provided in the display panel, and a third sub-longitudinal reset line 30c located in the first display area AA1 and a fourth sub-longitudinal reset line 30d located in the second display area AA2 are provided according to the position of the display area. In the same period of driving a row of pixel circuits 10H, the third sub-longitudinal reset line 30c and the fourth sub-longitudinal reset line 30d only reset the pixel circuits 10 connected thereto, rather than resetting all the pixel circuits 10 in a row of pixel circuits 10H. Moreover, in the time interval of driving two rows of pixel circuits 10H row by row by the third sub-longitudinal reset line 30c and the fourth sub-longitudinal reset line 30d, the reset bus 60 can compensate the voltage on each longitudinal reset line 30 to a certain extent, so that the reset conditions of the pixel circuits 10 in the two adjacent rows of pixel circuits 10H driven by the third sub-longitudinal reset line 30c are also relatively small, and the reset conditions of the pixel circuits 10 in the two adjacent rows of pixel circuits 10H driven by the fourth sub-longitudinal reset line 30d are also relatively small. In this way, the brightness difference of the light-emitting devices driven by the pixel circuit rows 10H on both sides of the gap K in the first direction x is small, and the brightness difference of the light-emitting devices driven by two adjacent pixel circuit rows 10H in the second direction y is also small, thereby improving display uniformity.

[0113] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention, such as Fig.25As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention is any device with a display function, such as a mobile phone, a tablet computer, a laptop computer, a television, etc.

[0114] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, It is characterized in that The display panel comprises a scan line extending along a first direction and a longitudinal reset line extending along a second direction, wherein the first direction and the second direction intersect each other; the display panel comprises a display area, wherein adjacent longitudinal reset lines in the display area are disconnected from each other; The display panel comprises a substrate and a pixel circuit located on one side of the substrate, wherein a plurality of the pixel circuits are arranged into a pixel circuit row in the first direction; The longitudinal reset line includes a first longitudinal reset line; The display panel includes a first light emitting device, a second light emitting device, and a third light emitting device, which emit light of different colors; the pixel circuits in the pixel circuit row include a first pixel circuit, a second pixel circuit, and a third pixel circuit; the first light emitting device is coupled to the first pixel circuit, the second light emitting device is coupled to the second pixel circuit, and the third light emitting device is coupled to the third pixel circuit; The pixel circuit includes a storage capacitor, the capacitance value of the storage capacitor in the first pixel circuit is greater than the capacitance value of the storage capacitor in the second pixel circuit, and the capacitance value of the storage capacitor in the first pixel circuit is greater than the capacitance value of the storage capacitor in the third pixel circuit; In a direction perpendicular to the plane of the substrate, at least one of the first longitudinal reset lines and the first pixel circuit at least partially overlap.

2. The display panel according to claim 1, It is characterized in that The display panel includes a transverse reset line extending along the first direction, and one of the transverse reset lines is correspondingly coupled to one of the first longitudinal reset lines; wherein, One of the horizontal reset lines is coupled to at least two of the pixel circuits in a row of the pixel circuits, and the number of the pixel circuits in the same row of the pixel circuits coupled to the same horizontal reset line is less than the total number of the pixel circuits in the pixel circuit row.

3. The display panel according to claim 2, It is characterized in that The first longitudinal reset line includes a first sub-longitudinal reset line; The transverse reset line includes a first transverse reset line, the first transverse reset line is coupled to the first sub-vertical reset line, and the first transverse reset line is disconnected from the vertical reset line adjacent to the first sub-vertical reset line in the display area.

4. The display panel according to claim 3, It is characterized in that The first longitudinal reset line includes a second sub-longitudinal reset line adjacent to the first sub-longitudinal reset line; The horizontal reset line includes a second horizontal reset line, and the second horizontal reset line is coupled to the second sub-vertical reset line; wherein, The first horizontal reset line and the second horizontal reset line are respectively coupled to different pixel circuits in the same row of pixel circuits, and the second horizontal reset line and the first horizontal reset line are disconnected in the display area.

5. The display panel according to claim 4, It is characterized in that The pixel circuits coupled to the first horizontal reset line are arranged sequentially in the first direction, and the pixel circuits coupled to the second horizontal reset line are arranged sequentially in the first direction.

6. The display panel according to claim 4, It is characterized in that At least one of the pixel circuits coupled to the first horizontal reset line is located between two of the pixel circuits coupled to the second horizontal reset line.

7. The display panel according to claim 2, It is characterized in that The connection point between the first longitudinal reset line and the transverse reset line is a first connection point; A difference in the number of the pixel circuits coupled to the horizontal reset line and located on both sides of the first connection point in the first direction is less than or equal to a first preset number.

8. The display panel according to claim 7, It is characterized in that The first preset number is 2.

9. The display panel according to claim 2, It is characterized in that The display panel comprises data lines extending along the second direction, and in a direction perpendicular to the plane where the substrate is located, at least one of the first longitudinal reset lines and the data lines at least partially overlap; Alternatively, the display panel comprises a power line extending along the second direction, and in a direction perpendicular to the plane where the substrate is located, at least one of the first longitudinal reset lines at least partially overlaps with the power line.

10. The display panel according to claim 2, It is characterized in that At least one of the horizontal reset lines is coupled to n pixel circuits, where n is an odd number greater than 1; and the n pixel circuits are arranged in the first direction; In a direction perpendicular to the plane where the substrate is located, at least one of the first longitudinal reset lines and the (n+1) / 2th pixel circuit among the n pixel circuits at least partially overlap.

11. The display panel according to claim 1, It is characterized in that The first light emitting device emits red light.

12. The display panel according to claim 2, It is characterized in that The display panel includes a first light emitting device, a second light emitting device, and a third light emitting device, which emit light of different colors; the pixel circuits in the pixel circuit row include a first pixel circuit, a second pixel circuit, and a third pixel circuit; the first light emitting device is coupled to the first pixel circuit, the second light emitting device is coupled to the second pixel circuit, and the third light emitting device is coupled to the third pixel circuit; A plurality of the first pixel circuits are arranged in a first circuit column in the second direction, a plurality of the second pixel circuits are arranged in a second circuit column in the second direction, and a plurality of the third pixel circuits are arranged in a third circuit column in the second direction; In the first direction, the first circuit columns, the second circuit columns, and the third circuit columns are arranged alternately.

13. The display panel according to claim 2, It is characterized in that The display panel includes a first light emitting device, a second light emitting device, and a third light emitting device, which emit light of different colors; the pixel circuits in the pixel circuit row include a first pixel circuit, a second pixel circuit, and a third pixel circuit; the first light emitting device is coupled to the first pixel circuit, the second light emitting device is coupled to the second pixel circuit, and the third light emitting device is coupled to the third pixel circuit; The first pixel circuits and the second pixel circuits are alternately arranged in the second direction to form a fourth circuit column, and a plurality of the third pixel circuits are arranged in the second direction to form a fifth circuit column; in the first direction, the fourth circuit column and the fifth circuit column are alternately arranged; Among them, of the two pixel circuits belonging to the same pixel circuit row in two adjacent fourth circuit columns, one is the first pixel circuit and the other is the second pixel circuit.

14. The display panel according to claim 2, It is characterized in that At least two of the horizontal reset lines are respectively coupled to different pixel circuits in the same row of pixel circuits; wherein, The difference in number of the pixel circuits coupled to the two horizontal reset lines corresponding to the same row of the pixel circuits is less than or equal to a second preset number.

15. The display panel according to claim 14, It is characterized in that The second preset number is 3.

16. The display panel according to claim 14, It is characterized in that The number of pixel circuits coupled to each of the horizontal reset lines corresponding to the same row of pixel circuits is equal.

17. The display panel according to claim 2, It is characterized in that One of the first longitudinal reset lines is coupled to a plurality of the transverse reset lines arranged in the second direction, and each of the transverse reset lines coupled to the same first longitudinal reset line is coupled to the same number of pixel circuits.

18. The display panel according to claim 1, It is characterized in that The plurality of pixel circuits are arranged in a circuit row in the second direction; The longitudinal reset lines include second longitudinal reset lines, one of the second longitudinal reset lines is coupled to one of the pixel circuits in a row of the pixel circuits, and a plurality of the pixel circuits in one of the circuit columns are coupled to the same second longitudinal reset line.

19. The display panel according to claim 1, It is characterized in that The display panel includes a data line and a power line located on one side of the substrate; The longitudinal reset line is located at a different layer from at least one of the data line and the power line.

20. The display panel according to claim 2, It is characterized in that The longitudinal reset line and the transverse reset line are located in the same layer.

21. The display panel according to claim 2, It is characterized in that The longitudinal reset line and the transverse reset line are located in different layers.

22. The display panel according to claim 21, It is characterized in that The display panel comprises a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are located on one side of the substrate and are sequentially away from the substrate; the display panel comprises a data line, a scan line and a power line, and the pixel circuit comprises a transistor and a storage capacitor; the active layer of the transistor is located in the semiconductor layer, the scan line and the first electrode plate of the storage capacitor are located in the first metal layer, and the second electrode plate of the storage capacitor is located in the second metal layer; the data line and the power line are located in the third metal layer; wherein, The longitudinal reset line is located in the fourth metal layer, and the transverse reset line is located in the second metal layer.

23. The display panel according to claim 21, It is characterized in that Along a direction perpendicular to the plane where the substrate is located, at least one metal layer is spaced between the film layer where the horizontal reset line is located and the film layer where the vertical reset line is located. The display panel also includes a metal pad, the horizontal reset line is coupled to the metal pad through a via hole penetrating the insulating layer, and the metal pad is coupled to the vertical reset line through a via hole penetrating the insulating layer; the metal pad is located in a metal layer between the film layer where the horizontal reset line is located and the film layer where the vertical reset line is located.

24. The display panel according to claim 1, It is characterized in that The display panel includes a light emitting device, and the light emitting device is coupled to the pixel circuit; the pixel circuit includes a driving transistor, a first reset transistor and a second reset transistor, a first electrode of the first reset transistor is electrically connected to a gate of the driving transistor; a first electrode of the second reset transistor is electrically connected to an anode of the light emitting device; The vertical reset line is electrically connected to at least one of the second electrode of the first reset transistor and the second electrode of the second reset transistor.

25. The display panel according to claim 24, It is characterized in that The display panel includes a first reset line and a second reset line, the first reset line and the second reset line transmit different voltage values; the second electrode of the first reset transistor is coupled to the first reset line, and the second electrode of the second reset transistor is coupled to the second reset line; The same pixel circuit is electrically connected to two longitudinal reset lines, the first reset line includes one of the two longitudinal reset lines, and the second reset line includes the other of the two longitudinal reset lines.

26. The display panel according to claim 1, It is characterized in that The display panel also includes a non-display area, and the non-display area includes a reset bus; the reset bus is located on one side of the display area in the second direction; the longitudinal reset line extends from the display area to the non-display area and then connects to the reset bus.

27. The display panel according to claim 1, It is characterized in that The display area has a notch, and the edge of the notch is recessed toward the inside of the display area along the second direction; the display area includes a first display area and a second display area; In the second direction, the first display area is located on one side of the notch; in the first direction, the second display area is located on both sides of the notch; The longitudinal reset line includes a third sub-longitudinal reset line and a fourth sub-longitudinal reset line; In the display area: along the second direction, the length of the third sub-longitudinal reset line is less than the length of the fourth sub-longitudinal reset line, the third sub-longitudinal reset line is located in the first display area, and the fourth sub-longitudinal reset line is located in the second display area.

28. A display device, It is characterized in that A display panel comprising any one of claims 1 to 27.

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