Linear programming wafer-level chip architecture optimization method, system and storage medium based on fixed topological order

Abstract

The present invention relates to the field of electronic automation design technology, and in particular to a linear programming wafer-level chip architecture optimization method, system and storage medium based on a fixed topological order, which automatically generates a group of candidate core groups through input core information and wafer information, and performs preliminary screening on the candidate core groups; performs intra-group layout on the screened candidate core groups, and performs secondary screening on the core groups; each candidate core group after the secondary screening is copied and expanded, and flattened to the wafer layout area to complete the layout of the entire wafer; a linear programming method based on a fixed topological order is used for all candidate wafer-level architectures, and the architecture performance is used as the optimization target to perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance. The method of the present invention improves the optimization efficiency through a linear programming algorithm based on a fixed topological order.

Description

Technical Field

[0001] The present invention relates to the field of electronic automation design technology, and in particular to a linear programming wafer-level chip architecture optimization method, system and storage medium based on a fixed topological order. Background Art

[0002] With the development of artificial intelligence, cloud computing, intelligent computing networks and other fields, industry applications and scientific research work have higher and higher requirements for computing power. Wafer-level chips break through the limits of single-chip manufacturing processes by integrating prefabricated parts or core particles on wafers with high density and heterogeneity, thereby meeting the computing power requirements in multiple current scenarios. However, in the process of wafer-level chip architecture design, it is necessary to weigh the impact of architectural design parameters on various aspects of chip performance, such as manufacturing cost, performance, power consumption, etc. At present, a variety of automatic architecture exploration methods have been proposed for microarchitecture design, system-on-chip (SOC), and coarse-grained reconfigurable array (CGRA). For example, MAGNet, a framework for automatically optimizing design space proposed by NVIDIA, can map neural networks to CGRA. BOOM-Explorer is a framework for automatic exploration of RISCV microarchitecture design space. GIA is a reusable general-purpose interposer architecture for agile chiplet integration. This architecture uses an end-to-end design automation framework to automatically generate the optimal system design solution, including chiplet selection, inter-chip network configuration, chiplet layout, and mapping of specific workloads on GIA. Theseus is an efficient wafer-level chip design space exploration framework for large language models (LLMs).

[0003] The disadvantages of the prior art are:

[0004] (1) Architecture optimization methods based on DSE (Design space exploration) require manual design of design space parameters in the early stage, which lacks flexibility. For example, MAGNet, BOOM-Explorer and Theseus all require the definition of design space parameters in advance. The model can only be combined within the given parameters, and the performance of the generated architecture depends greatly on the quality of the early design space parameters. If the optimal system architecture is outside the range of design space parameter values, the optimal architecture cannot be found. In addition, DSE usually explores internal component parameters such as buffer width, storage capacity, number of registers, buffer entries, etc. under a certain architectural framework. Wafer-level architecture design usually does not have a fixed architectural framework.

[0005] (2) Currently, most existing technologies are used for the design of non-wafer-level chips. In view of the high-density integration characteristics of wafer-level chips and their huge potential design space, existing methods cannot be well transferred and applied. Among them, MAGNet is oriented to CGRA, BOOM-Explorer is oriented to micro-architecture, and GIA is oriented to Chiplet. Although Theseus is oriented to wafer-level chips, it is based on the DSE method for architecture exploration and is an LLM large model for application, which cannot be directly applied to other application fields.

[0006] (3) The architecture performance evaluation of existing technologies requires the support of simulators, and a trade-off needs to be made between accuracy and simulation efficiency, which takes a long time to optimize the architecture. Traditional DSE methods usually use cycle-accurate simulators to evaluate architecture performance, which is very time-consuming at the integration scale of wafer-level chips. BOOM-Explorer and Theseus can quickly evaluate the performance of the architecture by training the neural network model in advance. However, neural network training requires a large amount of high-quality data, and even small sample training requires thousands of data samples. The acquisition and processing of these samples requires a lot of time and manpower costs. In addition, the neural network method is usually regarded as a black box, and the internal mechanism cannot be clearly explained. Summary of the invention

[0007] The present invention aims to solve the problem of the lack of a more universal architecture exploration method for wafer-level chips; in view of the large exploration space for wafer-level chip optimization, the need for simulators to participate in performance simulation of the complete architecture, and the long optimization time, a linear programming wafer-level chip architecture optimization method, system and storage medium based on fixed topological order are proposed, which improves the optimization efficiency.

[0008] To achieve the above purpose, the technical solution adopted is:

[0009] A linear programming wafer-level chip architecture optimization method based on fixed topological order, comprising:

[0010] Automatically generate a group of candidate core groups based on the input core particle information and wafer information, and preliminarily screen the candidate core groups;

[0011] Conducting in-group layout of the screened candidate core groups and performing secondary screening of the core groups;

[0012] Each candidate core group after secondary screening is replicated and expanded, and laid out to the layout area of ​​the wafer to complete the layout of the entire wafer;

[0013] A fixed topological order linear programming method is used for all candidate wafer-level architectures. With the architecture performance as the optimization goal, task division and scheduling are performed, all candidate architectures are traversed, and one or more architectures with the best performance are selected.

[0014] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, a group of candidate core groups are automatically generated by inputting core information and wafer information, and the generation method is as follows: the core type is selected according to the wafer-level chip requirements, the possible number and combination of all core types are enumerated according to the core information and wafer information, and the same type of cores are allowed to be repeated.

[0015] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, the candidate core groups are preliminarily screened to filter out obviously unreasonable candidate core groups: ① there are no core particles for control in the core group; ② the number of core particles in the core group is too small, that is, the total area of ​​the core particles in the core group is less than 50% of the mask area; ③ the total area of ​​the core particles in the core group exceeds the mask area; ④ the core group is composed entirely of one type of core particles.

[0016] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, the candidate core groups after screening are laid out within the group, and before the secondary screening of the core groups, it also includes: generating core-to-core interconnections within the core group through defined rules, Rule 1: Each computing core is connected to a switching core; Rule 2: Each control core is connected to a storage core; Rule 3: The core groups are connected through the switching core using an on-chip network with a 2D Mesh topology.

[0017] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, the screened candidate core groups are laid out within the group, and secondary screening of the core groups includes: using a simulated annealing algorithm, with the mask width, height, and safe distance between core particles as constraints, and the area of ​​a single candidate core group and the length of the interconnection line between core particles as optimization targets to layout the core particles, and deleting the candidate core groups that cannot be laid out in the mask area.

[0018] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, all candidate wafer-level architectures are task-divided and scheduled using the linear programming method based on fixed topological order, and the constraints are defined as follows:

[0019] (1) A task can only be assigned to one chip for execution;

[0020] (2) The operator's end execution time is greater than or equal to the sum of the start execution time and the operator's execution time on the core particle;

[0021] (3) There is a set of tasks with execution dependencies. Task b depends on the execution of task a. Then the start execution time of task b is later than the sum of the end execution time of task a and the communication time between the two.

[0022] (4) The task execution end time cannot be greater than the total running time T;

[0023] (5) When multiple tasks without execution dependencies occupy the same core, the occupied time cannot overlap.

[0024] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, all candidate wafer-level architectures are task-divided and scheduled using the linear programming method based on fixed topological order, and the objective function is defined as , where T is the total running time.

[0025] According to the linear programming wafer-level chip architecture optimization method based on fixed topological order of the present invention, further, a linear programming solution is performed based on the fixed topological order linear programming method, and a linear programming solver is used to solve based on constraint definitions and objective functions to obtain the optimal chip architecture.

[0026] Furthermore, the present invention also provides a linear programming wafer-level chip architecture optimization system based on a fixed topological order, comprising a primary screening module, a secondary screening module, a candidate wafer architecture generation module and an architecture optimization module, wherein:

[0027] The initial screening module is used to automatically generate a group of candidate core groups based on the input core information and wafer information, and to perform initial screening on the candidate core groups;

[0028] A secondary screening module is used to arrange the candidate core groups after screening and perform secondary screening of the core groups;

[0029] The candidate wafer architecture generation module is used to replicate and expand each candidate core group after the secondary screening, and lay it out in the wafer layout area to complete the whole wafer layout;

[0030] The architecture optimization module is used to use a fixed topological order linear programming method for all candidate wafer-level architectures, with architecture performance as the optimization goal, to perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance.

[0031] Furthermore, the present invention also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0032] The beneficial effects achieved by adopting the above technical solution are:

[0033] The present invention aims to propose a linear programming wafer-level chip architecture optimization method based on a fixed topological order, which divides the wafer-level chip into multiple core groups (tiles), each core group consisting of multiple types of core particles. The architecture optimization object is a single core group. After determining the composition of the core group, the core group is copied to the entire wafer to form an architecture design scheme for the entire wafer. This method greatly simplifies the design space of the wafer-level chip. The linear programming algorithm is used for architecture exploration, and the optimization problem is abstracted into a mathematical model for solution, and the computing task is represented by a fixed topological sequence, thereby reducing the optimization solution space and improving the solution efficiency. Furthermore, the candidate core groups are quickly filtered out by simple operations of the initial screening, and the remaining candidate core groups are further filtered through secondary screening. In this way, the number of candidate core groups is greatly reduced for the relatively slow secondary screening, and the optimization efficiency is further improved. The present invention can also be applied to a variety of fields and flexibly generate a system architecture in a specific field.

[0034] In summary, the present invention can automatically and quickly explore the optimal wafer-level chip architecture, provide design solutions for engineers, reduce chip design time, and reduce labor costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings of the embodiments of the present invention, wherein the drawings are only used to illustrate some embodiments of the present invention, but not to limit all embodiments of the present invention thereto.

[0036] Figure 1 It is a flow chart of a linear programming wafer-level chip architecture optimization method based on fixed topological order according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings of specific embodiments of the present invention to clearly and completely describe the exemplary scheme of the embodiment of the present invention. Unless otherwise defined, the technical terms or scientific terms used in the present invention should be the common meanings understood by people with ordinary skills in the field.

[0038] like Figure 1 As shown, this embodiment discloses a linear programming wafer-level chip architecture optimization method based on a fixed topological order, which can automatically and quickly find a better wafer-level chip architecture under given constraints and optimization goals according to the computational task graph. Specifically, it includes the following contents:

[0039] Input data:

[0040] (1) Chip information: including chip model, type, and physical size information.

[0041] (2) Wafer information: including wafer size, length and width of the inscribed square that can be laid out, and safety distance (minimum chip spacing in the X and Y directions during chip layout).

[0042] (3) Bandwidth information: the bandwidth between core particles that can be interconnected.

[0043] (4) Task graph: The task graph abstracted from the computing application uses functions as the minimum partitioning granularity to divide the complete application into a set of subtasks. The task graph is represented by a directed acyclic graph, where nodes V represent computing tasks, edges E represent dependencies between tasks, and the weight of the edge is the amount of communication Q.

[0044] (5) Operator information: The execution time of each task in the task graph on all computing cores. This time can be obtained through the simulator.

[0045] The above input data, chip information, wafer information, and bandwidth information are provided by the system (preset). The task graph is provided by the user, and the operator information is obtained through the simulation module of the system after the task graph is input. Some commonly used operator information can also be preset in the system.

[0046] Step S101 : automatically generating a group of candidate cores by inputting core information and wafer information.

[0047] Select the core type according to the user's specified wafer-level chip requirements, such as the architecture requires two types of cores, CPU and GPU. Enumerate the possible number and combination of all core types based on the core information and wafer information, and allow the same type of cores to be repeated. Match one exchange core for each core group, and one storage core for each control core. Stop generating until the total area of ​​the cores in the core group exceeds the mask area.

[0048] Step S102, preliminarily screen the candidate core groups, and delete the obviously unreasonable core groups from the candidate core groups. For example: ① There are no cores for control such as CPU in the core group. ② The number of cores in the core group is too small, that is, the total area of ​​the cores in the core group is less than 50% of the mask area, resulting in a waste of wafer area and low utilization. ③ The total area of ​​the cores in the core group exceeds the area of ​​the reticle or mask. ④ The core group is composed entirely of one type of cores, which does not meet the characteristics of heterogeneous heterogeneous integration of systems on wafer.

[0049] Step S103: Generate interconnections between core particles within the core group according to defined rules. Rule 1: Each computing core particle is connected to a switching core particle; Rule 2: Each control core particle such as a CPU is connected to a storage core particle; Rule 3: Core groups are connected through a switching core particle (swtich) using a 2D Mesh topology on-chip network.

[0050] Step S104 : perform intra-group layout on the screened candidate core groups, perform secondary screening of the core groups, and further filter out core groups whose layouts do not meet the constraints.

[0051] Using simulated annealing algorithm, with mask width width, height hight, and safe distance between core particles as constraints, the area of ​​a single candidate core group and the length of interconnection lines between core particles are optimized for core particle layout, and candidate core groups that cannot be arranged in the mask area are deleted.

[0052] Step S105: Duplicate and expand each candidate core group after the second screening, and lay it out in the wafer layout area to complete the whole wafer layout. Finally, output the architecture information of the wafer-level chip for task division and scheduling in the next step.

[0053] Step S106: For all candidate wafer-level architectures, a linear programming method based on a fixed topology order is used to optimize the performance of the architecture, perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance. The above architecture performance is the total system running time, and the performance of the same task on different architectures is compared, and the architecture with the best performance is selected as the final output.

[0054] The implementation process of task allocation based on fixed topological order linear programming method is as follows:

[0055] (1) Variable definition

[0056] Task collection: ;

[0057] Candidate core group set: ;

[0058] Candidate wafer architecture chiplet set: ;

[0059] The set of operator edges: ,in ;

[0060] A collection of task pairs without execution dependencies: ,in ;

[0061] Task allocation variable: X[i][j][k] is a binary variable. A value of 1 indicates that task i is allocated to core k of core group j. A value of 0 indicates that task i is not allocated to core k of core group j.

[0062] Operator Start execution time ;

[0063] Operator End execution time ;

[0064] Operator Execution time on core particle k: ;

[0065] The communication delay between a group of operators that need to communicate: ;

[0066] Maximum system operation time: ;

[0067] System running time: T.

[0068] (2) Constraint definition

[0069] ① A task can only be assigned to one core particle for execution, i, j, k are the total number of tasks, the number of core groups and the number of core particles in the core group respectively.

[0070]

[0071] ② The end execution time of the operator is greater than or equal to the sum of the start execution time and the execution time of the operator on the core particle. is the execution time of task i on corek.

[0072]

[0073] ③ There is a set of tasks with execution dependencies. Task b depends on task a for execution. Then the start execution time of task b is later than the sum of the end execution time of task a and the communication time between the two.

[0074]

[0075] in, is the communication time from task a to b, and the bandwidth from the core particle where task a is located to the exchange core particle is , the bandwidth from the core particle where task b is located to the exchange core particle is , the bandwidth between the switching core particles is , the communication volume from a to b is , the number of hops from a to b is hop, where is a constant representing the transmission delay (related to the wiring material), then:

[0076]

[0077]

[0078] The number of hops is calculated from the number of rows and columns M and N of the core group obtained by layout according to the following formula, where Indicates the remainder, and The numbers of the core particles where tasks a and b are located:

[0079]

[0080] ④The task completion time cannot be greater than the total running time T.

[0081]

[0082] ⑤ When multiple tasks without execution dependencies occupy the same core particle, the occupied time cannot overlap.

[0083]

[0084]

[0085] The method for finding the set of task pairs without execution dependencies ND is as follows: let the set of all pairs of tasks with dependencies in the application task graph be P, and let the set of task combinations in pairs in a fixed topology sequence be Q.

[0086]

[0087] (3) Objective function definition

[0088]

[0089] (4) Linear programming solution

[0090] Use IBM cplex linear programming solver to solve linear programming problems based on constraint definitions and objective functions. Use cplex parallel solving function to accelerate architecture optimization and ultimately obtain the optimal chip architecture.

[0091] Corresponding to the above method, this embodiment also proposes a linear programming wafer-level chip architecture optimization system based on a fixed topological order, comprising a primary screening module, a secondary screening module, a candidate wafer architecture generation module and an architecture optimization module, wherein:

[0092] The initial screening module is used to automatically generate a group of candidate core groups based on the input core particle information and wafer information, and to perform initial screening on the candidate core groups.

[0093] The secondary screening module is used to arrange the candidate core groups after screening within the group and perform secondary screening of the core groups.

[0094] The candidate wafer architecture generation module is used to copy and expand each candidate core group after the secondary screening, and spread it to the wafer layout area to complete the entire wafer layout.

[0095] The architecture optimization module is used to use a fixed topological order linear programming method for all candidate wafer-level architectures, with architecture performance as the optimization goal, to perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance.

[0096] This embodiment also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0097] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0098] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0099] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0100] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0101] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A linear programming wafer-level chip architecture optimization method based on fixed topological order, characterized in that: Include: Automatically generate a group of candidate core groups based on the input core particle information and wafer information, and preliminarily screen the candidate core groups; Conducting in-group layout of the screened candidate core groups and performing secondary screening of the core groups; Each candidate core group after secondary screening is replicated and expanded, and laid out to the layout area of ​​the wafer to complete the layout of the entire wafer; For all candidate wafer-level architectures, a linear programming method based on a fixed topological order is used to optimize the performance of the architecture, perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance; Among them, all candidate wafer-level architectures are task-divided and scheduled using a fixed topological order linear programming method, and the constraints are defined as follows: (1) A task can only be assigned to one chip for execution; (2) The operator's end execution time is greater than or equal to the sum of the start execution time and the operator's execution time on the core particle; (3) There is a set of tasks with execution dependencies. Task b depends on the execution of task a. Then the start execution time of task b is later than the sum of the end execution time of task a and the communication time between the two. (4) The task execution end time cannot be greater than the total running time T; (5) When multiple tasks without execution dependencies occupy the same core particle, the occupied time cannot overlap.

2. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 1, characterized in that: A group of candidate core groups is automatically generated by inputting core information and wafer information. The generation method is as follows: select the core type according to the wafer-level chip requirements, enumerate the possible quantity and combination of all core types according to the core information and wafer information, and allow the same type of cores to be repeated.

3. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 1, characterized in that: The candidate core groups were preliminarily screened and obviously unreasonable candidate core groups were filtered out: ① there were no core particles for control in the core group; ② the number of core particles in the core group was too small; ③ the total area of ​​core particles in the core group exceeded the mask area, or the total area of ​​core particles in the core group was less than 50% of the mask area; ④ the core group was composed entirely of core particles of one type.

4. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 1, characterized in that: The screened candidate core groups are laid out within the group. Before the secondary screening of the core groups, the following steps are included: the core group generates interconnections between core particles according to defined rules. Rule 1: Each computing core particle is connected to a switching core particle; Rule 2: Each control core particle is connected to a storage core particle; Rule 3: The core groups are connected to each other through switching core particles using an on-chip network with a 2D Mesh topology.

5. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 4 is characterized in that: The screened candidate core groups are laid out within the group, and secondary screening of the core groups includes: using a simulated annealing algorithm, with the mask width, height, and safe distance between core particles as constraints, and the area of ​​a single candidate core group and the length of interconnection lines between core particles as optimization targets for core particle layout, and deleting candidate core groups that cannot be laid out in the mask area.

6. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 1, characterized in that: For all candidate wafer-level architectures, a fixed topology-order linear programming method is used to perform task partitioning and scheduling. The objective function is defined as min( T ), where T is the total running time.

7. The method for optimizing wafer-level chip architecture based on linear programming with fixed topological order according to claim 6, characterized in that: The linear programming solution is solved based on the fixed topological order linear programming method. The linear programming solver is used to solve the problem based on the constraint definition and the objective function to obtain the optimal chip architecture.

8. A linear programming wafer-level chip architecture optimization system based on fixed topological order, characterized in that: The method for optimizing a wafer-level chip architecture based on linear programming and fixed topological order according to any one of claims 1 to 7 comprises a primary screening module, a secondary screening module, a candidate wafer architecture generation module and an architecture optimization module, wherein: The initial screening module is used to automatically generate a group of candidate core groups based on the input core information and wafer information, and to perform initial screening on the candidate core groups; A secondary screening module is used to arrange the candidate core groups after screening and perform secondary screening of the core groups; The candidate wafer architecture generation module is used to replicate and expand each candidate core group after the secondary screening, and lay it out in the wafer layout area to complete the whole wafer layout; The architecture optimization module is used to use a fixed topological order linear programming method for all candidate wafer-level architectures, with architecture performance as the optimization goal, to perform task division and scheduling, traverse all candidate architectures, and select one or more architectures with the best performance.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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