Gigabit Ethernet PHY chip PTP test method based on Zynq

Abstract

The present invention discloses a Gigabit Ethernet PHY chip PTP test method based on ZYNQ, comprising the steps of: S1, hardware configuration: setting a master-slave system, integrating a clock source and simulating network conditions; S2, setting a software driver; S3, obtaining test results of multiple test cases; S4, performing multi-angle performance analysis. The present invention uses the PHY chip and the ZYNQ chip of the master-slave system for synchronous testing, and can display accurate test results on an oscilloscope, effectively improving the test accuracy; it also optimizes the processing system and programmable logic structure of the ZYNQ chip, transmits with a variety of dedicated high-efficiency interfaces, and controls multiple test cases with a MAC controller under the control of the software driver, effectively achieving accurate clock alignment and time synchronization; in addition, it also performs multi-angle performance analysis on the final test results to further improve the reliability of the test.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a ZYNQ-based Gigabit Ethernet PHY chip PTP testing method. Background Art

[0002] Gigabit Ethernet technology has become the mainstream standard in the field of modern communications, and most network devices use Gigabit Ethernet PHY chips for communication. In network communications, clock synchronization is crucial. PTP stands for Precision Time Protocol, which is a high-precision network time synchronization protocol. When using Gigabit Ethernet PHY chips, ensuring that it works properly and achieves accurate clock synchronization is crucial to network stability and performance. Among them, PHY stands for Physical Layer, and Gigabit Ethernet PHY chip is a physical layer chip used for Gigabit Ethernet communication.

[0003] Many industrial, test, measurement and communication applications require high-precision clock signals to synchronize control signals and capture data. At present, in some standard Ethernet networks, the time information of the master clock can be propagated to multiple nodes in the system by applying the precision time protocol PTP, and the precision time protocol PTP also provides test methods for these nodes to verify the effect of time synchronization. One method is to rely solely on software for control, and the other method is to mix software and FPGA or software and ASIC for transmission. Although when using these methods, the node can generate a clock output signal based on the master clock, the signal accuracy is not enough to meet the system's requirements for extremely low clock jitter. In addition, the system's clock phase alignment and time synchronization are also difficult to meet strict requirements.

[0004] In other words, the measures currently taken include at least the following three problems:

[0005] 1) The signal accuracy is insufficient and it is difficult to meet the system's requirements for extremely low clock jitter;

[0006] 2) It is difficult to achieve phase alignment and time synchronization of clocks;

[0007] 3) The accuracy and reliability of the test are insufficient. Summary of the invention

[0008] In view of the above three problems, the purpose of the present invention is to propose a Gigabit Ethernet PHY chip PTP test method based on ZYNQ. Clock synchronization test is performed on the PHY chip and ZYNQ chip of the master-slave system, and accurate test results can be displayed on the oscilloscope, which is also convenient for analysis and effectively improves the accuracy of the test; at the same time, the processing system and programmable logic structure of the ZYNQ chip are optimized, corresponding transmission is performed with a variety of dedicated high-efficiency interfaces, and multiple test cases are controlled by the MAC controller under the control of the software driver, which can effectively achieve accurate clock alignment and time synchronization; in addition, multi-angle performance analysis is performed on the final test results to further improve the reliability of the test.

[0009] This is achieved through the following technical solutions:

[0010] A Gigabit Ethernet PHY chip PTP test method based on ZYNQ, the method comprising the following steps: S1, hardware configuration: setting a master system and a slave system, the master system comprising an interconnected master ZYNQ chip and a master PHY chip, the slave system comprising an interconnected slave ZYNQ chip and a slave PHY chip, the master PHY chip being connected to the slave PHY chip via a cable and an oscilloscope respectively; constructing the same test environment inside the master ZYNQ chip and inside the slave ZYNQ chip respectively, for integrating the same clock source and simulating the same network condition; S2, setting software driver: setting a first software driver for the master ZYNQ chip in step S1 and a second software driver for the slave ZYNQ chip in step S1 respectively, using the first software driver to control the first PTP of the master PHY chip, and simultaneously synchronizing the time of the master PHY chip with the master ZYNQ chip; using the second software driver to control the second PTP of the slave PHY chip, and simultaneously synchronizing the time of the slave PHY chip with the slave ZYNQ chip; S3, conducting a test: completing step After S2, set multiple test cases and store the multiple test cases in the first software driver and the second software driver at the same time; test each test case in turn, use an oscilloscope to obtain each first second pulse signal and each first PTP synchronous output clock corresponding to the main ZYNQ chip under each test case, and use an oscilloscope to obtain each second second pulse signal and each second PTP synchronous output clock corresponding to each slave ZYNQ chip under each test case; use each first second pulse signal, each first PTP synchronous output clock, each second second pulse signal and each second PTP synchronous output clock as the final test result; S4, monitoring and analysis: perform multi-angle performance analysis of delay, jitter and synchronization accuracy on the final test result in step S3 to determine whether it meets the performance requirements of the test. If so, end the test; if not, return to step S1 to build the same test environment inside the main ZYNQ chip and the slave ZYNQ chip respectively, and loop until the performance requirements of the test are met, then end the test.

[0011] By using the master PHY chip and master ZYNQ chip of the master system and the slave PHY chip and slave ZYNQ chip of the slave system to perform clock synchronization tests under multiple test cases, accurate test results can be displayed on the oscilloscope, which is convenient for analysis and effectively improves the accuracy of the test. At the same time, by optimizing the structure of each processing system and each programmable logic of each ZYNQ chip, and using each corresponding MAC controller to control multiple test cases under the control of each software driver, accurate clock alignment and time synchronization can be effectively achieved. In addition, multi-angle performance analysis is performed on the final test results to further improve the reliability of the test.

[0012] Preferably, in step S1, the main ZYNQ chip includes a first programmable logic and a first processing system, the first processing system is provided with a first MAC controller, the first MAC controller is used to connect the main PHY chip and the first software driver, and is also used to control whether each test case in the first software driver is tested; the first programmable logic is provided with a first hardware trigger module and a first IP core, the first IP core is respectively connected to the first processing system and the first hardware trigger module, the first hardware trigger module is used to control the first IP core to transmit the corresponding first second pulse signal to the oscilloscope when the first software driver performs any test case test; the structure of the slave ZYNQ chip is the same as that of the main ZYNQ chip.

[0013] Preferably, the first IP core is an IEEE 1588 IP core, the first IP core includes an interconnected first register unit and a first real-time clock unit, the first register unit and the first real-time clock unit are both controlled by a first hardware trigger module, the first register unit is connected to a first processing system, and the first real-time clock unit is connected to an oscilloscope. The IEEE 1588 IP core is a high-precision IP core that can ensure the accuracy of the test.

[0014] Preferably, the main ZYNQ chip further includes a first application processor module, a first timestamp unit, a first RGMII interface, a first MIO multi-function interface, a first central connection unit and a first status and control register; the first MAC controller is respectively connected to the first timestamp unit, the first central connection unit and the first status and control register, the first MAC controller is connected to the first software driver through the first MIO multi-function interface and is connected to the main PHY chip through the first RGMII interface, the first central connection unit is respectively connected to the first MAC controller, the first MIO multi-function interface, the first IP core and the first application processor module, and the first application processor module is used to perform tests of multiple test cases. The first timestamp unit, the first status and control register, the first central connection unit and the first application processor module can allow the main ZYNQ chip to efficiently and accurately test each test case.

[0015] Preferably, when the first software driver is used to control the first PTP of the master PHY chip in step S2, the first software driver is first connected to the first processing system through the first UART interface and the first JTAG interface, and then connected to the master PHY chip through the first processing system; when the second software driver is used to control the second PTP of the slave PHY chip in step S2, the second software driver is first connected to the second processing system through the second UART interface and the second JTAG interface, and then connected to the slave PHY chip through the second processing system. The JTAG interface facilitates program debugging, the UART interface facilitates rapid data transmission, and the software driver interacts with the PHY chip through the processing system, which is highly flexible and convenient for precise control.

[0016] Preferably, in step S3, the multiple test cases include a synchronization delay test case, a drift measurement test case, a timestamp accuracy test case, and a packet loss rate verification test case. The multiple test cases can obtain the precision and accuracy of synchronization in multiple aspects, thereby ensuring the precision and accuracy of the entire test.

[0017] Preferably, in step S4, after completing the multi-angle performance analysis, compliance verification is continued to detect whether the final test result complies with the IEEE 1588 standard. The IEEE 1588 standard is a high-precision standard with high versatility, and compliance with the standard also ensures the accuracy and precision of the test.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The technical solution of the present invention performs clock synchronization testing through the PHY chip and ZYNQ chip of the master-slave system, and can accurately display the test results at the oscilloscope, which is also convenient for analysis and effectively improves the accuracy of the test; at the same time, the processing system and programmable logic structure of the ZYNQ chip are optimized, corresponding transmission is performed with a variety of dedicated high-efficiency interfaces, and a plurality of test cases are controlled by the MAC controller under the control of the software driver, which can effectively achieve accurate clock alignment and time synchronization; in addition, a variety of test cases are set and multi-angle performance analysis is performed on the final test results to further improve the reliability of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a flow chart of a PTP test method for a Gigabit Ethernet PHY chip based on ZYNQ;

[0021] Figure 2 A schematic diagram of a framework in which a ZYNQ chip is connected to an oscilloscope and a corresponding PHY chip;

[0022] Figure 3 A schematic diagram of a framework for connecting a master system to a slave system. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0024] like Figure 1 FIG. 1 is a flowchart of a PTP test method for a Gigabit Ethernet PHY chip based on ZYNQ. ZYNQ is a system-level chip. During the test, software testing, second pulse signals and clock comparison are combined to test the accuracy and precision of clock synchronization. The method specifically includes the following steps:

[0025] S1. Perform hardware configuration: set up two identical ZYNQ chips and two identical PHY chips, wherein the two ZYNQ chips are used as the master ZYNQ chip and the slave ZYNQ chip respectively, and the two PHY chips are used as the master PHY chip and the slave PHY chip respectively. Set up a master system and a slave system, wherein the master system includes an interconnected master ZYNQ chip and a master PHY chip, and the slave system includes an interconnected slave ZYNQ chip and a slave PHY chip, and the master PHY chip is connected to the slave PHY chip via a cable and an oscilloscope respectively; construct the same test environment inside the master ZYNQ chip and the slave ZYNQ chip respectively, integrate the same clock source and simulate the same network conditions. Among them, the structure of connecting the master ZYNQ chip to the master PHY chip and the oscilloscope is the same as the structure of connecting the slave ZYNQ chip to the slave PHY chip and the oscilloscope.

[0026] like Figure 2 The figure shows a schematic diagram of the framework of connecting a ZYNQ chip to an oscilloscope and a corresponding PHY chip. Figure 1 and Figure 2 As shown, any ZYNQ chip in step S1 includes a programmable logic and a processing system. The processing system is provided with a MAC controller, and the MAC controller is used to connect the corresponding PHY chip and the software driver and to control whether to test multiple test cases; the programmable logic is provided with a hardware trigger module and an IP core, and the IP core is respectively connected to the processing system and the hardware trigger module. The hardware trigger module is used to control the IP core to transmit the corresponding second pulse signal to the oscilloscope when testing any test case.

[0027] The IP core is an IEEE 1588 IP core, which includes interconnected register units and real-time clock units. Both units are controlled by the hardware trigger module. The register unit is connected to the processing system to achieve data interaction with the processing system; the real-time clock unit is an integrated clock source, which is used to connect to the oscilloscope to transmit second pulse signals, and can also send clock signals to the processing system through the register unit, thereby achieving synchronization of various components or units inside the ZYNQ chip. The IEEE 1588 IP core is a high-precision IP core that can ensure the accuracy of the test.

[0028] In addition, the simulated network conditions are set by the user to make the test more in line with the actual scenario and increase the reliability and practicality of the test. For example, when the real-time clock unit sends a clock signal, a timer is added to each transmission line of the real-time clock unit to set the delay.

[0029] The MAC controller is a media access controller, which is connected to a timestamp unit, a central connection unit, and a status and control register. The timestamp unit is used to capture the inbound port time of the PTP message. The timestamp unit can record the precise time of the PTP event message and obtain these timestamps by accessing the status and control register through the software driver. The MAC controller connects to the corresponding software driver through the MIO multi-function interface and to the corresponding PHY chip through the RGMII interface to achieve data interaction among the three. When using the RGMII interface, the number of actual signal lines required is small, and the MAC controller and the corresponding PHY chip are allowed to transmit over a long distance, which allows for more flexible actual layout; when the MAC controller needs to communicate with the corresponding PHY chip, the pins of the RGMII interface will be assigned to the MIO multi-function interface, that is, the MIO multi-function interface and the RGMII interface are used for communication at the same time. The central connection unit is an interconnection structure unit inside the chip for connecting different parts. The central connection unit connects the MAC controller, the MIO multi-function interface, the IP core, and the application processor module respectively to achieve data interaction and control of different parts, so as to achieve subsequent testing. When the central connection unit is connected to the MIO multi-function interface, it is connected through the UART interface and the SDIO interface respectively. The UART is an asynchronous serial communication interface used for data transmission and debugging; the SDIO interface is an interface for expanding storage capacity or connecting SDIO peripherals, that is, an interface for adapting the connection between the software driver and the PHY chip. The application processor module is the processing center, which is used to perform the test of multiple test cases in the future, and is also connected to the mounted DDR through the memory interface for data access.

[0030] The PHY chip also has an MDIO interface, through which the status and control registers related to the PTP function can be accessed, and then various parameters related to the PTP function can be obtained or adjusted, such as the clock frequency, interrupt function, and timestamp configuration.

[0031] It should be noted that the MDIO of the MDIO interface stands for Management Data Input / Output, which is an interface for managing data input or output; the IP of the IP core stands for Intellectual Property Core, which is an intellectual property core used in integrated circuit design; the IEEE stands for Institute of Electrical and Electronics Engineers, which means the Institute of Electrical and Electronics Engineers, and the IEEE 1588 IP core is an IP core that complies with the 1588 standard of the Institute of Electrical and Electronics Engineers; the RGMII in the RGMII interface stands for Reduced Gigabit Media Independent Interface, which is a reduced gigabit media independent interface; the MIO in the MIO multi-function interface stands for Multiuse I / O, which is a multi-function input or output interface; the MAC of the MAC controller stands for Media Access Controller, which is a media access controller.

[0032] Specifically, the following requirements are imposed on the MAC controller:

[0033] High-precision timestamp function: The MAC controller needs to be able to provide or support high-precision timestamp function to meet the strict requirements of PTP for time synchronization;

[0034] Support for hardware implementation of PTP: The MAC controller shall support or be compatible with the hardware implementation of PTP, including but not limited to being able to process PTP messages and related timestamp information;

[0035] Interface type matching: The MAC controller should support the interface type that matches the PHY chip;

[0036] Sufficient processing power: The MAC controller needs to have sufficient processing power to handle Ethernet data transmission and implement the time correction and synchronization required by the PTP protocol;

[0037] Good PCB layout design: The layout of the MAC controller on the circuit board should consider signal integrity, avoid signal interference and improve communication quality;

[0038] Stable power supply and clock source: MAC controller requires stable power supply and accurate clock source to ensure the accuracy of time synchronization and stable operation of the system;

[0039] Status indication and monitoring: MAC controller should provide status indication and monitoring functions to facilitate debugging and maintenance;

[0040] Compliance with IEEE 802.3 standards: The MAC controller should fully comply with the 10Mbit / s, 100Mbit / s, and 1000Mbit / s Ethernet standards specified in the IEEE 802.3 and IEEE 802.3u specifications.

[0041] By meeting the above requirements, the MAC controller can effectively cooperate with the Gigabit Ethernet PHY chip that supports the PTP function to achieve accurate time synchronization and network communication.

[0042] like Figure 3 As shown, it is a schematic diagram of the framework of the master system connecting the slave system. For two ZYNQ chips and two PHY chips, the two ZYNQ chips are the same, and the two PHY chips are also the same. When the PTP test of two PHY chips is performed with this framework, the PHY chip can use RTL8211, which is a PHY chip suitable for high-performance Ethernet communication. It can maintain high speed and stability of transmission during testing. The two RTL8211 can be connected to the oscilloscope through the built-in CLK_OUT pin. CLK_OUT is the abbreviation of Clock Output, which means clock output. The ZYNQ chip can actually use the XC7Z020 chip in the ZYNQ70OO chip model for testing. Its built-in MAC controller can meet the above performance requirements. At the same time, the XC7Z020 chip can use the MDC port, MDIO port and RGMII port to interact with RTL8211 for data. The MDC of the MDC port refers to Management Data Clock, which is a port for managing data clock. In this application, the port of each model means the communication endpoint of the interface of this model at the hardware level. The XC7Z020 chip integrates two major modules, PS and PL. PS is the processing system and PL is the programmable logic, realizing dual programmability of software and hardware. The ZYNQXC7Z020 chip is not only a microprocessor, but also a MAC device with PTP function.

[0043] The PS is equipped with two completely independent Gigabit Ethernet controllers that support full-duplex communication at 10 / 100 / 1000 Mb / s and comply with the IEEE 802.3 2008 standard. These controllers exchange data with the outside world through the MIO port using the RGMII standard, which includes software drivers and PHY chips. When needed, these signals can be flexibly transferred to the PL part through the EMIO port extended by the MIO multi-function interface, thereby achieving direct connection with the PL. In the PL, the incoming signals can be customized through hardware programming, which provides great flexibility for real-time data processing. The built-in packet filtering module of the Gigabit Ethernet controller can intelligently identify packets of the PTPv2 protocol, which is the second version of the PTP protocol, and then access the timestamp-related information stored in the status register through the corresponding register interface, or use the control register through the corresponding register interface to fine-tune the MAC controller and the timestamp unit. Here, the status register and the control register can also use the status and control registers with integrated functions.

[0044] In addition, at the system level of the ZYNQ chip, the Linux operating system can be ported, the startup file can be imported through the JTAG interface, and the UART interface can be used for system debugging. The full name of the JTAG interface is Joint Test Action Group, which means Joint Test Action Group. This interface is an international standard interface. The kernel under the Linux operating system has built-in support for PTP since version 3.1, allowing the timestamp unit in the ZYNQ chip to be controlled through the driver to obtain timestamp information or adjust the timestamp function. At the application layer, the open source project PTPd or LinuxPTP can be ported to build a complete software state machine. Among them, PTPd is the Precision Time Protocol daemon, which is an open source project for achieving high-precision clock synchronization; LinuxPTP is the PTP implementation in the Linux operating system, which is also an open source project.

[0045] S2. Setting software driver: respectively setting corresponding software drivers for the two ZYNQ chips in step S1, using each software driver to control the PTP of the corresponding PHY chip, and at the same time synchronizing the time of the corresponding PHY chip with the corresponding ZYNQ chip.

[0046] In this embodiment, when the software driver is used to control the PTP of the corresponding PHY chip in step S2, the software driver is first connected to the MIO multi-function port in the corresponding processing system through the UART interface and the JTAG interface, and then connected to the corresponding PHY chip, so as to achieve interaction. The JTAG interface is convenient for program debugging, the UART interface is convenient for fast data transmission, and the software driver interacts with the PHY chip through the processing system, which is highly flexible and convenient for precise control.

[0047] S3. Conduct testing: After completing the time synchronization of step S2, set multiple test cases and store the multiple test cases in each software driver of step S2 at the same time, and then start testing, test each test case in turn, use an oscilloscope to obtain each first second pulse signal and each first PTP synchronous output clock corresponding to the master ZYNQ chip under each test case, and use an oscilloscope to obtain each second second pulse signal and each second PTP synchronous output clock corresponding to each slave ZYNQ chip under each test case; use each first second pulse signal, each first PTP synchronous output clock, each second second pulse signal and each second PTP synchronous output clock as the final test result.

[0048] In actual testing, although the structure of the master system is the same as that of the slave system, in order to facilitate the distinction between the master system and the slave system, the first and second prefixes can be used to distinguish the internal resources and related signals of the two systems. For example, each resource or signal in the master system can be named as the first software driver, the first PTP, the first second pulse signal, the first PTP synchronous output clock, the first programmable logic, the first processing system, the first MAC controller, the first hardware trigger module, the first IP core, the first register unit, the first real-time clock unit, the first application processor module, the first timestamp unit, the first MIO multi-function interface, the first central connection unit, the first status and control register, the first UART interface and the first JTAG interface, and then the corresponding resource or signal in the slave system is given the second prefix, so as to facilitate the distinction between the master system and the slave system during actual testing and record related data.

[0049] In this embodiment, in step S3, multiple test cases include synchronization delay test cases, drift measurement test cases, timestamp accuracy test cases and packet loss rate verification test cases. Synchronization delay test: record the sending and receiving timestamps of PTP messages, calculate the average delay, maximum delay and minimum delay, and these delays can reflect the precision and accuracy of synchronization. Drift measurement test: record the local clock timestamp of the system running for a period of time, and compare it with the reference clock, that is, analyze and compare the two clocks of the PHY chip and the corresponding ZYNQ chip to determine whether they can be stable in the long term. Timestamp accuracy test: analyze the recorded timestamp data to ensure the accuracy and consistency of the timestamp record. Packet loss rate verification test: send a certain number of PTP messages, record the number of messages received, calculate the packet loss rate, and analyze the cause of the packet loss for manual processing. Through these test cases, the time synchronization performance of PTP in the network can be fully evaluated, including synchronization delay, clock source stability, timestamp accuracy and message loss. These tests help to ensure the accuracy and accuracy of PTP in practical applications, and thus ensure the accuracy and accuracy of the entire test.

[0050] S4, monitoring and analysis: Perform multi-angle performance analysis of delay, jitter and synchronization accuracy on the final test result in step S3 to determine whether it meets the performance requirements of the test. If so, end the test; if not, return to step S1 to build the same test environment inside the main ZYNQ chip and the slave ZYNQ chip respectively, and loop until the performance requirements of the test are met, then end the test.

[0051] In this embodiment, in step S4, after completing the multi-angle performance analysis, compliance verification can be continued to detect whether the final test result complies with the IEEE 1588 standard. The IEEE 1588 standard is a high-precision standard with high versatility. Compliance with the standard also ensures the accuracy and precision of the test.

[0052] In summary, the present invention performs clock synchronization testing through the PHY chip and ZYNQ chip of the master-slave system, and can display accurate test results on the oscilloscope, which is also convenient for analysis and effectively improves the accuracy of the test; at the same time, the processing system and programmable logic structure of the ZYNQ chip are optimized, and corresponding transmission is performed with a variety of dedicated high-efficiency interfaces, and a plurality of test cases are controlled by the MAC controller under the control of the software driver, which can effectively achieve accurate clock alignment and time synchronization; in addition, a variety of test cases are set and multi-angle performance analysis is performed on the final test results, which further improves the reliability of the test and has significant progress.

[0053] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A Gigabit Ethernet PHY chip PTP test method based on ZYNQ, characterized in that: The method comprises the following steps: S1. Perform hardware configuration: A master system and a slave system are set, the master system includes an interconnected master ZYNQ chip and a master PHY chip, the slave system includes an interconnected slave ZYNQ chip and a slave PHY chip, and the master PHY chip is connected to the slave PHY chip via a cable and an oscilloscope respectively; Build the same test environment inside the master ZYNQ chip and the slave ZYNQ chip to integrate the same clock source and simulate the same network conditions; S2. Set up software driver: A first software driver is set for the master ZYNQ chip in step S1 and a second software driver is set for the slave ZYNQ chip in step S1, respectively, the first software driver is used to control the first PTP of the master PHY chip, and the master PHY chip is synchronized with the master ZYNQ chip; the second software driver is used to control the second PTP of the slave PHY chip, and the slave PHY chip is synchronized with the slave ZYNQ chip; S3. Test: After completing step S2, a plurality of test cases are set and the plurality of test cases are stored in the first software driver and the second software driver simultaneously; Test each test case in turn, use an oscilloscope to obtain each first second pulse signal and each first PTP synchronous output clock corresponding to the master ZYNQ chip under each test case, and use an oscilloscope to obtain each second second pulse signal and each second PTP synchronous output clock corresponding to each slave ZYNQ chip under each test case; take each first second pulse signal, each first PTP synchronous output clock, each second second pulse signal, and each second PTP synchronous output clock as the final test result; S4. Monitoring and Analysis: The final test result in step S3 is subjected to multi-angle performance analysis of delay, jitter and synchronization accuracy to determine whether it meets the performance requirements of the test. If so, the test is terminated; if not, the process returns to step S1 to construct the same test environment inside the master ZYNQ chip and the slave ZYNQ chip respectively, and the test is terminated until the performance requirements of the test are met.

2. According to a ZYNQ-based Gigabit Ethernet PHY chip PTP testing method according to claim 1, it is characterized in that: In step S1, the main ZYNQ chip includes a first programmable logic and a first processing system. The first processing system is provided with a first MAC controller. The first MAC controller is used to connect the main PHY chip and the first software driver, and is also used to control whether each test case in the first software driver is tested; the first programmable logic is provided with a first hardware trigger module and a first IP core. The first IP core is connected to the first processing system and the first hardware trigger module respectively. The first hardware trigger module is used to control the first IP core to transmit the corresponding first second pulse signal to the oscilloscope when the first software driver performs any test case test; the structure of the slave ZYNQ chip is the same as that of the main ZYNQ chip.

3. A ZYNQ-based Gigabit Ethernet PHY chip PTP testing method according to claim 2, characterized in that: The first IP core is an IEEE 1588 IP core, which includes an interconnected first register unit and a first real-time clock unit. The first register unit and the first real-time clock unit are both controlled by a first hardware trigger module. The first register unit is connected to a first processing system, and the first real-time clock unit is connected to an oscilloscope.

4. A ZYNQ-based Gigabit Ethernet PHY chip PTP testing method according to claim 2, characterized in that: The main ZYNQ chip also includes a first application processor module, a first timestamp unit, a first RGMII interface, a first MIO multi-function interface, a first central connection unit and a first status and control register; the first MAC controller is respectively connected to the first timestamp unit, the first central connection unit and the first status and control register, the first MAC controller is connected to the first software driver through the first MIO multi-function interface and to the main PHY chip through the first RGMII interface, the first central connection unit is respectively connected to the first MAC controller, the first MIO multi-function interface, the first IP core and the first application processor module, and the first application processor module is used to execute tests of multiple test cases.

5. A ZYNQ-based Gigabit Ethernet PHY chip PTP testing method according to claim 2, characterized in that: When the first software driver is used to control the first PTP of the master PHY chip in step S2, the first software driver is first connected to the first processing system through the first UART interface and the first JTAG interface, and then connected to the master PHY chip through the first processing system; when the second software driver is used to control the second PTP of the slave PHY chip in step S2, the second software driver is first connected to the second processing system through the second UART interface and the second JTAG interface, and then connected to the slave PHY chip through the second processing system.

6. A ZYNQ-based Gigabit Ethernet PHY chip PTP testing method according to claim 1, characterized in that: In step S3, the multiple test cases include a synchronization delay case, a drift measurement case, a timestamp accuracy case, and a packet loss rate verification case.

7. The method for testing a Gigabit Ethernet PHY chip PTP based on ZYNQ according to claim 1, characterized in that: In step S4, after completing the multi-angle performance analysis, compliance verification is continued to detect whether the final test result complies with the IEEE1588 standard.

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