Optimization method of resistive three-input majority logic circuit

Abstract

The invention discloses an optimization method of a resistive three-input majority logic circuit, which comprises the following steps of: calculating an optimal resistive three-input majority-inverter graph RM3IG of all four-input NPN Boolean functions by utilizing an accurate comprehensive algorithm based on Boolean satisfiability SAT and NPN equivalent classification, and establishing an offline database; converting the input circuit into an RM3IG structure through a graph mapping algorithm and an offline database; based on the algebraic property of the RM3 logic, an inverter transmission rule in the RM3IG structure is provided, the number of inverters in the RM3IG structure is optimized, finally, the inverters in the RM3IG structure are represented by using the RM3 logic, and a logic circuit only taking the RM3 logic as a basic operation set is obtained. According to the method, the area and delay of a logic circuit taking RM3 logic as a basic operation set are effectively reduced, and particularly, when the method is applied to a memristor circuit, the number of required memristors can be remarkably reduced, and the design cost is reduced.

Description

Technical Field

[0001] The invention relates to a method for optimizing a logic circuit, and in particular to a method for optimizing a resistive three-input majority logic circuit. Background Art

[0002] The storage wall and power consumption wall brought by the von Neumann architecture's storage-computing separation computing system limit the growth of computing power. It requires frequent data transfer between the CPU and the memory, making the data transfer overhead much greater than the data operation overhead. Therefore, a new computing paradigm of storage and computing integration is needed, which eliminates the data transfer between them by merging the memory and the processor. In recent years, resistive random access memory (ReRAM) has aroused widespread research interest in the system design and synthesis of storage-computing integrated circuits. ReRAM has high scalability and low standby leakage energy characteristics. Its internal resistance state switching can realize resistive three-input majority (3-input Resistive Majority, RM3) logic, and logical operations can be performed directly in the ReRAM device.

[0003] Logic synthesis plays a vital role in emerging technology design, and since the advent of this field, extensive research has been conducted on optimizing logic circuits. Current logic synthesis methods for storage-computation-in-one based on RM3 logic use existing general-purpose logic circuits such as And-Inverter Graphs (AIG) and Majority-Inverter Graphs (MIG) to derive resistive three-input majority logic circuits (i.e., RM3 logic circuits). However, this approach fails to provide guidance on how to achieve the optimal cost trade-off because the cost associated with the inverter must be considered. In AIG and MIG, inverters do not affect the circuit scale, while when they are mapped to RM3 logic circuits, each inverter requires one RM3 logic to implement. This situation results in additional ReRAM requirement costs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to propose an optimization method for a resistive three-input majority logic circuit in view of the shortcomings of the prior art. The method first uses an accurate synthesis algorithm based on Boolean Satisfiability (SAT) and negation-permutation-negation (NPN) equivalence classification to calculate the optimal resistive three-input majority-inverter graph (RM3IG) of all four-input NPN Boolean functions, and establishes an offline database. Then, the input circuit is efficiently converted into an RM3IG structure through a graph mapping algorithm and an offline database, and then the number of inverters in the RM3IG structure is optimized. Finally, the inverters in the RM3IG structure are represented by using RM3 logic to obtain a logic circuit with only RM3 logic as the basic operation set. The optimization method of the present invention effectively reduces the area and delay of the logic circuit with RM3 logic as the basic operation set, especially when applied to a memristor circuit, it can significantly reduce the number of required memristors and reduce the design cost.

[0005] The technical solution adopted by the present invention to solve the above technical problem is: an optimization method for a resistive three-input majority logic circuit, comprising the following steps: S1. Calculate the optimal resistive three-input majority-inverter graph RM3IG (3-input Resistive Majority-Inverter Graph, RM3IG) of all four-input NPN Boolean functions using an exact synthesis algorithm based on Boolean satisfiability SAT ((Satisfiability, SAT)) and NPN (Negation-Permutation-Negation, NPN) equivalence classification, and establish an offline database; S2, convert the input circuit into RM3IG structure through graph mapping algorithm and offline database; S3. Based on the algebraic properties of RM3 logic, the inverter transmission rules in the RM3IG structure are proposed, and the number of inverters in the RM3IG structure is optimized. Finally, by using RM3 logic to represent the inverters in the RM3IG structure, a logic circuit with only RM3 logic as the basic operation set is obtained.

[0006] In a specific implementation manner, the specific process of step S1 is: S1.1. Define four Boolean variables: x it , g hi , S ijkl , Pci ,in: x it Indicates the circuit i Logic Gates x i In the truth table of the logic function t The value of the bit; g hi Represents a logic gate x i Is the output of the circuit the original output? If the logic gate x i The output of the circuit is h Raw output g hi , then the Boolean variable g hi The value is true, otherwise it is false; S ijkl Represents a logic gate x i The three inputs x j , x k and x l The connection relationship and whether the three inputs execute RM3 logic. If the logic gate x i The three inputs x j , x k and x l Execute RM3 logic, then the Boolean variable S ijkl The value is true, otherwise it is false, where j , k and l The value range is: 0≤ j < l < i , 0≤ k < i , j ≠ k ≠ l ; P ci Represents a logic gate x i The three inputs x j , x k and x l The polarity of c =1,2,3, ifP ci =1, indicating a logic gate x i The three inputs x j , x k and x l The polarity of is negative, otherwise it is positive; S1.2. A logic circuit consisting of RM3 logic and negation logic is used as a logic function. In addition to the original input and original output, each logic gate performs RM3 logic operations. The negation logic is represented by the dotted lines connecting the edges in the circuit. The main constraints in the RM3 logic are: , In formula (1), the symbol “→” represents the actual implied logical operation, and the symbol “ " indicates strict equivalence; Formula (1) indicates that if the logic gate x i The three inputs are x j , x k and x l , and the three inputs perform RM3 logic operation, namely , then the logic gate x i The value of x it Expressed as ,in x kt The horizontal line on the represents the inherent inverting nature of RM3 logic; make , so formula (1) can be further expressed as: , in" ” represents the AND gate; The logic gates in the circuit are converted into the description form of CNF formula using Tseytin transformation method, which is further simplified to: , in s ijkl , x it and c jklt The horizontal line on the represents the negation operation. ” represents the OR gate; To sum up, the main clause of RM3 logic is encoded as follows: , In addition, if the logic gate x i is the original output of the circuit, then x i The logic function truth table must be equal to the original output of the circuit g h So we add the constraint: , in( t 1, t 2,…, t n )2Yes t The binary code of " ” stands for logical exclusive OR; To ensure the original output of the circuit g h Must be a logic gate x i Output of adding constraints: , To ensure that each logic gate in the circuit has three legal inputs, add the constraints: , Finally, to ensure that only one of the three inputs of each logic gate has an inverter, add the constraint: , S1.3. Based on the constraints obtained above, the number of RM3 logic gates required is first set to 0, and a CNF constraint file is obtained by encoding. The obtained CNF constraint file is then transmitted to a Boolean satisfiability solver, i.e., a SAT solver. The SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​satisfy equations (4) to (8) and are all true. If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the number of RM3 logic gates required is increased by 1, and the code and solution are re-performed until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned; S1.4. Based on the results representing the optimal solution returned by the SAT solver, the optimal resistive three-input majority-inverter diagram RM3IG of all four-input NPN Boolean functions is calculated using NPN equivalent classification, and an offline database is established.

[0007] In a specific implementation manner, the specific process of step S2 is: S2.1. Given an input circuit NAND graph AIG, first use the cut enumeration algorithm to find the four-input cuts for each node of AIG. S2.2, apply NPN equivalent classification to normalize each cut and obtain the Boolean function of the cut; S2.3, matching the offline database established in step S1 with the cut Boolean function; S2.4. Cover the matching result into AIG to obtain the RM3IG structure of the input circuit.

[0008] In a specific implementation manner, the specific process of step S3 is: S3.1, calculate the initial total number C1 of inverters in the RM3IG structure; S3.2. Determine each RM3 node in the RM3IG structure n The improvement in the number of inverters caused by the implementation of the inverter transmission rule is recorded as saving, where for each RM3 node n , satisfying the following inverter transmission rules: , In the formula x , y , z The horizontal line on the left indicates that there is an inverter on the input connection line of the logic gate, and the "=" indicates that the logical functions of the two RM3 nodes on the left and right sides of the equation are consistent; According to the number of inverters of the node before optimization minus the number of inverters of the node after optimization, the savings of each node are calculated. If the savings is a positive number, the inverter transmission rule is executed in the RM3IG structure and the process goes to step S3.4. If the savings is a negative number, the process goes to step S3.3. S3.3. Define the node set Q to consist of nodes r and r The output connection lines of all nodes connected to the set Q are used to determine the improvement in the number of inverters caused by all nodes in the set Q before and after executing the inverter transmission rule, which is recorded as savings_two_level; for each node in the set Q, call equations (9) to (12) to calculate its savings, and then savings_two_level is the savings of all nodes in the set Q; S3.4, traverse the next node in the RM3IG structure, repeat steps S3.2 to S3.3, until all nodes in the RM3IG structure are traversed, completing the first optimization of the number of inverters in the RM3IG structure; S3.5, after completing the first optimization of the number of inverters in the RM3IG structure, calculate the total number of inverters C2 in the current RM3IG structure, and repeat the same cycle for the first time.m Optimize all the time, m is a positive integer equal to or greater than 2, until m The total number of inverters in the RM3IG structure after optimization is m If the total number of inverters in the RM3IG structure is equal before the optimization, it means that the optimal result of the number of inverters in the RM3IG structure has been obtained, and the optimization is completed; finally, by calling formula (13), the inverters in the RM3IG structure are represented by RM3 logic, and the logic circuit with only RM3 logic as the basic operation set is obtained: .

[0009] Compared with the prior art, the present invention has the following advantages: (1) The present invention proposes an optimization method for a resistive three-input majority logic circuit. First, the optimal resistive three-input majority-inverter graph (RM3IG) of all four-input NPN Boolean functions is calculated using an exact synthesis algorithm based on Boolean Satisfiability (SAT) and Negation-Permutation-Negation (NPN) equivalence classification, and an offline database is established. Then, the input circuit is efficiently converted into an RM3IG structure through a graph mapping algorithm and an offline database. Then, the number of inverters in the RM3IG structure is optimized. Finally, the inverters in the RM3IG structure are represented by RM3 logic, and a logic circuit with only RM3 logic as a basic operation set is obtained. (2) The optimization method of the present invention does not change the RM3IG structure during the entire optimization process, while reducing the number of inverters in the RM3IG structure. Experimental results show that the optimization method of the present invention reduces the number of inverters by an average of 18.2 times in commonly used benchmark circuits, reduces the circuit area by an average of 14.0%, and reduces the delay by an average of 17.7%, significantly reducing the complexity of the circuit. The optimization method of the present invention effectively reduces the area and delay of logic circuits with RM3 logic as the basic operation set, especially when applied to memristor circuits, it can significantly reduce the number of required memristors and reduce design costs. The present invention not only optimizes the hardware requirements of the circuit, but also provides a new idea and method for circuit design based on RM3 logic, and has a wide range of practical application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The structure of the RM3 logic circuit composed of ReRAM; Figure 2 is the truth table of the logic function of the RM3 logic circuit composed of ReRAM; Figure 3 For the circuit of the example, a circuit schematic diagram with RM3 logic as the basic operation set is obtained through AIG one-to-one mapping; Figure 4 A schematic diagram of a circuit using RM3 logic as a basic operation set obtained by the method of the present invention for an example circuit; Figure 5 The process of the graph mapping algorithm; Figure 6 An example of the inverter number optimization process in a simple RM3IG structure. DETAILED DESCRIPTION

[0011] The present invention is further described in detail below with reference to the accompanying drawings.

[0012] Figure 1 The structure of the RM3 logic circuit composed of ReRAM. Figure 2 is the truth table of the logic function of the RM3 logic circuit composed of ReRAM. ReRAM is a two-terminal device with an internal resistance state, whose internal resistance can be a low resistance state (LRS) or a high resistance state (HRS), representing the binary values ​​0 and 1, respectively. The resistance state Zn of these devices can be changed by applying a positive or negative voltage. The state is a function of the previous resistance state Z, the voltage at terminal P, and the voltage at terminal Q, such as Figure 1 By representing Z as the value stored in the switch and Zn as the value stored after applying a signal to the P and Q terminals, Zn can form an RM3 logic operation as follows: , Take a Boolean expression as Take a simple circuit as an example, the truth table of its circuit logic function is (10010110)2. For this circuit, Figure 3 The schematic diagram of the circuit using RM3 logic as the basic operation set is obtained through the existing one-to-one mapping of AIG. Figure 3 In (b), all nodes are RM3 logic. FIG4 is a schematic diagram of a circuit with RM3 logic as the basic operation set obtained by the method of the present invention for the circuit. The advantage of the method of the present invention is that the optimal resistive three-input majority-inverter RM3IG structure (i.e., the optimal RM3IG structure) of the circuit is obtained without changing the logic function of the circuit, and then Figure 4 The number of inverters in the RM3IG structure shown in (b) is optimized, and the inverters in the optimized RM3IG structure are represented by RM3 nodes, and a circuit with only RM3 logic as the basic operation set is obtained, that is, Figure 4 (c) in .

[0013] For Boolean expressions The implementation process of solving the optimal RM3IG structure of a simple circuit using the optimization method of the present invention includes the following steps: Step 1: Define Boolean variables Define four Boolean variables: x it , g hi , S ijkl , P ci ,like Figure 4 As shown, the original input of the circuit is x 1 (ie variable x ), x 2 (ie variable y ), x 3 (ie variable z ), the middle logic gate is x 4. x 5 , x 6, the original output is g 1; Step ②: Convert the constraint problem in RM3 logic into a conjunctive normal form formula, i.e. CNF formula The constraint formulas for RM3 logic are: ' Where 4≤ i ≤6,0≤ j < l < i , 0≤ k < i , j ≠ k ≠ l , h =1,0≤ t ≤7; Step ③: Based on the constraints obtained in step ②, first set the required number of RM3 logic gates to 0, encode to obtain a CNF constraint file; then transmit the obtained CNF constraint file to the SAT solver; Step ④: The SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​satisfy the above constraint condition formulas and are all true; If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the number of RM3 logic gates required is increased by 1, and the code is re-encoded and solved until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned. The final result is shown in Figure 4 .

[0014] In the above simple digital circuit, the logic gate x 4. x 5. x 6 are all RM3 logic gates, and their RM3 logic gate truth table is:

[0015] In Boolean variables g hi middle, g 16 is 1, and the rest g hi is 0; in the Boolean variable S ijkl middle, S 4123 , S 5243 , S 6154 is 1, and the rest S ijkl is 0; in the Boolean variable P ci middle, P 34 , P 25 , P 36 is 1, and the rest P ci is 0.

[0016] For all digital circuit logic functions of four-input NPN equivalent classes (a total of 222 functions), the optimization method of the present invention is used to obtain the best RM3IG of the circuit logic function, and an offline database is established. Then, the input circuit is converted into an RM3IG structure using the graph mapping algorithm and the offline database. The flow of the graph mapping algorithm is shown in Figure 5 Finally, the number of inverters in the RM3IG structure is optimized.

[0017] Figure 6 An example of the inverter number optimization process in a simple RM3IG structure is shown, where Figure 6 (a) is a schematic diagram of the structure of the RM3IG before structural optimization. Figure 6 (b) is the node in the RM3IG structure. n 1 andn 2. Schematic diagram of the structure after optimizing the number of inverters. Figure 6 (c) in the figure is the node in the RM3IG structure. n 3 is a schematic diagram of the structure after the optimization of the number of inverters. In FIG6 , the dotted lines between nodes represent inverters, and the bubbles represent the inherent inversion characteristics of the RM3 logic. The advantage of the optimization method of the present invention is that the number of inverters can be optimized by reducing the inverter transmission rules without changing the connection lines and nodes (i.e., without changing the RM3IG structure).

[0018] The optimization method of the present invention is used to Figure 6 The number of inverters in the RM3IG structure shown in (a) is optimized, and the optimization process includes the following steps: Step ①: Calculate the initial total number of inverters C1 in the RM3IG structure, and calculate that C1 is 6; Step ②: Determine the nodes in the RM3IG structure n The positions and numbers of the inverters on the input and output connection lines of 1 are based on the inverter transmission rule (11), that is, , calculate the node n The value of savings of 1 is 2; Step 3: For nodes in the RM3IG structure n 2. Repeat step ②, according to the inverter transmission rule (10), that is, , calculate the node n The value of savings of 2 is 2; node n 1 Execute the inverter transmission rule (11), node n 2 After executing the inverter transmission rule (10), the schematic diagram of the RM3IG structure is shown in Figure 6 (b) Step ④: For nodes in the RM3IG structure n 3. According to the inverter transmission rule (11), , calculate the node n The value of savings of 3 is 2, completing the first pass optimization of the number of inverters in the RM3IG structure; node n 3 After executing the inverter transmission rule (4), the schematic diagram of the RM3IG structure is shown in Figure 6 (c) Step ⑤: After completing the first optimization of the number of inverters in the RM3IG structure, calculate the total number of inverters C2 in the current RM3IG structure. The calculated value of C2 is 0, and C2﹤C1, indicating that the optimal result for the number of inverters in the RM3IG structure has been obtained. There is no need for a second optimization, and the optimization is completed.

[0019] For commonly used circuits, we use the method of the present invention to convert and obtain the initial RM3IG structure. The results are shown in the first four columns of Table 1, where "Original Input / Output", "Area", "Delay" and "Original Inverter" respectively represent the input / output scale of the circuit, the number of nodes in the RM3IG structure, the initial number of levels and inverters, and the "Optimized Inverter" column is the number of inverters after optimization; Adder, Barrel Shifter, Divisor, Hypotenuse, Log2, Max, Multiplier, Sine, Square-root, Square are the names of existing commonly used circuits. Since the inverter is represented by the supplementary edge in the RM3IG structure, the circuit area and delay do not include the inverter. It can be seen from Table 1 that the optimization method of the present invention reduces the number of inverters by 18.2 times on average in commonly used circuits. In addition, we also counted the CPU running time, where the "CPU running time" column represents the total CPU running time of the method of the present invention. Since the method of the present invention uses an offline database, the calculation speed is very fast. Therefore, the method of the present invention can be extended to larger and more complex circuits. Finally, we use RM3 nodes to represent the inverters in the RM3IG structure, and generate a logic circuit with only RM3 logic as the basic operation set. We calculate the area and delay of this circuit. Table 2 shows the experimental results. The method of the present invention is compared with the existing MIG one-to-one mapping method. In all test circuits, the circuit area of ​​the method of the present invention is reduced by an average of 14.0%, and the delay is reduced by an average of 17.7%. Therefore, the optimization method of the present invention can effectively reduce the area and delay of the logic circuit with RM3 logic as the basic operation set. When applied to the memristor circuit, it can reduce the cost of the design of the memristor circuit, and enrich the research method of RM3 logic in logic synthesis.

[0020]

[0021]

Claims

1. A method for optimizing a resistive three-input majority logic circuit, characterized in that: The following steps are involved: S1. Calculate the optimal resistive three-input majority-inverter graph RM3IG of all four-input NPN Boolean functions using the exact synthesis algorithm based on Boolean satisfiability SAT and NPN equivalent classification, and establish an offline database; S2, convert the input circuit into RM3IG structure through graph mapping algorithm and offline database; S3. Based on the algebraic properties of RM3 logic, the inverter transmission rules in the RM3IG structure are proposed, and the number of inverters in the RM3IG structure is optimized. Finally, by using RM3 logic to represent the inverters in the RM3IG structure, a logic circuit with only RM3 logic as the basic operation set is obtained.

2. The optimization method of a resistive three-input majority logic circuit according to claim 1, characterized in that: The specific process of step S1 is: S1.

1. Define four Boolean variables: x it , g hi , S ijkl , P ci ,in: x it Indicates the circuit i Logic Gates x i In the truth table of the logic function t The value of the bit; g hi Represents a logic gate x i Is the output of the circuit the original output? If the logic gate x i The output of the circuit is h Raw output g hi , then the Boolean variable g hi The value is true, otherwise it is false; S ijkl Represents a logic gate x i The three inputs x j , x k and x l The connection relationship and whether the three inputs execute RM3 logic. If the logic gate x i The three inputs x j , x k and x l Execute RM3 logic, then the Boolean variable S ijkl The value is true, otherwise it is false, where j , k and l The value range is: 0≤ j < l < i , 0≤ k < i , j ≠ k ≠ l ; P ci Represents a logic gate x i The three inputs x j , x k and x l The polarity of c =1,2,3, if P ci =1, indicating a logic gate x i The three inputs x j , x k and x l The polarity of is negative, otherwise it is positive; S1.

2. A logic circuit consisting of RM3 logic and negation logic is used as a logic function. In addition to the original input and original output, each logic gate performs RM3 logic operations. The negation logic is represented by the dotted lines connecting the edges in the circuit. The main constraints in the RM3 logic are: ， In formula (1), the symbol "→" represents the actual implied logical operation, and the symbol " " indicates strict equivalence; Formula (1) indicates that if the logic gate x i The three inputs are x j , x k and x l , and the three inputs perform RM3 logic operation, namely , then the logic gate x i The value of x it Expressed as ,in x kt The horizontal line on the represents the inherent inverting nature of RM3 logic; make , so formula (1) can be further expressed as: ， in" ” represents the AND gate; The logic gates in the circuit are converted into the description form of CNF formula using Tseytin transformation method, which is further simplified to: ， in s ijkl , x it and c jklt The horizontal line on the " ” represents the OR gate; To sum up, the main clause of RM3 logic is encoded as follows: ， In addition, if the logic gate x i is the original output of the circuit, then x i The logic function truth table must be equal to the original output of the circuit g h Boolean function, so add the constraint: ， in( t 1, t 2,…, t n )2Yes t The binary encoding of " ” stands for logical exclusive OR; To ensure the original output of the circuit g h Must be a logic gate x i Output of , adding constraints: ， To ensure that each logic gate in the circuit has three legal inputs, add the constraints: ， Finally, to ensure that only one of the three inputs of each logic gate has an inverter, add the constraint: ， S1.

3. Based on the constraints obtained above, the number of RM3 logic gates required is first set to 0, and a CNF constraint file is obtained by encoding. The obtained CNF constraint file is then transmitted to a Boolean satisfiability solver, i.e., a SAT solver. The SAT solver assigns values ​​to the Boolean variables in the received CNF constraint file, and searches for a set of Boolean variable assignments whose values ​​satisfy equations (4) to (8) and are all true. If the SAT solver finds such a set of Boolean variable assignments, the result returned is SAT, indicating that the optimal solution has been found; otherwise, the number of RM3 logic gates required is increased by 1, and the code and solution are re-performed until the result returned by the SAT solver is SAT and the result representing the optimal solution is returned; S1.

4. Based on the results representing the optimal solution returned by the SAT solver, the optimal resistive three-input majority-inverter diagram RM3IG of all four-input NPN Boolean functions is calculated using NPN equivalent classification, and an offline database is established.

3. The optimization method of a resistive three-input majority logic circuit according to claim 1, characterized in that: The specific process of step S2 is: S2.

1. Given an input circuit NAND graph AIG, first use the cut enumeration algorithm to find the four-input cuts for each node of AIG. S2.2, apply NPN equivalent classification to normalize each cut and obtain the Boolean function of the cut; S2.3, matching the offline database established in step S1 with the cut Boolean function; S2.

4. Cover the matching result into AIG to obtain the RM3IG structure of the input circuit.

4. The optimization method of a resistive three-input majority logic circuit according to claim 1, characterized in that: The specific process of step S3 is: S3.1, calculate the initial total number C1 of inverters in the RM3IG structure; S3.

2. Determine each RM3 node in the RM3IG structure n The improvement in the number of inverters caused by the implementation of the inverter transmission rule is recorded as saving, where for each RM3 node n , satisfying the following inverter transmission rules: ， In the formula x , y , z The horizontal line on the left indicates that there is an inverter on the input connection line of the logic gate, and "=" indicates that the logical functions of the two RM3 nodes on the left and right sides of the equation are consistent; According to the number of inverters of the node before optimization minus the number of inverters of the node after optimization, the savings of each node are calculated. If the savings is a positive number, the inverter transmission rule is executed in the RM3IG structure and the process goes to step S3.

4. If the savings is a negative number, the process goes to step S3.

3. S3.

3. Define the node set Q consisting of nodes r and r The output connection lines of all nodes connected to the set Q are used to determine the improvement in the number of inverters caused by all nodes in the set Q before and after executing the inverter transmission rule, which is recorded as savings_two_level; for each node in the set Q, call equations (9) to (12) to calculate its savings, and then savings_two_level is the savings of all nodes in the set Q; S3.4, traverse the next node in the RM3IG structure, repeat steps S3.2 to S3.3, until all nodes in the RM3IG structure are traversed, completing the first optimization of the number of inverters in the RM3IG structure; S3.5, after completing the first optimization of the number of inverters in the RM3IG structure, calculate the total number of inverters C2 in the current RM3IG structure, and repeat the same cycle for the first time. m Optimize all the time, m is a positive integer equal to or greater than 2, until m The total number of inverters in the RM3IG structure after optimization is m If the total number of inverters in the RM3IG structure is equal before the optimization, it means that the optimal result of the number of inverters in the RM3IG structure has been obtained, and the optimization is completed; finally, by calling formula (13), the inverters in the RM3IG structure are represented by RM3 logic, and the logic circuit with only RM3 logic as the basic operation set is obtained: 。

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