Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body comprises a first epitaxial layer and a second epitaxial layer, and the first epitaxial layer is used for supporting the second epitaxial layer; the conduction type of the second epitaxial layer is opposite to that of the first epitaxial layer; the semiconductor body comprises a silicon carbide material; or the semiconductor body comprises a gallium nitride material; the second epitaxial layer comprises a well region and a first region, and the well region and the second epitaxial layer have the same conduction type and doping concentration; the gate structure comprises a gate dielectric layer, a gate and an interlayer dielectric layer; the dielectric constant of the gate dielectric layer is larger than that of silicon oxide, the dielectric capacitance of the gate dielectric layer is a negative value, and the gate dielectric layer has a spontaneous polarization characteristic. According to the technical scheme provided by the embodiment of the invention, the switching speed and the reliability of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-oxide semiconductor field-effect transistors (MOSFETs) are semiconductor devices that have the advantages of low on-resistance, high-speed operation, and low switching losses. They are the development direction of the third generation of wide-bandgap semiconductor devices.

[0003] The switching speed and device reliability of the existing third-generation wide bandgap semiconductor MOSFET semiconductor devices need to be further improved to meet practical applications. Summary of the invention

[0004] The present invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the switching speed and device reliability of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body comprising a first surface and a second surface arranged opposite to each other;

[0007] The semiconductor body comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is arranged on the first surface, and the first epitaxial layer is used to support the second epitaxial layer;

[0008] The conductivity type of the second epitaxial layer is opposite to the conductivity type of the first epitaxial layer; the semiconductor body comprises silicon carbide material; or the semiconductor body comprises gallium nitride material;

[0009] The second epitaxial layer includes a well region and a first region, the well region and the second epitaxial layer have the same conductivity type and doping concentration; the first region is arranged on the first surface, the first region and the well region have opposite conductivity types, and the well region is arranged on a side of the first region away from the first surface;

[0010] A gate structure, wherein the gate structure comprises a gate dielectric layer, a gate and an interlayer dielectric layer; the gate structure is located on the first surface, or the gate structure extends from the first surface into the semiconductor body; the gate dielectric layer is used to insulate the gate and the semiconductor body; the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer is negative, and the gate dielectric layer has a spontaneous polarization characteristic;

[0011] A source electrode, the source electrode is located on the first surface, or the source electrode extends from the first surface into the semiconductor body; the interlayer dielectric layer is used to insulate the gate electrode and the source electrode;

[0012] A drain electrode is located on the second surface. Optionally, the gate dielectric layer comprises a ferroelectric thin film gate dielectric layer.

[0013] Optionally, the material of the gate dielectric layer includes at least one of barium titanate (BT), lead titanate (PT), lead zirconate titanate (PZT), barium strontium titanate (BST) and lead magnesium niobate-lead titanate (PMN-PT).

[0014] Optionally, the gate structure includes a trench gate structure;

[0015] The first surface is provided with a first groove;

[0016] The gate dielectric layer is located at the bottom and sidewalls of the first groove;

[0017] The gate is located at a side of the gate dielectric layer away from the semiconductor body;

[0018] The interlayer dielectric layer is located on a side of the gate away from the gate dielectric layer.

[0019] Optionally, the source electrode comprises a trench structure;

[0020] The first surface is provided with a second groove;

[0021] The source electrode extends from the first surface into the second groove.

[0022] Optionally, the gate structure comprises a planar gate structure;

[0023] The gate dielectric layer is located on the first surface;

[0024] The gate is located on a side of the gate dielectric layer away from the first surface;

[0025] The interlayer dielectric layer is located on a side of the gate away from the gate dielectric layer.

[0026] Optionally, the source electrode comprises a planar source electrode structure;

[0027] The source is disposed on the first surface.

[0028] According to another aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0029] A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the semiconductor body comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is arranged on the first surface, and the first epitaxial layer is used to support the second epitaxial layer; the conductivity type of the second epitaxial layer is opposite to the conductivity type of the first epitaxial layer; the semiconductor body comprises a silicon carbide material; or the semiconductor body comprises a gallium nitride material; the second epitaxial layer comprises a well region, and the conductivity type and doping concentration of the well region and the second epitaxial layer are the same;

[0030] forming a first region in the second epitaxial layer, the first region being located on the first surface, the first region and the well region having opposite conductivity types, and the well region being arranged on a side of the first region away from the first surface;

[0031] A gate structure is formed on the first surface, the gate structure comprising a gate dielectric layer, a gate and an interlayer dielectric layer; the gate structure is located on the first surface, or the gate structure extends from the first surface into the semiconductor body; the gate dielectric layer is used to insulate the gate and the semiconductor body; the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer is a negative value, and the gate dielectric layer has a spontaneous polarization characteristic;

[0032] A source electrode is formed on the first surface, the source electrode is located on the first surface, or the source electrode extends from the first surface into the semiconductor body; the interlayer dielectric layer is used to insulate the gate electrode and the source electrode;

[0033] A drain electrode is formed on the second surface.

[0034] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0035] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0036] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0037] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any of the embodiments of the present invention, wherein the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0038] The semiconductor device and preparation method, power module, power conversion circuit and vehicle provided by the embodiment of the present invention, the gate structure in the semiconductor device includes a gate dielectric layer, the dielectric capacitance of the gate dielectric layer is negative, the dielectric capacitance and the metal-oxide-semiconductor capacitance caused by the interlayer dielectric layer are connected in series, the internal gate voltage is increased, and the subthreshold swing is reduced, and the subthreshold swing can even be reduced to 60mV·dec -1 Below this, the Boltzmann limit of 60mV·dec is reached. -1 Since the subthreshold swing is a performance indicator for measuring the conversion rate between the transistor on and the associated state, the smaller the subthreshold swing, the faster the MOSFET semiconductor device turns on or off. Therefore, the above technical solution improves the switching speed of the semiconductor device.

[0039] Among them, the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, which better realizes the electrical insulation between the gate and the semiconductor body, improves the carrier transport control capability of the semiconductor device, and thus helps to reduce the leakage current.

[0040] Moreover, the gate dielectric layer has a spontaneous polarization characteristic. After the gate control voltage is removed, due to the spontaneous polarization characteristic of the gate dielectric layer, there is still a residual polarization field that can have a stabilizing effect in the silicon carbide or gallium nitride semiconductor channel. As a gate dielectric layer, it can play the role of a floating gate by utilizing the electrostatic field effect. When the semiconductor device is working, there is no need for an epitaxial gate control voltage input, so the channel carrier concentration can be effectively regulated, and the device power consumption can be significantly suppressed, especially helping to deeply deplete the carriers in the silicon carbide or gallium nitride semiconductor channel and reduce leakage current.

[0041] Furthermore, the conductivity type of the second epitaxial layer is opposite to that of the first epitaxial layer, and the conductivity type and doping concentration of the second epitaxial layer and the well region are equal, so the first epitaxial layer and the second epitaxial layer constitute a stacked PN junction, and the formation of the well region does not require the first epitaxial layer to be formed through an ion implantation process, thereby avoiding the ion implantation process from causing lattice defects in the first epitaxial layer, reducing the possibility of defects in the MOSFET semiconductor device, improving the electrical performance of the MOSFET semiconductor device, and improving the reliability of the MOSFET semiconductor device.

[0042] In addition, the MOSFET semiconductor device provided in the embodiment of the present invention is a silicon carbide MOSFET semiconductor device or a gallium nitride MOSFET semiconductor device, which has the advantages of high withstand voltage, low on-resistance and high frequency, and can further improve the performance of the semiconductor device.

[0043] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 5-Figure 12 It is a structural schematic diagram corresponding to each step of a method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] In order to improve the switching speed and device reliability of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0053] like Figure 1 As shown, Figure 1 1 is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 001, comprising a first surface 002 and a second surface 003 arranged opposite to each other; the semiconductor body 001 comprises a first epitaxial layer 101 and a second epitaxial layer 102; the second epitaxial layer 102 is arranged on the first surface 002, and the first epitaxial layer 101 is used to support the second epitaxial layer 102; the conductivity type of the second epitaxial layer 102 is opposite to the conductivity type of the first epitaxial layer 101; the semiconductor body 001 comprises a silicon carbide material; or, the semiconductor body 001 comprises a gallium nitride material; the second epitaxial layer 102 comprises a well region 103 and a first region 112, the conductivity type and doping concentration of the well region 103 and the second epitaxial layer 102 are the same; the first region 112 is arranged on the first surface 002; the conductivity types of the first region 112 and the well region 103 are opposite , the well region 103 is arranged on the side of the first region 112 away from the first surface 002; the gate structure 105, the gate structure 105 includes a gate dielectric layer 106, a gate 107 and an interlayer dielectric layer 108; the gate structure 105 is located on the first surface 002, or the gate structure 105 extends from the first surface 002 to the semiconductor body 001; the gate dielectric layer 106 is used to insulate the gate 107 and the semiconductor body 001; the dielectric constant of the gate dielectric layer 106 is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer 106 is negative, and the gate dielectric layer 106 has a spontaneous polarization characteristic; the source 109, the source 109 is located on the first surface 002, or the source 109 extends from the first surface 002 to the semiconductor body 001; the interlayer dielectric layer 108 is used for the gate 107 and the source 109; the drain 110, the drain is located on the second surface 003.

[0054] For example, Figure 1As shown, the semiconductor body 001 includes a substrate 10, a first epitaxial layer 101 and a second epitaxial layer 102. In some embodiments of the present invention, the semiconductor body 001 may also include only the first epitaxial layer 101 and the second epitaxial layer 102. The first epitaxial layer 101 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 100. The second epitaxial layer 102 is a semiconductor layer formed by a single epitaxial process on the basis of the first epitaxial layer 101. The epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE).

[0055] In other embodiments, the semiconductor body 001 may further include a second region 111, the conductivity type of the second region 111 is opposite to the conductivity type of the first region 112, and the doping concentration of the second region 111 is greater than the doping concentration of the well region 103. The provision of the second region 111 can better achieve ohmic contact between the source 109 and the semiconductor body 001.

[0056] As typical third-generation wide bandgap semiconductor materials, silicon carbide materials or gallium nitride materials have excellent characteristics such as high critical breakdown electric field, wide bandgap, high thermal conductivity and high electron saturation drift velocity. When silicon carbide materials or gallium nitride materials are used as channel materials for MOSFET semiconductor devices, the devices exhibit advantages such as high breakdown voltage, low on-resistance, high current density, high heat dissipation and high switching speed. Among them, the critical breakdown electric field of silicon carbide materials is nearly 10 times that of silicon materials, the bandgap of silicon carbide materials is nearly 3 times that of silicon materials, and the thermal conductivity of silicon carbide materials is nearly 3 times that of silicon materials. In summary, silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0057] In the MOSFET semiconductor device provided by the embodiment of the present invention, the gate structure 105 includes a gate dielectric layer 106. The dielectric capacitance of the gate dielectric layer 106 is negative. The dielectric capacitance is connected in series with the metal-oxide-semiconductor capacitance caused by the interlayer dielectric layer 108, thereby increasing the internal gate voltage and reducing the subthreshold swing, and can even reduce the subthreshold swing to 60mV·dec. -1 Below this, the Boltzmann limit of 60mV·dec is reached. -1 Since the subthreshold swing is a performance indicator for measuring the conversion rate between the transistor on and the associated state, the smaller the subthreshold swing, the faster the MOSFET semiconductor device turns on or off. Therefore, the above technical solution improves the switching speed of the semiconductor device.

[0058] The dielectric constant of the gate dielectric layer 106 is greater than that of silicon oxide, which better achieves electrical insulation between the gate 107 and the semiconductor body 001, improves the carrier transport control capability of the semiconductor device, and thus helps reduce leakage current.

[0059] In addition, the gate dielectric layer 106 has a spontaneous polarization characteristic. After the gate control voltage is removed, due to the spontaneous polarization characteristic of the gate dielectric layer 106, there is still a residual polarization field that can stably act in the silicon carbide or gallium nitride semiconductor channel. As a gate dielectric layer, it can play the role of a floating gate by utilizing the electrostatic field effect. When the semiconductor device is working, there is no need for an epitaxial gate control voltage input, so the channel carrier concentration can be effectively regulated, and the device power consumption can be significantly suppressed, especially helping to deeply deplete the carriers in the silicon carbide or gallium nitride semiconductor channel and reduce leakage current.

[0060] Furthermore, the conductivity type of the second epitaxial layer 102 is opposite to that of the first epitaxial layer 101, and the conductivity type and doping concentration of the second epitaxial layer 102 and the well region 103 are equal, so the first epitaxial layer 101 and the second epitaxial layer 102 form a stacked PN junction, and the formation of the well region 103 does not require the first epitaxial layer 101 to be formed by an ion implantation process, thereby avoiding the ion implantation process from causing lattice defects in the first epitaxial layer 101, reducing the possibility of defects in the MOSFET semiconductor device, improving the electrical performance of the MOSFET semiconductor device, and improving the reliability of the MOSFET semiconductor device. In addition, the MOSFET semiconductor device provided in the embodiment of the present invention is a silicon carbide MOSFET semiconductor device or a gallium nitride MOSFET semiconductor device, which has the advantages of high withstand voltage, low on-resistance and high frequency, and can further improve the performance of the semiconductor device.

[0061] Optionally, based on the above technical solution, the gate dielectric layer 106 includes a ferroelectric thin film gate dielectric layer.

[0062] Specifically, the ferroelectric thin film gate dielectric layer will introduce a ferroelectric dielectric capacitor, which is a negative value. The ferroelectric dielectric capacitor is connected in series with the metal-oxide-semiconductor capacitor caused by the interlayer dielectric layer 108, increasing the internal gate voltage, thereby reducing the subthreshold swing, and further increasing the switching speed of the semiconductor device.

[0063] Among them, the dielectric constant of the ferroelectric thin film gate dielectric layer can reach 10 3 Farad / meter, which is greater than the dielectric constant of silicon oxide, better achieves electrical insulation between the gate 107 and the second epitaxial layer 102, improves the carrier transport control capability of the semiconductor device, and thus helps to reduce leakage current.

[0064] Moreover, the ferroelectric thin film gate dielectric layer has a spontaneous polarization characteristic. After the gate control voltage is removed, due to the spontaneous polarization characteristic of the ferroelectric thin film gate dielectric layer, there is still a residual polarization field that can stably act in the silicon carbide or gallium nitride semiconductor channel. As a gate dielectric layer, it can play the role of a floating gate using the electrostatic field effect. When the semiconductor device is working, there is no need for an epitaxial gate control voltage input, so the channel carrier concentration can be effectively regulated, and the device power consumption can be significantly suppressed, especially helping to deeply deplete the carriers in the silicon carbide or gallium nitride semiconductor channel and reduce leakage current.

[0065] Optionally, based on the above technical solution, the material of the gate dielectric layer 106 includes at least one of barium titanate (BT), lead titanate (PT), lead zirconate titanate (PZT), barium strontium titanate (BST) and lead magnesium niobate-lead titanate (PMN-PT), and the above materials all belong to ferroelectric thin film gate dielectric layers.

[0066] The MOSFET semiconductor device provided by the embodiment of the present invention is applicable to a planar MOSFET semiconductor device, a single trench MOSFET semiconductor device, and a double trench MOSFET semiconductor device.

[0067] like Figure 2 As shown, Figure 2 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. The semiconductor device is a planar MOSFET semiconductor device, and the gate structure 105 includes a planar gate structure. The source 109 includes a planar source structure. Among them, the gate dielectric layer 106 is located on the first surface 002; the gate 107 is located on the side of the gate dielectric layer 106 away from the first surface 002; and the interlayer dielectric layer 108 is located on the side of the gate 107 away from the gate dielectric layer 106. The source 109 is arranged on the first surface 002.

[0068] like Figure 1 As shown, the semiconductor device is a single trench MOSFET semiconductor device, the gate structure 105 includes a trench gate structure; the first surface 002 is provided with a first groove; the gate dielectric layer 106 is located at the bottom and sidewall of the first groove; the gate 107 is located on the side of the gate dielectric layer 106 away from the semiconductor body 001; the interlayer dielectric layer 108 is located on the side of the gate 107 away from the gate dielectric layer 106. The source 109 includes a planar source structure, and the source 109 is provided on the first surface 002. The provision of the trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance.

[0069] like Figure 3 As shown, Figure 31 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. The semiconductor device is a double trench MOSFET semiconductor device, wherein the gate structure 105 includes a trench gate structure; a first groove is provided on the first surface 002; a gate dielectric layer 106 is located at the bottom and sidewall of the first groove; a gate 107 is located on the side of the gate dielectric layer 106 away from the semiconductor body 001; and an interlayer dielectric layer 108 is located on the side of the gate 107 away from the gate dielectric layer 106. The source 109 includes a trench source structure; a second groove is provided on the second surface 003; and the source 109 extends from the first surface 002 into the second groove. The trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance. In the trench source structure, the second region 111 below the source 109 and the drift region of the first epitaxial layer 101 constitute a depletion layer, which can effectively alleviate the electric field distribution below the gate dielectric layer 106.

[0070] The present invention also provides a method for manufacturing a semiconductor device. Figure 4 As shown, Figure 4 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, Figure 1 Taking the semiconductor device shown as an example, the method for preparing the semiconductor device includes the following steps:

[0071] S110. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body comprising a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is arranged on the first surface, and the first epitaxial layer is used to support the second epitaxial layer; the conductivity type of the second epitaxial layer is opposite to the conductivity type of the first epitaxial layer; the semiconductor body comprises silicon carbide material; or, the semiconductor body comprises gallium nitride material; the second epitaxial layer comprises a well region, and the well region and the second epitaxial layer have the same conductivity type.

[0072] like Figure 1 As shown, the semiconductor body 001 includes a substrate 10, a first epitaxial layer 101 and a second epitaxial layer 102. In some embodiments of the present invention, the semiconductor body 001 may also include only the first epitaxial layer 101 and the second epitaxial layer 102. The first epitaxial layer 101 is a semiconductor layer formed by a single epitaxial process on the basis of the substrate 100. The second epitaxial layer 102 is a semiconductor layer formed by a single epitaxial process on the basis of the first epitaxial layer 101. The epitaxial process includes processes such as chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE).

[0073] Exemplarily, when the semiconductor body 001 includes a substrate 10, a first epitaxial layer 101, and a second epitaxial layer 102, providing the semiconductor body 001 includes the following steps:

[0074] like Figure 5As shown, a substrate 100 is provided. The substrate 100 includes a silicon carbide material or a gallium nitride material. When the MOSFET semiconductor device is an N-channel MOSFET semiconductor device, the substrate 100 may be an N+ substrate. When the MOSFET semiconductor device is a P-channel MOSFET semiconductor device, the substrate 100 may be a P+ substrate.

[0075] like Figure 5 As shown, a first epitaxial layer 101 is formed on one side of a substrate 100 by an epitaxial growth process. When the MOSFET semiconductor device is an N-channel MOSFET semiconductor device, the first epitaxial layer 101 may be an N-epitaxial layer. When the MOSFET semiconductor device is a P-channel MOSFET semiconductor device, the first epitaxial layer 101 may be a P-epitaxial layer. The first epitaxial layer 101 includes a silicon carbide material or a gallium nitride material.

[0076] like Figure 6 As shown, a second epitaxial layer 102 is formed on a side of the first epitaxial layer 101 away from the substrate 100 by an epitaxial growth process, wherein the conductivity type of the second epitaxial layer 102 is opposite to that of the first epitaxial layer 101 .

[0077] When the MOSFET semiconductor device is an N-channel MOSFET semiconductor device, the second epitaxial layer 102 may be a P-epitaxial layer. When the MOSFET semiconductor device is a P-channel MOSFET semiconductor device, the second epitaxial layer 102 may be an N-epitaxial layer. The second epitaxial layer 102 includes silicon carbide material or gallium nitride material.

[0078] S120, forming a first region in the second epitaxial layer, the first region being located on the first surface, the first region and the well region having opposite conductivity types, and the well region being arranged on a side of the first region away from the first surface.

[0079] The process of forming the first region 112 on the side of the second epitaxial layer 102 away from the first epitaxial layer 101 by the heavily doped high temperature ion implantation process is as follows:

[0080] like Figure 7 As shown, the second region 111 is formed in the second epitaxial layer 102 by a heavily doped high temperature ion implantation process. Figure 8As shown, a first region 112 is formed in the second epitaxial layer 102 by a heavily doped high temperature ion implantation process. The second epitaxial layer 102 includes a well region 103, a first region 112, and a second region 111. The well region 103 and the second epitaxial layer 102 have the same conductivity type and doping concentration; the second epitaxial layer 102 except the first region 112 and the second region 111 is the well region 103. The first region 112 is provided to achieve good ohmic contact between the source 109 and the semiconductor body 001. The second region 111 can better achieve ohmic contact between the source 109 and the semiconductor body 001.

[0081] Specifically, when the MOSFET semiconductor device is an N-channel MOSFET semiconductor device, the well region 103 may be a P-well region, the second region 111 may be a P+ region, and the first region 112 may be an N+ region. When the MOSFET semiconductor device is a P-channel MOSFET semiconductor device, the well region 103 may be an N-well region, the second region 111 may be an N+ region, and the first region 112 may be a P+ region.

[0082] It should be noted that, in other embodiments, the semiconductor body 001 may also include only the first region 112 .

[0083] Specifically, the conductivity type of the second epitaxial layer 102 is opposite to the conductivity type of the first epitaxial layer 101, and the conductivity type and doping concentration of the second epitaxial layer 102 are the same as the well region 103, so the first epitaxial layer 101 and the second epitaxial layer 102 form a stacked PN junction, and the formation of the well region 103 does not require the first epitaxial layer 101 to be formed through an ion implantation process, thereby avoiding the ion implantation process from causing lattice defects in the first epitaxial layer 101, reducing the possibility of defects in the MOSFET semiconductor device, improving the electrical performance of the MOSFET semiconductor device, and improving the reliability of the MOSFET semiconductor device.

[0084] S130, forming a gate structure on the first surface, the gate structure comprising a gate dielectric layer, a gate and an interlayer dielectric layer; the gate structure is located on the first surface, or the gate structure extends from the first surface into the semiconductor body; the gate dielectric layer is used to insulate the gate and the semiconductor body; the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer is a negative value, and the gate dielectric layer has a spontaneous polarization characteristic;

[0085] Here, Figure 1 Taking the single trench MOSFET semiconductor device shown as an example, the gate structure 105 extends from the first surface 002 into the semiconductor body 001. The process of forming the gate structure 105 on the first surface 002 is as follows:

[0086] like Fig. 9As shown, a first groove T1 is formed on the first surface 002. Fig.10 As shown, a gate dielectric layer 106 is formed at the bottom and sidewalls of the first groove T1 through a deposition process. The dielectric constant of the gate dielectric layer 106 is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer 106 is negative, and the gate dielectric layer 106 has a spontaneous polarization characteristic. Fig.11 As shown, a gate 107 is formed on a side of the gate dielectric layer 106 away from the semiconductor body 001. Fig.12 As shown, an interlayer dielectric layer 108 is formed on a side of the gate 107 away from the gate dielectric layer 106 . Figure 3 The preparation process of the gate structure 105 in the double trench MOSFET semiconductor device shown can be referred to Figure 9-12 The arrangement of the trench gate structure can effectively suppress the JFET effect and further reduce the on-resistance.

[0087] Figure 2 The manufacturing process of the gate structure 105 in the planar MOSFET semiconductor device shown does not require forming the first groove T1 on the first surface 002 .

[0088] The gate 107 is made of polysilicon material.

[0089] S140, forming a source electrode on the first surface, the source electrode is located on the first surface, or the source electrode extends from the first surface into the semiconductor body; the interlayer dielectric layer is used to insulate the gate and the source electrode.

[0090] by Figure 1 The single trench MOSFET semiconductor device shown is used as an example for explanation. Figure 1 As shown, a source 109 is formed on the first surface 002 , and the source 109 is a planar source structure.

[0091] Figure 3 The source 109 in the double trench MOSFET semiconductor device shown is a trench source structure, and a second groove needs to be formed on the first surface 002, and then the source 109 is formed in the second groove. In the trench source structure, the second region 111 below the source 109 and the drift region of the first epitaxial layer 101 constitute a depletion layer, which can effectively alleviate the electric field distribution below the gate dielectric layer 106.

[0092] Figure 2 In the planar MOSFET semiconductor device shown, the source 109 is a planar source structure, and there is no need to form a second groove on the first surface 002 for placing the source 109 .

[0093] S150, forming a drain on the second surface.

[0094] like Figure 1As shown, the drain 110 is formed on the second surface 003 by a film forming process. Exemplarily, in this embodiment, the second surface 003 is a surface of the substrate 100 away from the first epitaxial layer 101.

[0095] In the MOSFET semiconductor device prepared in the embodiment of the present invention, the gate structure 105 includes a gate dielectric layer 106. The dielectric capacitance of the gate dielectric layer 106 is negative. The dielectric capacitance is connected in series with the metal-oxide-semiconductor capacitance caused by the interlayer dielectric layer 108, thereby increasing the internal gate voltage and reducing the subthreshold swing, and even reducing the subthreshold swing to 60mV·dec -1 Below this, the Boltzmann limit of 60mV·dec is reached. -1 Since the subthreshold swing is a performance indicator for measuring the conversion rate between the transistor on and the associated state, the smaller the subthreshold swing, the faster the MOSFET semiconductor device turns on or off. Therefore, the above technical solution improves the switching speed of the semiconductor device.

[0096] The dielectric constant of the gate dielectric layer 106 is greater than that of silicon oxide, which better achieves electrical insulation between the gate 107 and the semiconductor body 001, improves the carrier transport control capability of the semiconductor device, and thus helps reduce leakage current.

[0097] In addition, the gate dielectric layer 106 has a spontaneous polarization characteristic. After the gate control voltage is removed, due to the spontaneous polarization characteristic of the gate dielectric layer 106, there is still a residual polarization field that can stably act in the silicon carbide or gallium nitride semiconductor channel. As a gate dielectric layer, it can play the role of a floating gate by utilizing the electrostatic field effect. When the semiconductor device is working, there is no need for an epitaxial gate control voltage input, so the channel carrier concentration can be effectively regulated, and the device power consumption can be significantly suppressed, especially helping to deeply deplete the carriers in the silicon carbide or gallium nitride semiconductor channel and reduce leakage current.

[0098] Furthermore, the conductivity type of the second epitaxial layer 102 is opposite to the conductivity type of the first epitaxial layer 101, and the conductivity type and doping concentration of the second epitaxial layer 102 and the well region 103 are equal, so the first epitaxial layer 101 and the second epitaxial layer 102 constitute a stacked PN junction, and the formation of the well region 103 does not require the first epitaxial layer 101 to be formed through an ion implantation process, thereby avoiding the ion implantation process from causing lattice defects in the first epitaxial layer 101, reducing the possibility of defects in the MOSFET semiconductor device, improving the electrical performance of the MOSFET semiconductor device, and improving the reliability of the MOSFET semiconductor device.

[0099] Optionally, based on the above technical solution, the gate dielectric layer 106 includes a ferroelectric thin film gate dielectric layer.

[0100] Specifically, the ferroelectric thin film gate dielectric layer will introduce a ferroelectric dielectric capacitor, which is a negative value. The ferroelectric dielectric capacitor is connected in series with the metal-oxide-semiconductor capacitor caused by the interlayer dielectric layer 108, increasing the internal gate voltage, thereby reducing the subthreshold swing, and further increasing the switching speed of the semiconductor device.

[0101] Among them, the dielectric constant of the ferroelectric thin film gate dielectric layer can reach 10 3 Farad / meter, which is greater than the dielectric constant of silicon oxide, better achieves electrical insulation between the gate 107 and the second epitaxial layer 102, improves the carrier transport control capability of the semiconductor device, and thus helps to reduce leakage current.

[0102] Moreover, the ferroelectric thin film gate dielectric layer has a spontaneous polarization characteristic. After the gate control voltage is removed, due to the spontaneous polarization characteristic of the ferroelectric thin film gate dielectric layer, there is still a residual polarization field that can stably act in the silicon carbide or gallium nitride semiconductor channel. As a gate dielectric layer, it can play the role of a floating gate using the electrostatic field effect. When the semiconductor device is working, there is no need for an epitaxial gate control voltage input, so the channel carrier concentration can be effectively regulated, and the device power consumption can be significantly suppressed, especially helping to deeply deplete the carriers in the silicon carbide or gallium nitride semiconductor channel and reduce leakage current.

[0103] Optionally, based on the above technical solution, the material of the gate dielectric layer 106 includes at least one of barium titanate (BT), lead titanate (PT), lead zirconate titanate (PZT), barium strontium titanate (BST) and lead magnesium niobate-lead titanate (PMN-PT), and the above materials all belong to ferroelectric thin film gate dielectric layers.

[0104] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device as described in any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device as described in any embodiment of the present invention are not described in detail here.

[0105] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0106] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0107] The embodiment of the present invention further provides a vehicle, comprising a load and any power conversion circuit as in the embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention are not repeated here.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface arranged opposite to each other; The semiconductor body comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is arranged on the first surface, and the first epitaxial layer is used to support the second epitaxial layer; The conductivity type of the second epitaxial layer is opposite to the conductivity type of the first epitaxial layer; the semiconductor body comprises silicon carbide material; or the semiconductor body comprises gallium nitride material; The second epitaxial layer includes a well region and a first region, and the well region and the second epitaxial layer have the same conductivity type and doping concentration; The first region is arranged on the first surface, the first region and the well region have opposite conductivity types, and the well region is arranged on a side of the first region away from the first surface; A gate structure, wherein the gate structure comprises a gate dielectric layer, a gate and an interlayer dielectric layer; the gate structure is located on the first surface, or the gate structure extends from the first surface into the semiconductor body; the gate dielectric layer is used to insulate the gate and the semiconductor body; the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer is negative, and the gate dielectric layer has a spontaneous polarization characteristic; A source electrode, the source electrode is located on the first surface, or the source electrode extends from the first surface into the semiconductor body; The interlayer dielectric layer is used to insulate the gate and the source; A drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The gate dielectric layer comprises a ferroelectric thin film gate dielectric layer.

3. The semiconductor device according to claim 2, characterized in that The material of the gate dielectric layer includes at least one of barium titanate (BT), lead titanate (PT), lead zirconate titanate (PZT), barium strontium titanate (BST) and lead magnesium niobate-lead titanate (PMN-PT).

4. The semiconductor device according to claim 1, wherein: The gate structure comprises a trench gate structure; The first surface is provided with a first groove; The gate dielectric layer is located at the bottom and sidewalls of the first groove; The gate is located at a side of the gate dielectric layer away from the semiconductor body; The interlayer dielectric layer is located on a side of the gate away from the gate dielectric layer.

5. The semiconductor device according to claim 4, characterized in that The source electrode comprises a trench structure; The first surface is provided with a second groove; The source electrode extends from the first surface into the second groove.

6. The semiconductor device according to claim 1, wherein: The gate structure comprises a planar gate structure; The gate dielectric layer is located on the first surface; The gate is located on a side of the gate dielectric layer away from the first surface; The interlayer dielectric layer is located on a side of the gate away from the gate dielectric layer.

7. The semiconductor device according to claim 4 or 6, characterized in that: The source electrode comprises a planar source electrode structure; The source is disposed on the first surface.

8. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the semiconductor body comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer is arranged on the first surface, and the first epitaxial layer is used to support the second epitaxial layer; the conductivity type of the second epitaxial layer is opposite to the conductivity type of the first epitaxial layer; the semiconductor body comprises a silicon carbide material; or the semiconductor body comprises a gallium nitride material; the second epitaxial layer comprises a well region, and the conductivity type and doping concentration of the well region and the second epitaxial layer are the same; forming a first region in the second epitaxial layer, the first region being located on the first surface, the first region and the well region having opposite conductivity types, and the well region being arranged on a side of the first region away from the first surface; A gate structure is formed on the first surface, the gate structure comprising a gate dielectric layer, a gate and an interlayer dielectric layer; the gate structure is located on the first surface, or the gate structure extends from the first surface into the semiconductor body; the gate dielectric layer is used to insulate the gate and the semiconductor body; the dielectric constant of the gate dielectric layer is greater than the dielectric constant of silicon oxide, the dielectric capacitance of the gate dielectric layer is a negative value, and the gate dielectric layer has a spontaneous polarization characteristic; forming a source electrode on the first surface, wherein the source electrode is located on the first surface, or the source electrode extends from the first surface into the semiconductor body; The interlayer dielectric layer is used to insulate the gate and the source; A drain electrode is formed on the second surface.

9. A power module, characterized in that: It comprises a substrate and at least one semiconductor device as claimed in any one of claims 1 to 7, wherein the substrate is used for carrying the semiconductor device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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