Test method and device of timing module, electronic equipment and readable medium

Abstract

The embodiment of the invention provides a testing method and device of a timing module, electronic equipment and a readable medium, and relates to the technical field of integrated circuits, in the method, based on a scanning mode configuration vector in a preset testing file and a setting vector used for setting a timing initial value, a chip to be tested is controlled to convert the value of a timing function register into a timing function register; the timing initial value indicated by the setting vector is set. And inputting timing information to the to-be-tested chip so as to control the to-be-tested timing module to start timing operation from the timing initial value of the timing function register according to the timing information. And controlling the to-be-tested chip to move out of an actual timing result corresponding to the timing function register based on the post-timing shift mode configuration vector in the preset test file. And generating a function test result for the to-be-tested timing module according to the actual timing result and an expected timing result corresponding to the timing information. The automatic test of the timing function of the timing module can be realized based on the universal ATE, and the test cost required for testing the timing function can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a testing method, device, electronic equipment and readable medium for a timing module. Background Art

[0002] As chip design becomes more and more complex, the number of functions that can be integrated into a chip is also increasing. Among them, the timing function is a basic function, and the integration of a timing module with a timing function on the chip has become a basic requirement for chip design. Basically, a timing module is integrated in each chip. Accordingly, how to test the timing function of the timing module in the chip has become a widely concerned issue.

[0003] In the prior art, a board-level test method is often used to test the timing function of the timing module in the chip using a development board, system software and test program in a pre-configured development environment. In this method, a development environment needs to be set up specifically for the chip, and the testing cost is high. Summary of the invention

[0004] The embodiments of the present invention provide a testing method, device, electronic device and readable medium for a timing module, which can reduce the testing cost.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a method for testing a timing module, which is applied to an automatic test machine ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, and a timing function register in the timing module to be tested supports a scan test. The method comprises:

[0006] Based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value, control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector;

[0007] Inputting timing information to the chip to be tested, so as to control the timing module to be tested to perform timing operation starting from the timing initial value of the timing function register according to the timing information;

[0008] Based on the timing post-shift mode configuration vector in the preset test file, control the chip under test to shift out the actual timing result corresponding to the timing function register;

[0009] Based on the actual timing result and the expected timing result corresponding to the timing information, a functional test result is generated for the timing module to be tested.

[0010] On the other hand, an embodiment of the present invention discloses a test device for a timing module, which is applied to an automatic test machine ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, wherein a timing function register in the timing module to be tested supports a scan test, and the device comprises:

[0011] A first control module, configured to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on a scan mode configuration vector in a preset test file and a setting vector for setting the timing initial value;

[0012] A first input module, used for inputting timing information for the chip to be tested, so as to control the timing module to be tested to perform a timing operation starting from the timing initial value of the timing function register according to the timing information;

[0013] A second control module, configured to control the chip under test to shift out an actual timing result corresponding to the timing function register based on the timing post-shift mode configuration vector in the preset test file;

[0014] A generating module is used to generate a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information.

[0015] In yet another aspect, an embodiment of the present invention discloses an integrated circuit, the integrated circuit comprising a timing module, the timing function registers in the timing module are scan registers, and the timing function registers constitute a scan chain;

[0016] In response to a first control operation of the ATE, the value of the timing function register is set to the timing initial value indicated by the setting vector; the first control operation is a control operation performed by the ATE based on the scan mode configuration vector in the preset test file and the setting vector;

[0017] The timing module is used to respond to the input timing information and perform a timing operation starting from the timing initial value of the timing function register according to the timing information;

[0018] In response to a second control operation of the ATE, an actual timing result corresponding to the timing function register is shifted out so that the ATE can generate a functional test result for the timing module based on the actual timing result and an expected timing result corresponding to the timing information; the second control operation is a control operation performed by the ATE based on a timing post-shift mode configuration vector in the preset test file.

[0019] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0020] The embodiment of the present invention further discloses a machine-readable medium on which instructions are stored. When executed by one or more processors, the processors are enabled to execute the method described above.

[0021] The embodiment of the present invention has the following advantages: the test method of the timing module provided by the embodiment of the present invention is applied to an automatic test machine ATE, the ATE is loaded with a chip to be tested including a timing module to be tested, and the timing function register in the timing module to be tested supports scan testing. In the method, based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value, the chip to be tested is controlled to set the value of the timing function register to the timing initial value indicated by the setting vector. Then, the timing information is input for the chip to be tested to control the timing module to be tested to perform the timing operation from the timing initial value of the timing function register according to the timing information. Based on the timing post-shift mode configuration vector in the preset test file, the chip to be tested is controlled to shift out the actual timing result corresponding to the timing function register. Finally, based on the actual timing result and the expected timing result corresponding to the timing information, a functional test result is generated for the timing module to be tested. In this way, there is no need to specially configure a development environment for the chip to be tested, and the automatic test of the timing function of the timing module can be realized based on the general ATE. Therefore, the test cost required for testing the timing function can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0023] Figure 1 is a flowchart of a method for testing a timing module provided by an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a timing clock generation structure illustrated in an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of inputting a scan mode configuration vector provided by an embodiment of the present invention;

[0026] Figure 4is a schematic diagram of a configuration of a scan shift pattern provided by an embodiment of the present invention;

[0027] Figure 5 It is a schematic diagram of a configuration of scanning and capturing graphics provided by an embodiment of the present invention;

[0028] Figure 6 is a comparison schematic diagram provided by an embodiment of the present invention;

[0029] Figure 7 is a block diagram of a testing device for a timing module provided by an embodiment of the present invention;

[0030] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The timing module testing method provided in the embodiment of the present invention can be applied to chip testing scenarios. Specifically, it is applied to the scenario of testing the timing function of the timing module in the chip. At present, in the field of integrated circuit design and testing, integrating the timing function in the chip has become a basic requirement for chip design, and the timing function requires a special timing module to implement. Exemplarily, the timing module can be a real-time clock (RTC), a timer / counter, and the like. Therefore, the timing module is basically integrated in each chip, and accordingly, there is an increasing demand for testing the timing function of the timing module in the chip.

[0033] At present, the timing function test adopts the board-level test method. In this board-level test method, the chip needs to run on the development board to test the timing function of the timing module. Therefore, when testing the timing function at the factory, it is necessary to build an additional development environment that can run the normal chip function. Among them, the development environment includes hardware and software parts that ensure the normal operation of the chip. The hardware part includes the development board, and the software part includes a set of system software that allows the chip to run normally, as well as a test program for testing the timing function. It costs a lot to build an additional development environment for timing function testing. However, the timing module is used on almost all chips. Therefore, the board-level test method is not conducive to cost control, which will increase the screening cost of the chip and reduce the cost performance of the product.

[0034] And the board-level test method is generally divided into two modes: manual test and automatic test. Among them, the manual test method is used for debugging or small-scale screening, and the automatic test method is generally used for batch screening. In the manual test method, when the chip runs normally on the development board, while the timing module is timing, the tester needs to use a stopwatch to synchronize manual timing. In the manual test method, manual timing is required, and the labor cost is high. And the tester uses the result of manual timing by the stopwatch as a reference to measure whether the timing result obtained by the timing function of the chip is accurate. However, the manual timing error is large, and it is often the case that the chip with accurate timing function is judged as not passing the test, while the chip with inaccurate timing function is judged as passing the test. The test error is large and the test accuracy is low. In the automatic test method, it is necessary to prepare an additional test machine with accurate timing, and connect the test machine to the development board with a data cable. The test machine communicates with the development board to control the synchronous start / end timing of the chip on the development board. Finally, the timing result of the test machine is used as a reference to measure whether the timing result obtained by the timing function of the chip is accurate. The automatic testing method requires an additional testing machine, and the testing machine needs to be calibrated regularly to ensure the accuracy of the testing machine, which further increases the testing cost.

[0035] To this end, an embodiment of the present invention provides a test method for a timing module to reduce the test cost required for testing the timing function and at the same time ensure the accuracy of the timing function test. The test method is described in detail below.

[0036] Reference Figure 1 , shows a flowchart of a method for testing a timing module provided by an embodiment of the present invention, such as Figure 1 As shown, the method specifically comprises the following steps:

[0037] Step 101: Based on a scan mode configuration vector in a preset test file and a setting vector for setting a timing initial value, control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector.

[0038] Step 102: input timing information to the chip under test to control the timing module under test to perform timing operation starting from the timing initial value of the timing function register according to the timing information.

[0039] Step 103: Based on the post-timing shift mode configuration vector in the preset test file, control the chip under test to shift out the actual timing result corresponding to the timing function register.

[0040] Step 104: Generate a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information.

[0041] In an embodiment of the present invention, the test method can be applied to an automatic test equipment (ATE), wherein the ATE is loaded with a chip to be tested including a timing module to be tested, and the timing function register in the timing module to be tested supports scan testing. Among them, ATE as a test device can include an ATE machine, an ATE test board and a test socket. Among them, the test socket is used to fix the chip to be tested to ensure that the chip to be tested is correctly aligned with the probe on the ATE test board, and the ATE test board is used to connect the ATE machine and the chip to be tested so that the chip to be tested is loaded into the ATE. The ATE machine, as a host part, can be used to perform test functions.

[0042] Specifically, the test method provided by the embodiment of the present invention can be executed by an ATE machine. The chip to be tested can be any chip that needs to test the timing function of the timing module integrated in the chip, and the timing module to be tested refers to the timing module in the chip to be tested. The timing function register can be a group of registers with automatic counting function in the timing module, and the timing function register can also be called a timing register. The main functional components of the timing module include a reference clock generation circuit and a timing circuit. The reference clock generation circuit can correspond to an analog circuit, and the timing circuit can correspond to a digital circuit. Among them, the timing circuit includes a timing function register, and the timing function register can count the reference clock under specific control, thereby achieving the timing function. Exemplarily, Figure 2 is a schematic diagram of a timing clock generation structure according to an embodiment of the present invention. Figure 2 As shown, the reference clock can be directly input from the outside, for example, it can be input based on the external clock input pin CLK_EXT. Alternatively, CLK can also be generated by an internal reference clock generation circuit as a reference clock. Among them, VDD and VSS represent the power supply voltage and the ground voltage respectively.

[0043] Among them, the timing function register is designed based on the scan chain technology to facilitate automated testing. Scan chain is a typical technology for integrated circuit testability design. The timing function register supports scan testing, which means that the timing function register in the timing module to be tested adopts a scan register, so that the timing function register supports scan testing. Among them, the scan register has an SI input terminal, an SE input terminal, a D input terminal, a clock input terminal and an SO output terminal. The scan registers are connected in series based on the SO output terminal and the SI input terminal to form a chain structure, that is, a scan chain is formed. These scan registers can be configured and observed through the scan chain. The scan registers in the scan chain perform normal functions in normal mode, and perform scan shift (SE=1 at this time) and scan capture (SE=0 at this time) functions in scan mode.

[0044] Furthermore, the preset test file may be a test vector file pre-configured for the timing function test. The preset test file may include a variety of test vectors. Among them, the test vectors may also be referred to as test patterns, and the test patterns may be input into the chip through the chip pins (also referred to as chip pins), and the test patterns may be a set of 01 sequence waveforms. The scan mode configuration vector and the setting vector are two types of patterns in the timing function test pattern. The scan mode configuration vector may enable the chip under test to configure the working mode and enable the chip under test to enter the scan mode.

[0045] The setting vector may represent the timing initial value defined in the preset test file for this timing function test. The initial value may be included in the setting vector, and the specific value of the initial value may be set as needed based on the design requirements. For example, the initial value may be 0, or the initial value may be 1, which is not limited in the embodiment of the present invention. By setting the value of the timing function register to the timing initial value indicated by the setting vector, it is possible to control the timing function register to use the timing initial value as the starting value for subsequent timing.

[0046] In an embodiment of the present invention, the ATE machine can input a clock signal with a fixed number of beats as timing information for the chip to be tested according to a predefined fixed number of beats. The number of beats represents the number of clock cycles of the clock signal. Accordingly, the timing module to be tested can control the timing function register to count the number of beats of the timing information, thereby realizing the timing operation. Specifically, the timing function register can accumulate the count value of the clock signal with a fixed number of beats on the basis of the timing initial value. Accordingly, the counting result finally obtained by the timing function register, that is, the value of the timing function register can represent the timing result. Exemplarily, assuming that the initial value is 0, the clock cycle is 1 millisecond, and the fixed number of beats is 60, then after counting the clock signal with a fixed number of beats, a duration of 60 milliseconds can be obtained.

[0047] Among them, the post-timing shift mode configuration vector can make the scan chain composed of the timing function register enter the shift mode. In this way, the current value of the timing function register can be conveniently shifted out, and the shifted value can represent the actual timing result. The expected timing result corresponding to the timing information can represent the counting result of counting the timing information from the timing initial value, and the counting result can represent the expected timing result. The expected timing result itself can be in the form of a vector. Compared with the method of using the result of manual timing by the tester using a stopwatch as a reference, the preset expected timing result is used as a reference in the embodiment of the present invention, which can avoid the problem of large manual timing error and low test accuracy. Specifically, if the actual timing result is consistent with the expected timing result, it can be determined that the timing function of the timing module to be tested is normal. On the contrary, if the actual timing result is inconsistent with the expected timing result, it can be determined that the timing function of the timing module to be tested is abnormal. Therefore, a functional test result can be generated for the timing module to be tested based on the actual timing result and the expected timing result. Among them, the functional test result can indicate whether the timing function of the timing module to be tested is normal.

[0048] In summary, the test method of the timing module provided in the embodiment of the present invention is applied to an automatic test machine ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, and the timing function register in the timing module to be tested supports scan testing. In the method, based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value, the chip to be tested is controlled to set the value of the timing function register to the timing initial value indicated by the setting vector. Then, the timing information is input for the chip to be tested to control the timing module to be tested to perform the timing operation from the timing initial value of the timing function register according to the timing information. Based on the timing post-shift mode configuration vector in the preset test file, the chip to be tested is controlled to shift out the actual timing result corresponding to the timing function register. Finally, based on the actual timing result and the expected timing result corresponding to the timing information, a functional test result is generated for the timing module to be tested. In this way, there is no need to specially configure a development environment for the chip to be tested, and the automatic test of the timing function of the timing module can be realized based on the general ATE. Therefore, the test cost required for testing the timing function can be reduced.

[0049] Specifically, when the chip is screened before leaving the factory, ATE will be used for automatic testing. However, the existing ATE test mainly tests the correctness of the digital logic circuit in the chip. Therefore, the digital logic circuit in the timing module can be covered by the test, but the timing function cannot be tested. In the embodiment of the present invention. For the chip to be tested whose timing module to be tested supports scan testing, the mode configuration is performed based on ATE, so that various information required for the timing function test can be moved in or out for the timing module to be tested, thereby realizing the test of the timing function. Compared with the traditional test method that requires an additional development environment, the test process of the timing function of the timing module to be tested can be completed based on ATE. In this way, the chip with problems in the timing function can be accurately and quickly screened out based on ATE. It should be noted that in the test method provided by the embodiment of the present invention, the chip can be used as the chip to be tested after the chip passes other tests of ATE, thereby avoiding the problem of testing the timing function of the chip with problems in the digital logic circuit, resulting in the execution of unnecessary test operations, and then wasting test resources. Further, if the timing function is normal, it can be determined that the chip to be tested is a qualified product. On the contrary, if the timing function is abnormal, it can be determined that the chip to be tested is a defective product.

[0050] Optionally, the above-mentioned controlling the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value may specifically include:

[0051] Step 1011: Load the scan mode configuration vector from the preset test file, and input the scan mode configuration vector to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to respond to the mode configuration vector and enter the scan mode indicated by the mode configuration vector;

[0052] Step 1012, load the setting vector from the preset test file, and input the setting vector to the chip under test that enters the scan mode, so as to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector.

[0053] In an embodiment of the present invention, the scan mode configuration vector may also be referred to as a scan mode configuration graph. The preset test file may be stored locally in the ATE, and the ATE machine may load the scan mode configuration vector in the preset test file from the first designated storage location. The scan mode configuration vector may be used to instruct the chip to enter the scan mode. The configuration pin may be a pin provided by the chip under test for inputting the test graph, and there may be multiple configuration pins, wherein the configuration pin may be positively correlated with the total number of pins included in the chip under test. The scan mode configuration vector may be input into the chip under test based on the multiple configuration pins. For example, taking the case where there are m configuration pins in the chip under test, Figure 3 is a schematic diagram of inputting a scan mode configuration vector provided by an embodiment of the present invention, such as Figure 3 As shown, the scan mode configuration vector is Figure 3 The scan mode configuration graph in the figure, the scan mode configuration vector can be input to the chip under test based on the m configuration pins 1 to m. Accordingly, after receiving the input scan mode configuration vector, the chip under test will configure the working mode in response to the mode configuration vector. Specifically, the working mode is configured as the scan mode.

[0054] Furthermore, after the chip to be tested enters the scan mode, a timing function test can be performed in combination with a timing function register that supports the scan test. Specifically, a starting value can be set for the timing function register first. The ATE machine can load a setting vector in a preset test file from a second designated storage location. And the setting vector is input into the chip to be tested based on the scan input pin provided by the chip to be tested. Among them, the scan input pin can be the same as the above-mentioned configuration pin, or there can be a difference. The setting vector can be input into the chip to be tested based on these multiple scan input pins. Accordingly, after the chip to be tested receives the input setting vector, it will respond to the setting vector and execute the operation of setting the value of the timing function register to the timing initial value indicated by the setting vector.

[0055] In an embodiment of the present invention, a scan mode configuration vector is first loaded from a preset test file, and then the scan mode configuration vector is input to the chip to be tested through a configuration pin between the chip to be tested. In this way, the chip to be tested can be controlled to respond to the mode configuration vector and enter the scan mode indicated by the mode configuration vector. Next, a setting vector is loaded from a preset test file, and the setting vector is input to the chip to be tested that enters the scan mode, so that the chip to be tested can be controlled to set the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector. By sequentially loading and inputting the scan mode configuration vector and the setting vector to the chip to be tested, the value of the timing function register can be set to the timing initial value indicated by the setting vector, which can ensure the efficiency of setting the initial value in the timing function test link to a certain extent, and then ensure the overall test efficiency of the on-chip timing function test based on ATE.

[0056] Optionally, the embodiment of the present invention may further include:

[0057] Step S21, inputting a timing pre-shift mode configuration vector into the chip under test through a configuration pin between the chip under test, so as to control the chip under test to respond to the timing pre-shift mode configuration vector and control the scan chain composed of the timing function registers to enter a shift mode.

[0058] Correspondingly, the above-mentioned chip under test sets the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector, which may specifically include: the chip under test moves the timing initial value indicated by the setting vector into the timing function register based on the scan shift function corresponding to the shift pattern.

[0059] In an embodiment of the present invention, the ATE machine can load the timing pre-shift mode configuration vector in the preset test file from the third designated storage location. The timing pre-shift mode configuration vector can be used to instruct the chip to control SE=1 of the scan register when entering the scan mode, thereby making the scan chain composed of the timing function register enter the shift mode. Among them, the timing pre-shift mode configuration vector may include the configuration value of the configuration pin, and inputting the timing pre-shift mode configuration vector into the chip to be tested through the configuration pin is equivalent to configuring the value of the configuration pin according to the timing pre-shift mode configuration vector. Accordingly, by configuring the value of the configuration pin according to the timing pre-shift mode configuration vector, the chip to be tested controls SE=1 of the scan register, thereby controlling the scan chain composed of the timing function register to enter the shift mode. In the scan shift mode, the scan register is in the test mode, and at this time, data is input from the SI input terminal of the scan register.

[0060] Further, after the scan chain formed by the timing function register enters the shift mode, the chip under test can use the scan shift function in the shift mode to shift the timing initial value indicated by the received setting vector into the timing function register. Specifically, the chip under test can drive the initial value carried in the setting vector to shift to the timing function register along the scan chain formed by the timing function register by shifting in the clock signal. Each time the clock edge of the shifted-in clock signal arrives, the initial value can be driven to shift by one bit. The data in the setting vector can be shifted based on the shifted-in clock signal. In this way, one bit of data is shifted for each clock cycle of the shifted-in clock signal until the timing initial value is shifted into each timing function register. Among them, in the shift mode, each bit of data in the setting vector is shifted in sequentially through the SI input terminal, and the timing initial values ​​shifted into different timing function registers can be the same or different. The setting vector can be input to the chip under test based on the scan input pin, and the scan input pin and the configuration pin can be the same or different. Configuration pins of the input scan mode configuration vector, the pre-clocked shift mode configuration vector, the capture mode configuration vector, and the post-clocked shift mode configuration vector may be the same or different.

[0061] In the embodiment of the present invention, the timing initial value may also be referred to as an initialization value or a test initial value. The timing pre-shift mode configuration vector and the setting vector may be used as a scan shift vector 1, which may also be referred to as a scan shift graph 1, and the scan shift graph 1 is used to shift the test initial value. Figure 4 is a schematic diagram of a configuration of a scan shift pattern provided by an embodiment of the present invention, such as Figure 4 As shown, taking scan shift pattern 1 as an example, the timing pre-shift mode configuration vector in scan shift pattern 1 can control the chip under test to set SE = 1. The setting vector in scan shift pattern 1 can shift the timing initial value into the scan chain composed of the timing function registers in the chip under test.

[0062] Furthermore, the setting vector may also include an initial value of a control register. Accordingly, the initial value of the control register may be shifted into the control register based on a scan shift function corresponding to the shift mode. The control register may be connected to a scan chain formed by a timing function register. By setting the initial value of the control register, the timing module to be tested may be controlled, for example, the timing module to be tested may be controlled to be in an enabled state. Thus, after the timing information is input, the timing module to be tested may start the timing operation according to the timing information.

[0063] In the embodiment of the present invention, the pre-timing shift mode configuration vector is first input into the chip to be tested through the configuration pin between the chip to be tested, so as to control the chip to be tested to respond to the pre-timing shift mode configuration vector, and control the scan chain composed of the timing function register to enter the shift mode. Accordingly, after the setting vector is input into the chip to be tested that enters the scan mode, the chip to be tested shifts the timing initial value indicated by the setting vector into the timing function register based on the scan shift function corresponding to the shift mode. In this way, by loading and inputting the pre-timing shift mode configuration vector for the chip to be tested, the shift mode can be controlled to be entered, so that the chip to be tested can shift in the timing initial value based on the scan shift function corresponding to the shift mode, and the shifting efficiency of the timing initial value is high.

[0064] Optionally, the embodiment of the present invention may further include:

[0065] Step S31, loading a capture mode configuration vector from the preset test file, and inputting the capture mode configuration vector into the chip under test, so as to control the chip under test to respond to the capture mode configuration vector and control the scan chain composed of the timing function registers to enter the capture mode.

[0066] Correspondingly, the above-mentioned timing module to be tested performs timing operations according to the timing information starting from the timing initial value based on the timing function register, and specifically may include: the chip to be tested inputs the timing information into the timing function register based on the data input function corresponding to the capture mode, so that the timing function register starts timing according to the timing information starting from the timing initial value.

[0067] In an embodiment of the present invention, the capture mode configuration vector can be specifically used to control the scan chain to enter the scan capture mode. The capture mode configuration vector can also be called a scan capture graph. In the scan capture mode, the scan register is in the functional mode, and the data is input from the D input terminal of the scan register. The ATE machine can load the capture mode configuration vector in the preset test file from the fourth designated storage location. The capture mode configuration vector can be used to indicate that when the chip enters the scan mode, the SE of the scan register is controlled to be 0, thereby making the scan chain composed of the timing function register enter the capture mode. Among them, the capture mode configuration vector may include the configuration value of the configuration pin, and the capture mode configuration vector is input into the chip to be tested through the configuration pin, which is equivalent to configuring the value of the configuration pin according to the capture mode configuration vector. Accordingly, by configuring the value of the configuration pin according to the capture mode configuration vector, the chip to be tested controls the SE of the scan register to be 0, thereby controlling the scan chain composed of the timing function register to enter the capture mode. Figure 5 is a schematic diagram of a configuration of a scanning and capturing graphic provided by an embodiment of the present invention, such as Figure 5 As shown, the chip under test can be controlled to set SE=0 based on the scan capture pattern.

[0068] Further, after the scan chain composed of the timing function register enters the capture mode, the chip under test can input the timing information based on the data input function in the capture mode. Exemplarily, the timing information can be input through CLK_EXT. The data input function in the capture mode can refer to the scan register using the D input terminal to input data normally. Specifically, for the timing function register, the timing function register counts the input information in the capture mode, specifically, counts each clock signal input, so as to realize the timing function of the timing module under test.

[0069] In an embodiment of the present invention, a capture mode configuration vector is first loaded from a preset test file, and the capture mode configuration vector is input into the chip to be tested, so as to control the chip to be tested to respond to the capture mode configuration vector, and control the scan chain composed of the timing function register to enter the capture mode. Accordingly, after the timing information is input into the chip to be tested, the chip to be tested inputs the timing information into the timing function register based on the data input function corresponding to the capture mode, so that the timing function register can start timing from the timing initial value according to the timing information. In this way, by loading and inputting the capture mode configuration vector for the chip to be tested, it is possible to control the entry into the capture mode, so that the timing function register in the chip to be tested starts to count the timing information, thereby realizing timing, and conveniently realizing the timing module to be tested based on ATE to perform timing according to the pre-configured timing information, thereby ensuring the convenience of the test method.

[0070] Optionally, in an embodiment of the present invention, the above-mentioned controlling the chip under test to shift out the actual timing result corresponding to the timing function register based on the timing post-shift mode configuration vector in the preset test file may specifically include:

[0071] Step 1031: Load the timing post-shift mode configuration vector from the preset test file, and input the timing post-shift mode configuration vector to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to perform the following operations:

[0072] In response to the post-timing shift mode configuration vector, the chip under test controls the scan chain composed of the timing function register to enter a shift mode; the chip under test shifts out the current value of the timing function register based on the scan shift function corresponding to the shift mode; the chip under test determines the actual timing result based on the shifted current value, and outputs the actual timing result to the ATE.

[0073] In an embodiment of the present invention, the post-timing shift mode configuration vector can be used as the scan shift pattern 2. The ATE machine can load the post-timing shift mode configuration vector in the preset test file from the fifth designated storage location. Among them, the post-timing shift mode configuration vector and the pre-timing shift mode configuration vector can be used to indicate that the chip controls the SE=1 of the scan register after timing and the SE=1 of the scan register before timing, respectively. In an embodiment of the present invention, the ATE can define the use time of the post-timing shift mode configuration vector and the pre-timing shift mode configuration vector in the internal test program, and the ATE can run the test program to execute the above test method.

[0074] Specifically, after the timing operation is completed, the SE of the chip control scan register can be controlled to be 1 through the timing post-shift mode configuration vector, thereby making the scan chain composed of the timing function register enter the shift mode. Among them, the timing post-shift mode configuration vector can include the configuration value of the configuration pin, and the timing post-shift mode configuration vector is input into the chip under test through the configuration pin, which is equivalent to configuring the value of the configuration pin according to the timing post-shift mode configuration vector. Accordingly, by configuring the value of the configuration pin according to the timing post-shift mode configuration vector, the SE of the chip control scan register under test is made to be 1, so as to realize the control of the scan chain composed of the timing function register to enter the shift mode.

[0075] Further, after the scan chain formed by the timing function register enters the shift mode, the chip to be tested can use the scan shift function in the shift mode. Specifically, the chip to be tested can drive the current value of the timing function register to be shifted out along the scan chain formed by the timing function register by shifting out the clock signal. Each time the clock edge of the shift-out clock signal arrives, the current value can be driven to shift out one bit sequentially. One bit of data is shifted out in each clock cycle of the shift-out clock signal until the current values ​​of all timing function registers are shifted out. Further, the chip to be tested can directly use the shifted out current value as the actual timing result. Alternatively, a numerical value representing the duration can be obtained based on the shifted out current value as the actual timing result. Finally, the actual timing result can be output to ATE based on the scan output pin. Among them, the scan output port can be a port for outputting the actual timing result to ATE.

[0076] In an embodiment of the present invention, a timing post-shift mode configuration vector is first loaded from a preset test file, and the timing post-shift mode configuration vector is input to the chip to be tested through a configuration pin between the chip to be tested, so as to control the chip to be tested to respond to the timing post-shift mode configuration vector, and control the scan chain composed of the timing function register to enter the shift mode. Accordingly, the chip to be tested can shift out the current value of the timing function register based on the scan shift function corresponding to the shift mode, determine the actual timing result based on the shifted current value, and output it to ATE. In this way, by loading and inputting the timing post-shift mode configuration vector for the chip to be tested, the chip to be tested can shift out the current value of the timing function register based on the scan shift function corresponding to the shift mode, and then obtain the actual timing result, and the actual timing result is obtained with high efficiency.

[0077] Optionally, the generating of a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information may specifically include:

[0078] Step 1041: Load an expected timing result corresponding to the timing information; the expected timing result is obtained in advance based on the timing initial value and the timing information.

[0079] Step 1042: Compare the actual timing result with the expected timing result.

[0080] Step 1043: If the actual timing result is consistent with the expected timing result, a first test result is generated for the timing module to be tested; the first test result is used to indicate that the timing function of the timing module to be tested has passed the test.

[0081] Step 1044: If the actual timing result is inconsistent with the expected timing result, a second test result is generated for the timing module to be tested; the second test result is used to indicate that the timing function of the timing module to be tested has failed the test.

[0082] In an embodiment of the present invention, the expected timing result may also be referred to as an expected timing test vector or an expected value comparison graph. Among them, the expected value comparison graph may include: a vector representation of the correct value obtained by counting the timing information of each timing function register starting from the timing initial value. The ATE machine can load the expected timing result in the preset test file from the sixth designated storage location. The actual timing result can be shifted out to the ATE according to the preset clock signal. Specifically, the actual timing result can be shifted out beat by beat according to the clock cycle of the preset clock signal. Accordingly, the expected timing result can be loaded according to the preset clock signal. Specifically, the expected timing result can be loaded beat by beat according to the clock cycle of the preset clock signal. Among them, one beat corresponds to one clock cycle of the preset clock signal. The preset clock signal is set as needed, and the embodiment of the present invention does not limit this.

[0083] When comparing the actual timing result with the expected timing result, the comparison can be performed beat by beat according to the preset clock cycle. Specifically, the data in the actual timing result of each beat shifted out according to the preset clock signal can be compared beat by beat with the data in the expected timing result of each beat loaded according to the preset clock signal. If the comparison results are consistent each time, it can be determined that the actual timing result is consistent with the expected timing result, and the timing function is normal. Accordingly, a first test result indicating that the timing function has passed the test can be generated. If there is data corresponding to at least one beat of the preset clock signal in the actual timing result, which is inconsistent with the data corresponding to the preset clock signal of the beat in the expected timing result, it can be determined that the actual timing result is inconsistent with the expected timing result, and the timing function is abnormal. Accordingly, a second test result indicating that the timing function has not passed the test can be generated. Among them, the representation form of the first test result and the second test result can be set as needed. For example, the first test result can be represented as Pass, and the second test result can be represented as Fail. Figure 6 is a comparison schematic diagram provided by an embodiment of the present invention, such as Figure 6 As shown, the current value of the timing function register can be first shifted out based on the scan chain formed by the timing function register, and then the chip under test outputs the actual timing result determined based on the current value. ATE can compare the actual timing result with the expected timing result.

[0084] In the embodiment of the present invention, the expected timing result and the actual timing result are loaded with the same clock signal, and the actual timing result and the expected timing result are compared beat by beat, so that the accuracy of the comparison can be ensured, and thus the accuracy of the functional test results generated subsequently can be ensured.

[0085] It should be noted that, in the embodiment of the present invention, the timing information may be a clock signal of M beats. In the embodiment of the present invention, after completing the counting of each beat clock signal, a shift-out operation may be performed. Accordingly, when the actual timing result is compared with the expected timing result, for any beat clock signal in the timing information, the specific value corresponding to the clock signal in the actual timing result is compared with the specific value corresponding to the clock signal in the expected timing result; wherein the specific value corresponding to the clock signal in the expected timing result is obtained based on the timing initial value and the clock signal. If the specific value corresponding to the M beat clock signal in the actual timing result is consistent with the specific value corresponding to the M beat clock signal in the expected timing result, it can be determined that the actual timing result is consistent with the expected timing result, and the timing function is normal. Accordingly, a first test result indicating that the timing function passes the test can be generated. If there is a specific value corresponding to at least one beat clock signal in the actual timing result, which is inconsistent with the specific value corresponding to the beat clock signal in the expected timing result, it can be determined that the actual timing result is inconsistent with the expected timing result, and the timing function is abnormal. Accordingly, a second test result indicating that the timing function fails the test can be generated.

[0086] Optionally, the vectors included in the preset test file in the embodiment of the present invention may be generated based on an ATPG vector generation tool. Specifically, constraints may be set for the ATPG tool according to the timing module test requirements to control the ATPG tool to generate the required test vectors. Among them, the ATPG (Automatic Test Pattern Generation) tool is software for automatically generating test vectors. The design file of the chip to be tested, the configuration information of the scan chain composed of the timing function registers, and other test-related constraints (for example, the maximum length of the test vector, the predefined timing initial value, and the predefined clock signal with a fixed number of beats) may be provided to the ATPG tool to control the ATPG tool to generate various test vectors used in the embodiment of the present invention. Exemplarily, the ATPG tool may generate a test vector that enables the chip to be tested to enter the scan mode based on the design file of the chip to be tested, as a scan mode configuration vector. Based on the configuration information of the scan chain. Generate a timing post-shift mode configuration vector that enables the scan chain composed of the timing function registers to enter the shift mode, a timing pre-shift mode configuration vector that enables the scan chain composed of the timing function registers to enter the shift mode, and generate a test vector that enables the scan chain composed of the timing function registers to enter the capture mode as a capture mode configuration vector. Based on the predefined timing initial value, a test vector that can indicate the timing initial value is generated as a setting vector. Based on the predefined timing initial value and a predefined clock signal with a fixed number of beats, an expected timing test vector is generated. In the embodiment of the present invention, the test vector can be generated by reusing a general ATPG tool. In this way, the implementation cost of the test method can be reduced. Of course, the test vector can also be manually written, and the embodiment of the present invention does not limit this.

[0087] Reference Figure 7 , shows a block diagram of a test device for a timing module provided by an embodiment of the present invention, which is applied to an automatic test machine ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, and the timing function register in the timing module to be tested supports scan testing, such as Figure 7 As shown, the test device of the timing module specifically includes:

[0088] The first control module 201 is used to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value;

[0089] A first input module 202, used for inputting timing information for the chip to be tested, so as to control the timing module to be tested to perform timing operation starting from the timing initial value of the timing function register according to the timing information;

[0090] A second control module 203, configured to control the chip under test to shift out an actual timing result corresponding to the timing function register based on the timing post-shift mode configuration vector in the preset test file;

[0091] The generating module 204 is configured to generate a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information.

[0092] Optionally, the first control module 201 is specifically configured to:

[0093] Loading the scan mode configuration vector from the preset test file, and inputting the scan mode configuration vector to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to respond to the mode configuration vector and enter the scan mode indicated by the mode configuration vector;

[0094] The setting vector is loaded from the preset test file, and the setting vector is input to the chip under test that enters the scan mode, so as to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector.

[0095] Optionally, the device further comprises:

[0096] a second input module, configured to input a timing pre-shift mode configuration vector into the chip under test through a configuration pin between the chip under test, so as to control the chip under test to respond to the timing pre-shift mode configuration vector and control the scan chain formed by the timing function register to enter a shift mode;

[0097] The chip under test sets the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector, including: the chip under test moves the timing initial value indicated by the setting vector into the timing function register based on the scan shift function corresponding to the shift pattern.

[0098] Optionally, the device further comprises:

[0099] A third input module is used to load a capture mode configuration vector from the preset test file, and input the capture mode configuration vector into the chip under test, so as to control the chip under test to respond to the capture mode configuration vector and control the scan chain composed of the timing function registers to enter the capture mode;

[0100] The timing module to be tested performs a timing operation according to the timing information starting from the timing initial value based on the timing function register, including: the chip to be tested inputs the timing information into the timing function register based on the data input function corresponding to the capture mode, so that the timing function register starts timing according to the timing information starting from the timing initial value.

[0101] Optionally, the second control module 203 is specifically configured to:

[0102] The timing post-shift mode configuration vector is loaded from the preset test file, and the timing post-shift mode configuration vector is input to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to perform the following operations:

[0103] In response to the post-timing shift mode configuration vector, the chip under test controls the scan chain formed by the timing function registers to enter a shift mode;

[0104] The chip under test shifts out the current value of the timing function register based on the scan shift function corresponding to the shift mode;

[0105] The chip under test determines the actual timing result based on the shifted-out current value, and shifts the actual timing result out to the ATE.

[0106] Optionally, the generating module 204 is specifically configured to:

[0107] Loading an expected timing result corresponding to the timing information; the expected timing result is obtained in advance based on the timing initial value and the timing information;

[0108] Comparing the actual timing result with the expected timing result;

[0109] If the actual timing result is consistent with the expected timing result, a first test result is generated for the timing module to be tested; the first test result is used to indicate that the timing function of the timing module to be tested has passed the test;

[0110] If the actual timing result is inconsistent with the expected timing result, a second test result is generated for the timing module to be tested; the second test result is used to indicate that the timing function of the timing module to be tested has failed the test.

[0111] Optionally, the actual timing result is shifted out to the ATE according to a preset clock signal;

[0112] The generating module is further configured to: load the expected timing result according to the preset clock signal;

[0113] The data in the actual timing result of each beat shifted out according to the preset clock signal is compared beat by beat with the data in the expected timing result of each beat loaded according to the preset clock signal.

[0114] Optionally, the vectors included in the preset test file are generated based on an ATPG vector generation tool.

[0115] In summary, the test device of the timing module provided by the embodiment of the present invention is applied to an automatic test machine ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, and the timing function register in the timing module to be tested supports scan testing. In the method, based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value, the chip to be tested is controlled to set the value of the timing function register to the timing initial value indicated by the setting vector. Then, the timing information is input for the chip to be tested to control the timing module to be tested to perform the timing operation from the timing initial value of the timing function register according to the timing information. Based on the timing post-shift mode configuration vector in the preset test file, the chip to be tested is controlled to shift out the actual timing result corresponding to the timing function register. Finally, based on the actual timing result and the expected timing result corresponding to the timing information, a functional test result is generated for the timing module to be tested. In this way, there is no need to specially configure a development environment for the chip to be tested, and the automatic test of the timing function of the timing module can be realized based on the general ATE. Therefore, the test cost required for testing the timing function can be reduced.

[0116] An embodiment of the present invention further provides an integrated circuit, characterized in that the integrated circuit includes a timing module, the timing function register in the timing module is a scan register, and the timing function register constitutes a scan chain.

[0117] In response to the first control operation of the ATE, the value of the timing function register is set to the timing initial value indicated by the setting vector; the first control operation is a control operation performed by the ATE based on the scan mode configuration vector in the preset test file and the setting vector. Specifically, the specific implementation of the first control operation can refer to the relevant description of the aforementioned step 101, which will not be repeated here. The timing module can be the aforementioned timing module to be tested, and the integrated circuit can be the aforementioned chip to be tested.

[0118] The timing module is used to respond to input timing information and perform a timing operation starting from the timing initial value of the timing function register according to the timing information.

[0119] In response to the second control operation of the ATE, the actual timing result corresponding to the timing function register is shifted out, so that the ATE can generate a functional test result for the timing module based on the actual timing result and the expected timing result corresponding to the timing information; the second control operation is a control operation performed by the ATE based on the timing post-shift mode configuration vector in the preset test file. Specifically, the specific implementation of the second control operation can refer to the relevant description of the aforementioned step 103, which will not be repeated here.

[0120] Reference Figure 8 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the test method of the timing module of the above embodiment. The executable instructions can form a program.

[0121] An embodiment of the present invention provides a machine-readable medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the test method of the timing module of the aforementioned embodiment.

[0122] An embodiment of the present invention provides a timing module, which includes a timing function register, and the timing function register is configured to support scan testing; the timing module is tested according to the testing method of the timing module of the above embodiment.

[0123] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0124] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0125] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0126] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0130] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0131] The above describes in detail a testing method for a timing module, a testing device for a timing module, an electronic device and one or more readable media provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for testing a timing module, characterized in that: The method is applied to an automatic tester ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, wherein the timing function register in the timing module to be tested supports scan testing, and the method comprises: Based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value, control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector; Inputting timing information to the chip to be tested, so as to control the timing module to be tested to perform timing operation starting from the timing initial value of the timing function register according to the timing information; Based on the timing post-shift mode configuration vector in the preset test file, control the chip under test to shift out the actual timing result corresponding to the timing function register; Based on the actual timing result and the expected timing result corresponding to the timing information, a functional test result is generated for the timing module to be tested.

2. The method according to claim 1, characterized in that The step of controlling the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the scan mode configuration vector in the preset test file and the setting vector for setting the timing initial value includes: Loading the scan mode configuration vector from the preset test file, and inputting the scan mode configuration vector to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to respond to the mode configuration vector and enter the scan mode indicated by the mode configuration vector; The setting vector is loaded from the preset test file, and the setting vector is input to the chip under test that enters the scan mode, so as to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector.

3. The method according to claim 2, characterized in that The method further comprises: Inputting a timing pre-shift mode configuration vector to the chip under test through a configuration pin between the chip under test, so as to control the chip under test to respond to the timing pre-shift mode configuration vector and control the scan chain formed by the timing function register to enter a shift mode; The chip under test sets the value of the timing function register to the timing initial value indicated by the setting vector based on the setting vector, including: the chip under test moves the timing initial value indicated by the setting vector into the timing function register based on the scan shift function corresponding to the shift pattern.

4. The method according to claim 1, characterized in that: The method further comprises: Loading a capture mode configuration vector from the preset test file, and inputting the capture mode configuration vector into the chip under test, so as to control the chip under test to respond to the capture mode configuration vector and control the scan chain formed by the timing function registers to enter the capture mode; The timing module to be tested performs a timing operation according to the timing information starting from the timing initial value based on the timing function register, including: the chip to be tested inputs the timing information into the timing function register based on the data input function corresponding to the capture mode, so that the timing function register starts timing according to the timing information starting from the timing initial value.

5. The method according to claim 1, characterized in that The controlling the chip under test to shift out the actual timing result corresponding to the timing function register based on the timing post-shift mode configuration vector in the preset test file includes: The timing post-shift mode configuration vector is loaded from the preset test file, and the timing post-shift mode configuration vector is input to the chip under test through the configuration pin between the chip under test, so as to control the chip under test to perform the following operations: In response to the post-timing shift mode configuration vector, the chip under test controls the scan chain formed by the timing function registers to enter a shift mode; The chip under test shifts out the current value of the timing function register based on the scan shift function corresponding to the shift mode; The chip under test determines the actual timing result based on the shifted-out current value, and shifts the actual timing result out to the ATE.

6. The method according to claim 1, characterized in that The generating a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information includes: Loading an expected timing result corresponding to the timing information; the expected timing result is obtained in advance based on the timing initial value and the timing information; Comparing the actual timing result with the expected timing result; If the actual timing result is consistent with the expected timing result, a first test result is generated for the timing module to be tested; the first test result is used to indicate that the timing function of the timing module to be tested has passed the test; If the actual timing result is inconsistent with the expected timing result, a second test result is generated for the timing module to be tested; the second test result is used to indicate that the timing function of the timing module to be tested has failed the test.

7. The method according to claim 6, characterized in that The actual timing result is shifted out to the ATE according to a preset clock signal; The loading of the expected timing result corresponding to the timing information includes: loading the expected timing result according to the preset clock signal; The comparing the actual timing result with the expected timing result includes: The data in the actual timing result of each beat shifted out according to the preset clock signal is compared beat by beat with the data in the expected timing result of each beat loaded according to the preset clock signal.

8. The method according to any one of claims 1 to 7, characterized in that: The vectors included in the preset test file are generated based on an ATPG vector generation tool.

9. A testing device for a timing module, characterized in that: The device is applied to an automatic tester ATE, wherein the ATE is loaded with a chip to be tested including a timing module to be tested, wherein the timing function register in the timing module to be tested supports a scan test, and the device comprises: A first control module, configured to control the chip under test to set the value of the timing function register to the timing initial value indicated by the setting vector based on a scan mode configuration vector in a preset test file and a setting vector for setting the timing initial value; A first input module, used for inputting timing information for the chip to be tested, so as to control the timing module to be tested to perform a timing operation starting from the timing initial value of the timing function register according to the timing information; A second control module, configured to control the chip under test to shift out an actual timing result corresponding to the timing function register based on the timing post-shift mode configuration vector in the preset test file; A generating module is used to generate a functional test result for the timing module to be tested based on the actual timing result and the expected timing result corresponding to the timing information.

10. An integrated circuit, characterized in that: The integrated circuit comprises a timing module, the timing function register in the timing module is a scan register, and the timing function register constitutes a scan chain; In response to a first control operation of the ATE, the value of the timing function register is set to the timing initial value indicated by the setting vector; the first control operation is a control operation performed by the ATE based on the scan mode configuration vector in the preset test file and the setting vector; The timing module is used to respond to the input timing information and perform a timing operation starting from the timing initial value of the timing function register according to the timing information; In response to a second control operation of the ATE, an actual timing result corresponding to the timing function register is shifted out, so that the ATE can generate a functional test result for the timing module based on the actual timing result and an expected timing result corresponding to the timing information; The second control operation is a control operation performed by the ATE based on a timing post-shift mode configuration vector in the preset test file.

11. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method according to any one of claims 1 to 8.

12. One or more machine-readable media, characterized in that Instructions are stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 8.

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