Tower type packaging structure and packaging method for transverse power semiconductor device

Abstract

The invention provides a tower type packaging structure and a packaging method for a transverse power semiconductor device, a plurality of transverse power semiconductor chips are packaged in the same device in a laminated manner through a simple method, and the chips are stacked and fixed by adopting an insulation connection layer-transition layer-insulation connection layer sandwich structure. The connection stability of each layer of chip is improved, the heat dissipation is enhanced, and a solution is provided for miniaturization and high performance of the device; in addition, due to the parallel structure of the multiple layers of chips, the on-resistance and the on-voltage drop of the power semiconductor device are also reduced. In conclusion, the tower type packaging structure for the transverse power semiconductor device can effectively improve the packaging stability and the heat dissipation capability, so that the power processing capability of the transverse power semiconductor device in unit area is improved, and excellent area performance efficiency is realized.

Description

Technical Field

[0001] The invention relates to the technical field of microelectronic packaging technology, in particular to a tower packaging structure and a packaging method for a lateral power semiconductor device. Background Art

[0002] As the complexity of electronic systems increases, the requirements for microelectronic packaging are becoming increasingly higher. Traditional chip packaging methods have defects such as large size and poor performance, and cannot meet the modern high-performance and miniaturization requirements. For power semiconductor devices, due to the heat generation when processing high voltage and high current, their power handling capacity is limited by the device area. Greater power requirements mean larger chip areas, which is not conducive to the miniaturization of electronic systems.

[0003] In view of the shortcomings of traditional two-dimensional packaging methods, some three-dimensional packaging technologies have emerged in recent years, but they cannot be widely used due to their complex production, disadvantages in heat dissipation of power devices and device layering. The present invention proposes a tower packaging structure that can connect horizontal power semiconductors in parallel. The bonding method of this structure adopts a more economical wire bonding. A new "sandwich" structure of supporting insulation layers is used between chips to make room for wires. On the one hand, stacking and paralleling of horizontal power devices is realized, and on the other hand, the high cost of advanced packaging such as TSV is avoided. Summary of the invention

[0004] The technical problem to be solved by the present invention is: to package more lateral power semiconductor power devices in a smaller area, and effectively improve the packaging stability and heat dissipation capability, thereby increasing the power processing capability of the lateral power semiconductor devices per unit area and achieving excellent area-performance efficiency.

[0005] To achieve the above-mentioned purpose, the present invention provides a tower packaging structure for a lateral power semiconductor device, and its detailed technical solution is as follows:

[0006] A tower packaging structure for a lateral power semiconductor device, comprising: a substrate 101, a first power semiconductor device chip 201, a second power semiconductor device chip 202, a first insulating adhesive layer 301, a second insulating adhesive layer 302, a third insulating adhesive layer 303, a transition layer 401, a first bonding wire 501, a second bonding wire 502, a third bonding wire 503, a fourth bonding wire 504 and a plastic packaging material 601;

[0007] The substrate 101 is located at the bottom, the molding material 601 is located above the substrate 101, and the lower, left and right edges of the molding material 601 are tangent to the upper, left and right edges of the substrate 101 respectively; the first power semiconductor device chip 201, the second power semiconductor device chip 202, the first insulating adhesive layer 301, the second insulating adhesive layer 302, the third insulating adhesive layer 303 and the transition layer 401 are all located inside the molding material 601, from bottom to top, the first insulating adhesive layer 301, the first power semiconductor device chip 201, the second insulating adhesive layer 302, the transition layer 401, the third insulating adhesive layer 303 and the second insulating adhesive layer 301 are tightly connected to each other. The power semiconductor device chip 202, and the lower edge of the first insulating adhesive layer 301 is tangent to the lower edge of the plastic packaging material 601; the two ends of the first bonding wire 501 are respectively connected to the left port of the first power semiconductor device chip 201 and the left end of the substrate 101; the two ends of the second bonding wire 502 are respectively connected to the right port of the first power semiconductor device chip 201 and the right end of the substrate 101; the two ends of the third bonding wire 503 are respectively connected to the left port of the second power semiconductor device chip 202 and the left end of the substrate 101; the two ends of the fourth bonding wire 504 are respectively connected to the right port of the second power semiconductor device chip 202 and the right end of the substrate 101.

[0008] As a preferred embodiment, the left and right edges of the transition layer 401 do not exceed the left and right edges of the first power semiconductor device chip 201 and the second power semiconductor device chip 202 .

[0009] As a preferred method, an insulating adhesive layer, a transition layer, an insulating adhesive layer and a power semiconductor device chip are repeatedly placed above the second power semiconductor device chip 202 to form a lateral power semiconductor device structure of a multi-layer stacked package.

[0010] As a preferred embodiment, the first power semiconductor device chip 201 and the second power semiconductor device chip 202 are three-terminal or four-terminal power semiconductor chips.

[0011] The second object of the present invention is to provide a packaging method for a tower packaging structure for a lateral power semiconductor device, which is a double-layer tower packaging, comprising the following steps:

[0012] S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device;

[0013] S2: Applying the first insulating adhesive layer 301 on the substrate 101;

[0014] S3: placing the first power semiconductor device chip 201 on the first insulating adhesive layer 301 and curing it;

[0015] S4: The first power semiconductor device chip 201 has only two PADs in total; each PAD of the first power semiconductor device chip 201 is bonded to a corresponding pad through a first bonding wire 501 and a second bonding wire 502;

[0016] S5: applying the second insulating adhesive layer 302, the transition layer 401, and the third insulating adhesive layer 303 on the first power semiconductor device chip 201, while avoiding the lead area of ​​the first power semiconductor device chip 201;

[0017] S6: placing the second power semiconductor device chip 202 on the third insulating adhesive layer 303 and curing it;

[0018] S7: The second power semiconductor device chip 202 has only two PADs in total; each PAD of the second power semiconductor device chip 202 is bonded to a corresponding pad via a third bonding wire 503 and a fourth bonding wire 504;

[0019] S8: Pour the plastic packaging material into the designed mold and cut it into shape.

[0020] The third object of the present invention is to provide a packaging method for the tower packaging structure of a lateral power semiconductor device, which is a multi-layer tower packaging with more than three layers, comprising the following steps:

[0021] S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device;

[0022] S2: Applying the first insulating adhesive layer 301 on the substrate 101;

[0023] S3: placing the first power semiconductor device chip 201 on the first insulating adhesive layer 301 and curing it;

[0024] S4: The first power semiconductor device chip 201 has only two PADs in total; each PAD of the first power semiconductor device chip 201 is bonded to a corresponding pad through a first bonding wire 501 and a second bonding wire 502;

[0025] S5: applying the second insulating adhesive layer 302, the transition layer 401, and the third insulating adhesive layer 303 on the first power semiconductor device chip 201, while avoiding the lead area of ​​the first power semiconductor device chip 201;

[0026] S6: placing the second power semiconductor device chip 202 on the third insulating adhesive layer 303 and curing it;

[0027] S7: repeat steps S4-S6 until the required number of layers is stacked;

[0028] S8: Pour the plastic packaging material into the designed mold and cut it into shape.

[0029] The first insulating adhesive layer 301 is located between the substrate 101 and the first power semiconductor device chip 201 to ensure connection stability; the second insulating adhesive layer 302 is located between the first power semiconductor device chip 201 and the transition layer 401 to ensure connection stability; the third insulating adhesive layer 303 is located between the transition layer 401 and the second power semiconductor device chip 202 to ensure connection stability; the port of the second power semiconductor device chip 202 is connected to the substrate 101 through the third bonding wire 503 and the fourth bonding wire 504 to achieve parallel connection between the first power semiconductor device chip 201 and the second power semiconductor device chip 202; the first power semiconductor device chip 201, the second power semiconductor device chip 202, the first insulating adhesive layer 301, the second insulating adhesive layer 302, the transition layer 401, the first bonding wire 501, the second bonding wire 502, the third bonding wire 503, and the fourth bonding wire 504 are all located inside the plastic packaging material 601 to be isolated from the outside world and protect the semiconductor chip.

[0030] The beneficial effects of the present invention are as follows: through the tower packaging technology proposed in the present invention, two (or more) small-area power semiconductor device chips are packaged within a smaller area, and the parallel connection of the power semiconductor device chips is realized through bonding wires and a substrate, thereby increasing the power processing capacity of the lateral power semiconductor device per unit area; the power semiconductor device chips are stably bonded together through an insulating adhesive layer and a transition layer, thereby ensuring the packaging stability, and the introduction of the transition layer also enhances the heat dissipation capacity of the tower packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the structure of a tower packaging device proposed in Embodiment 1 of the present invention;

[0032] Figure 2 A schematic diagram of the structure of a tower packaging device proposed in Embodiment 2 of the present invention;

[0033] 101 is a substrate, 201 is a first power semiconductor device chip, 202 is a second power semiconductor device chip, 301 is a first insulating adhesive layer, 302 is a second insulating adhesive layer, 303 is a third insulating adhesive layer, 401 is a transition layer, 501 is a first bonding wire, 502 is a second bonding wire, 503 is a third bonding wire, 504 is a fourth bonding wire, and 601 is a plastic encapsulation material. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Example 1

[0036] This embodiment provides a tower packaging structure for a lateral power semiconductor device, such as Figure 1 As shown, the structure includes: a substrate 101, a first power semiconductor device chip 201, a second power semiconductor device chip 202, a first insulating adhesive layer 301, a second insulating adhesive layer 302, a third insulating adhesive layer 303, a transition layer 401, a first bonding wire 501, a second bonding wire 502, a third bonding wire 503, a fourth bonding wire 504 and a plastic packaging material 601;

[0037] The substrate 101 is located at the bottom, the molding material 601 is located above the substrate 101, and the lower, left and right edges of the molding material 601 are tangent to the upper, left and right edges of the substrate 101 respectively; the first power semiconductor device chip 201, the second power semiconductor device chip 202, the first insulating adhesive layer 301, the second insulating adhesive layer 302, the third insulating adhesive layer 303 and the transition layer 401 are all located inside the molding material 601, from bottom to top, the first insulating adhesive layer 301, the first power semiconductor device chip 201, the second insulating adhesive layer 302, the transition layer 401, the third insulating adhesive layer 303 and the second insulating adhesive layer 301 are tightly connected to each other. The power semiconductor device chip 202, and the lower edge of the first insulating adhesive layer 301 is tangent to the lower edge of the plastic packaging material 601; the two ends of the first bonding wire 501 are respectively connected to the left port of the first power semiconductor device chip 201 and the left end of the substrate 101; the two ends of the second bonding wire 502 are respectively connected to the right port of the first power semiconductor device chip 201 and the right end of the substrate 101; the two ends of the third bonding wire 503 are respectively connected to the left port of the second power semiconductor device chip 202 and the left end of the substrate 101; the two ends of the fourth bonding wire 504 are respectively connected to the right port of the second power semiconductor device chip 202 and the right end of the substrate 101.

[0038] The left and right edges of the transition layer 401 do not exceed the left and right edges of the first power semiconductor device chip 201 and the second power semiconductor device chip 202 .

[0039] In other embodiments, the first power semiconductor device chip 201 and the second power semiconductor device chip 202 are three-terminal or four-terminal power semiconductor chips.

[0040] This embodiment also provides a packaging method for the tower packaging structure for a lateral power semiconductor device, which is a double-layer tower packaging, comprising the following steps:

[0041] The production steps of double-layer tower package are as follows:

[0042] S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device;

[0043] S2: Applying the first insulating adhesive layer 301 on the substrate 101;

[0044] S3: placing the first power semiconductor device chip 201 on the first insulating adhesive layer 301 and curing it;

[0045] S4: The first power semiconductor device chip 201 has only two PADs in total; each PAD of the first power semiconductor device chip 201 is bonded to a corresponding pad through a first bonding wire 501 and a second bonding wire 502;

[0046] S5: applying the second insulating adhesive layer 302, the transition layer 401, and the third insulating adhesive layer 303 on the first power semiconductor device chip 201, while avoiding the lead area of ​​the first power semiconductor device chip 201;

[0047] S6: placing the second power semiconductor device chip 202 on the third insulating adhesive layer 303 and curing it;

[0048] S7: The second power semiconductor device chip 202 has only two PADs in total; each PAD of the second power semiconductor device chip 202 is bonded to a corresponding pad via a third bonding wire 503 and a fourth bonding wire 504;

[0049] S8: Pour the plastic packaging material into the designed mold and cut it into shape.

[0050] Example 2

[0051] This embodiment provides an embodiment 2 of a tower packaging structure of a lateral power semiconductor device. Figure 2 As shown, compared with Example 1, due to the repeatability of the packaging steps, the insulating adhesive layer, the transition layer, the insulating adhesive layer and the power semiconductor device chip are repeatedly placed above the second power semiconductor device chip 202, thereby forming a multi-layer stacked package lateral power semiconductor device structure. The power handling capacity of the power semiconductor device is greatly increased; in addition, the multi-layer parallel-connected power semiconductor device can greatly reduce the on-resistance and on-voltage drop of the device when it is turned on;

[0052] This embodiment also provides a packaging method for a tower packaging structure of a lateral power semiconductor device, which is a multi-layer tower packaging with more than three layers, comprising the following steps:

[0053] The steps for making a multi-layer tower package are as follows:

[0054] S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device;

[0055] S2: Applying the first insulating adhesive layer 301 on the substrate 101;

[0056] S3: placing the first power semiconductor device chip 201 on the first insulating adhesive layer 301 and curing it;

[0057] S4: The first power semiconductor device chip 201 has only two PADs in total; each PAD of the first power semiconductor device chip 201 is bonded to a corresponding pad through a first bonding wire 501 and a second bonding wire 502;

[0058] S5: applying the second insulating adhesive layer 302, the transition layer 401, and the third insulating adhesive layer 303 on the first power semiconductor device chip 201, while avoiding the lead area of ​​the first power semiconductor device chip 201;

[0059] S6: placing the second power semiconductor device chip 202 on the third insulating adhesive layer 303 and curing it;

[0060] S7: repeat steps S4-S6 until the required number of layers is stacked;

[0061] S8: Pour the plastic packaging material into the designed mold and cut it into shape.

[0062] At the same time, please note that when performing tower packaging, the total height of the chip and the insulation structure must not exceed the height of the mold. At the same time, when bonding, the wire length will gradually increase as the number of layers increases, resulting in greater resistance.

[0063] How it works

[0064] The tower packaging structure for lateral power semiconductor devices proposed by the present invention uses a simple method to stack and package multiple lateral power semiconductor chips inside the same device. The stacking and fixing of the chips adopts a sandwich structure of insulating connection layer-transition layer-insulating connection layer, which improves the connection stability of each layer of chips and enhances heat dissipation, providing a solution for the miniaturization and high performance of the device; in addition, the parallel structure of the multi-layer chips also reduces the on-resistance and on-voltage drop of the power semiconductor device. Based on the above principles, the tower packaging structure for lateral power semiconductor devices proposed by the present invention can effectively improve the packaging stability and heat dissipation capacity, thereby increasing the power handling capacity of the lateral power semiconductor device per unit area and achieving excellent area performance efficiency.

[0065] Embodiment 1 and Embodiment 2 show the stacked packaging structure of 2-port power semiconductor chips. Similarly, the structure is also applicable to the stacked packaging of 3-terminal or 4-terminal lateral power semiconductor devices, which should also be included in the protection scope of the present invention.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A tower packaging structure for a lateral power semiconductor device, Features include: A substrate (101), a first power semiconductor device chip (201), a second power semiconductor device chip (202), a first insulating adhesive layer (301), a second insulating adhesive layer (302), a third insulating adhesive layer (303), a transition layer (401), a first bonding wire (501), a second bonding wire (502), a third bonding wire (503), a fourth bonding wire (504), and a plastic encapsulation material (601); The substrate (101) is located at the bottom, the molding material (601) is located above the substrate (101), and the lower, left and right edges of the molding material (601) are tangent to the upper, left and right edges of the substrate (101) respectively; the first power semiconductor device chip (201), the second power semiconductor device chip (202), the first insulating adhesive layer (301), the second insulating adhesive layer (302), the third insulating adhesive layer (303) and the transition layer (401) are all located inside the molding material (601), and from bottom to top, they are the first insulating adhesive layer (301) with the upper and lower edges of each layer tightly connected, the first power semiconductor device chip (201), the second insulating adhesive layer (302), the transition layer (401), the third insulating adhesive layer (303) and A second power semiconductor device chip (202), and the lower edge of the first insulating adhesive layer (301) is tangent to the lower edge of the plastic packaging material (601); two ends of the first bonding wire (501) are respectively connected to the left port of the first power semiconductor device chip (201) and the left end of the substrate (101); two ends of the second bonding wire (502) are respectively connected to the right port of the first power semiconductor device chip (201) and the right end of the substrate (101); two ends of the third bonding wire (503) are respectively connected to the left port of the second power semiconductor device chip (202) and the left end of the substrate (101); and two ends of the fourth bonding wire (504) are respectively connected to the right port of the second power semiconductor device chip (202) and the right end of the substrate (101).

2. The tower packaging structure for a lateral power semiconductor device according to claim 1, Features: The left and right edges of the transition layer (401) do not exceed the left and right edges of the first power semiconductor device chip (201) and the second power semiconductor device chip (202).

3. The tower packaging structure for a lateral power semiconductor device according to claim 1, Features: An insulating adhesive layer, a transition layer, an insulating adhesive layer and a power semiconductor device chip are repeatedly placed above the second power semiconductor device chip (202), thereby forming a lateral power semiconductor device structure of a multi-layer stacked package.

4. The tower packaging structure for a lateral power semiconductor device according to claim 1, Features: The first power semiconductor device chip (201) and the second power semiconductor device chip (202) are three-terminal or four-terminal power semiconductor chips.

5. A packaging method for a tower packaging structure for a lateral power semiconductor device according to any one of claims 1 to 4, Features It is a double-layer tower package, including the following steps: S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device; S2: applying a first insulating adhesive layer (301) on the substrate (101); S3: placing the first power semiconductor device chip (201) on the first insulating adhesive layer (301) and curing it; S4: the first power semiconductor device chip (201) has only two PADs in total; each PAD of the first power semiconductor device chip (201) is bonded to a corresponding pad via a first bonding wire (501) and a second bonding wire (502); S5: applying a second insulating adhesive layer (302), a transition layer (401), and a third insulating adhesive layer (303) above the first power semiconductor device chip (201), while avoiding the lead area of ​​the first power semiconductor device chip (201); S6: placing the second power semiconductor device chip (202) on the third insulating adhesive layer (303) and curing it; S7: the second power semiconductor device chip (202) has only two PADs in total; each PAD of the second power semiconductor device chip (202) is bonded to a corresponding pad via a third bonding wire (503) and a fourth bonding wire (504); S8: Pour the plastic packaging material into the designed mold and cut it into shape.

6. A packaging method for a tower packaging structure for a lateral power semiconductor device according to any one of claims 1 to 4, Features For a multi-layer tower package with more than three layers, the following steps are included: S1: Prepare a substrate and design metal pads on the substrate for leading out electrodes of the power device; S2: applying a first insulating adhesive layer (301) on the substrate (101); S3: placing the first power semiconductor device chip (201) on the first insulating adhesive layer (301) and curing it; S4: the first power semiconductor device chip (201) has only two PADs in total; each PAD of the first power semiconductor device chip (201) is bonded to a corresponding pad via a first bonding wire (501) and a second bonding wire (502); S5: applying a second insulating adhesive layer (302), a transition layer (401), and a third insulating adhesive layer (303) above the first power semiconductor device chip (201), while avoiding the lead area of ​​the first power semiconductor device chip (201); S6: placing the second power semiconductor device chip (202) on the third insulating adhesive layer (303) and curing it; S7: repeat steps S4-S6 until the required number of layers is stacked; S8: Pour the plastic packaging material into the designed mold and cut it into shape.

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