Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a gate structure and a side wall on the substrate, and enabling the gate structure to comprise a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer; forming a first patterned photoresist layer covering the NMOS region; forming grooves in the substrate at two sides of the gate structure in the PMOS region, and reserving an amorphous carbon layer with a partial thickness on the second hard mask layer; the first patterned photoresist layer is removed; and removing the amorphous carbon layer by adopting an ashing process. In the process of forming the groove in the PMOS region, the amorphous carbon layer protects the second hard mask layer below the amorphous carbon layer from being thinned, and after the amorphous carbon layer is removed, the thickness of the second hard mask layer in the two regions can be ensured to be consistent, so that the height of the dummy gate is ensured to be consistent, and the electrical performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the increasing integration of CMOS technology and the shrinking of key dimensions, the stress stretching method used in traditional CMOS processes can no longer meet the device's requirements for PMOS drive current. When the key dimensions reach 28nm and below, germanium silicon (GeSi) epitaxial technology is needed to increase the compressive stress of PMOS, thereby improving the overall response speed of the device.

[0003] However, during the formation of the epitaxial structure of PMOS, the PMOS pseudo gate is exposed, and after etching and other processes, the second hard mask layer on the PMOS pseudo gate becomes thinner or disappears. In the subsequent chemical mechanical polishing process, the thickness of the hard mask layer on the NMOS and PMOS pseudo gates is different, resulting in different pseudo gate heights, which affects the subsequent electrical performance. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can keep the pseudo gate heights in the NMOS region and the PMOS region consistent, thereby avoiding affecting the subsequent electrical performance.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: Providing a substrate, the substrate comprising an NMOS region and a PMOS region, a gate structure is formed on the substrate in both the NMOS region and the PMOS region, the gate structure comprises a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer sequentially formed on the substrate, and a sidewall of the gate structure is formed with a sidewall; Forming a first patterned photoresist layer, wherein the first patterned photoresist layer covers the substrate and the gate structure in the NMOS region; forming grooves in the substrate at both sides of the gate structure in the PMOS region, and retaining a partial thickness of the amorphous carbon layer on the second hard mask layer; removing the first patterned photoresist layer; and The amorphous carbon layer in the NMOS region and the PMOS region is removed by an ashing process.

[0006] Optionally, the cross-sectional widths of the dummy gates in different gate structures are different.

[0007] Optionally, in the step of providing the substrate, an upper surface of the sidewall spacer is flush with an upper surface of the second hard mask layer.

[0008] Optionally, after the amorphous carbon layer is removed by an ashing process, the upper surface of the sidewall spacer is flush with the upper surface of the second hard mask layer.

[0009] Optionally, after the amorphous carbon layer is removed by an ashing process, the upper surface of the second hard mask layer in the NMOS region is flush with the upper surface of the second hard mask layer in the PMOS region.

[0010] Optionally, the temperature of the ashing process is between 300°C and 350°C.

[0011] Optionally, the method for forming the gate structure includes: forming a gate dielectric material layer, a dummy gate material layer, a first hard mask material layer, a second hard mask material layer and an amorphous carbon material layer on the substrate in sequence; forming a second patterned photoresist layer, wherein the second patterned photoresist layer covers the area where the gate structure is to be formed and exposes the remaining area; Using the second patterned photoresist layer as a mask, sequentially etching the amorphous carbon material layer, the second hard mask material layer, the first hard mask material layer, the dummy gate material layer, and the gate dielectric material layer until a portion of the substrate is exposed; and The second patterned photoresist layer is removed.

[0012] Optionally, a wet etching process is used to remove the first patterned photoresist layer and the second patterned photoresist layer.

[0013] Optionally, after removing the amorphous carbon layer, the manufacturing method further comprises: filling silicon germanium in the groove to form an epitaxial structure.

[0014] Correspondingly, the present invention also provides a semiconductor device manufactured by the method for manufacturing the semiconductor device as described above.

[0015] In summary, in the semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, the substrate comprising an NMOS region and a PMOS region, a gate structure is formed on the substrate in the NMOS region and the PMOS region, the gate structure comprises a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer sequentially formed on the substrate, and a sidewall of the gate structure is formed with a sidewall; then a first patterned photoresist layer covering the NMOS region is formed, and then grooves are formed in the substrate on both sides of the gate structure in the PMOS region, and a partial thickness of the amorphous carbon layer is retained on the second hard mask layer, and then the first patterned photoresist layer is removed, and then an ashing process is used to remove the amorphous carbon layer in the NMOS region and the PMOS region. The unexpected effect of the present invention is that an amorphous carbon layer is formed on the second hard mask layer, and in the process of forming grooves in the substrate on both sides of the gate structure in the PMOS region, the amorphous carbon layer is used to protect the second hard mask layer below from being thinned. After the remaining amorphous carbon layer is subsequently removed, the thickness of the second hard mask layer in the NMOS region and the PMOS region can be guaranteed to be consistent, thereby ensuring that the height of the pseudo gate in the NMOS region and the PMOS region is consistent, thereby improving the electrical performance of the device. At the same time, removing the remaining amorphous carbon layer through the ashing process will not affect the remaining structures, there will be no residual problems, and will not cause other effects on the semiconductor device.

[0016] In addition, the cross-sectional widths of the pseudo gates in different gate structures may be different. An amorphous carbon layer is used to protect the second hard mask layer and an ashing process is used to remove it. This is not limited by the different cross-sectional widths of the pseudo gates. Compared with the prior art, this can save process steps and process costs.

[0017] Moreover, the upper surface of the side wall is flush with the upper surface of the second hard mask layer. After removing the remaining amorphous carbon layer, the upper surface of the side wall is flush with the upper surface of the gate structure. Therefore, when chemical mechanical polishing is subsequently used to remove the second hard mask layer and the first hard mask layer, the existence of the side wall will not affect the polishing. The polishing amount in the NMOS region is consistent with that in the PMOS region, thereby further ensuring that the height of the pseudo gates in the NMOS region and the PMOS region are consistent. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device provided by one embodiment of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure after an amorphous carbon material layer is formed according to an embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of a structure after a gate structure is formed according to an embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the structure after the first groove is formed according to an embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the structure after the second groove is formed according to an embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the structure after the first patterned photoresist layer is removed provided by an embodiment of the present invention.

[0024] Figure 7 It is a schematic diagram of the structure after the amorphous carbon layer is removed provided by one embodiment of the present invention.

[0025] Description of reference numerals: 10-substrate; 11-gate dielectric material layer; 12-dummy gate material layer; 13-first hard mask material layer; 14-second hard mask material layer; 15-amorphous carbon material layer; 20-gate structure; 21-gate dielectric layer; 22-dummy gate; 23-first hard mask layer; 24-second hard mask layer; 25-amorphous carbon layer; 26-side wall; 30-first patterned photoresist layer; 41-first groove; 42-second groove. DETAILED DESCRIPTION

[0026] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0027] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0028] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for manufacturing the semiconductor device comprises the following steps: S1: providing a substrate, the substrate comprising an NMOS region and a PMOS region, a gate structure being formed on the substrate in both the NMOS region and the PMOS region, the gate structure comprising a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer sequentially formed on the substrate, and a sidewall of the gate structure being formed with a sidewall; S2: forming a first patterned photoresist layer, wherein the first patterned photoresist layer covers the substrate and the gate structure in the NMOS region; S3: forming grooves in the substrate at both sides of the gate structure in the PMOS region, and a partial thickness of the amorphous carbon layer is retained on the second hard mask layer; S4: removing the first patterned photoresist layer; and S5: removing the amorphous carbon layer in the NMOS region and the PMOS region by using an ashing process.

[0029] Figures 2 to 7 FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 and Figures 2 to 7 The method for manufacturing a semiconductor device provided by an embodiment of the present invention is described in detail.

[0030] In step S1, refer to Figure 3As shown, a substrate 10 is provided, the substrate 10 includes an NMOS region I and a PMOS region II, a gate structure 20 is formed on the substrate 10 in the NMOS region I and the PMOS region II, the gate structure 20 includes a gate dielectric layer 21, a dummy gate 22, a first hard mask layer 23, a second hard mask layer 24 and an amorphous carbon layer 25 formed in sequence on the substrate 10, and a sidewall 26 is formed on the sidewall of the gate structure 20.

[0031] The material of the substrate 10 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, etc., or may be silicon on insulator, germanium on insulator; or may be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is silicon.

[0032] The substrate 10 includes an NMOS region I for forming an NMOS transistor and a PMOS region II for forming a PMOS transistor. Of course, the substrate 10 may also include regions for forming other devices, which is not limited in the present invention. A shallow trench isolation structure (not shown) may be formed in the substrate 10 between the NMOS region I and the PMOS region II and between gate structures formed subsequently.

[0033] In one embodiment of the present invention, a method for forming the gate structure 20 includes: First, please refer to Figure 2 As shown, a gate dielectric material layer 11, a pseudo gate material layer 12, a first hard mask material layer 13, a second hard mask material layer 14 and an amorphous carbon material layer 15 are sequentially formed on the substrate 10. The gate dielectric material layer 11 is, for example, silicon oxide, the pseudo gate material layer 12 is, for example, polysilicon, the first hard mask material layer 13 is, for example, silicon nitride, and the second hard mask material layer 14 is, for example, silicon oxide. In this embodiment, two hard mask layers are formed on the pseudo gate material layer 12. In other embodiments, one hard mask layer may be formed on the pseudo gate material layer 12, or more than two hard mask layers may be formed. The present invention is not limited to this.

[0034] Then, a second patterned photoresist layer (not shown) is formed, wherein the second patterned photoresist layer covers the area where the gate structure is to be formed and exposes the remaining area.

[0035] Then, using the second patterned photoresist layer as a mask, the amorphous carbon material layer 15 , the second hard mask material layer 14 , the first hard mask material layer 13 , the dummy gate material layer 12 and the gate dielectric material layer 11 are etched in sequence until a portion of the substrate 10 is exposed.

[0036] Then, the second patterned photoresist layer is removed to form Figure 3 In this embodiment, the second patterned photoresist layer is removed by a wet etching process to avoid consumption of the amorphous carbon layer 25 during removal of the second patterned photoresist layer by dry etching or other methods.

[0037] In one embodiment of the present invention, the cross-sectional widths of the dummy gates 22 in different gate structures 20 are different. Figure 3 As shown, two gate structures 20 are formed in the NMOS region I, wherein the cross-sectional width of the dummy gate 22 in one of the gate structures 20 is greater than the cross-sectional width of the dummy gate 22 in the other gate structure 20, and the cross-sectional width of the dummy gate 22 in the other gate structure 20 may be equal to the cross-sectional width of the dummy gate 22 in the PMOS region II. In another embodiment, a plurality of gate structures 20 may also be formed in the PMOS region II, and the cross-sectional widths of the dummy gates 22 in the gate structures 20 may be the same or different. In another embodiment, the cross-sectional width of the dummy gate 22 in the NMOS region I is different from the cross-sectional width of the dummy gate 22 in the PMOS region II. Of course, the cross-sectional width of the dummy gate 22 may be one, two, or more than two, and the present invention is not limited thereto.

[0038] Please continue to refer to Figure 3 As shown, after forming the gate structure 20, the manufacturing method further includes: forming a sidewall 26 on the sidewall of the gate structure 20. The sidewall 26 may include a first sidewall located on the sidewall of the gate structure 20 and a second sidewall located on the sidewall of the first sidewall, the material of the first sidewall is, for example, silicon nitride, and the material of the second sidewall is, for example, silicon oxide. Of course, the sidewall 26 may also include a three-layer structure, such as silicon oxide-silicon nitride-silicon oxide, or the sidewall 26 may also be other materials or structures. The present invention is not limited to this.

[0039] In one embodiment of the present invention, the upper surface of the sidewall 26 is flush with the upper surface of the second hard mask layer 24. That is, the sidewall 26 only covers the sidewalls of the gate dielectric layer 21, the dummy gate 22, the first hard mask layer 23 and the second hard mask layer 24 in the gate structure 20. The method for forming the sidewall 26 may be to first form a sidewall material layer, the sidewall material layer covers the surface of the substrate 10, the sidewall and the top of the gate structure 20, and then etch the sidewall material layer to remove the sidewall material layer on the surface of the substrate 10 and the top of the gate structure 20, and retain the sidewall material layer on the sidewall of the gate structure 20 as the sidewall 26. During the etching process, the upper surface of the sidewall 26 can be flush with the upper surface of the second hard mask layer 24 by adjusting relevant factors such as etching rate, time, and etching selectivity.

[0040] The upper surface of the sidewall 26 is flush with the upper surface of the second hard mask layer 24. After the amorphous carbon layer 25 is subsequently removed, the upper surface of the gate structure 20 can be ensured to be flush with the upper surface of the sidewall 26, so that when the second hard mask layer 24 and the first hard mask layer 23 are subsequently removed by chemical mechanical polishing, the existence of the sidewall 26 will not affect the polishing, and the polishing amount in the NMOS region I is consistent with that in the PMOS region II, thereby further ensuring that the height of the dummy gate 22 in the NMOS region I is consistent with that in the PMOS region II.

[0041] In step S2, please refer to Figure 4 As shown, a first patterned photoresist layer 30 is formed, and the first patterned photoresist layer 30 covers the substrate 10 and the gate structure 20 in the NMOS region I. That is, the first patterned photoresist layer 30 covers the entire NMOS region I.

[0042] Exemplarily, a photoresist layer is first formed, the photoresist layer covering the substrate 10 and the gate structure 20. Then, the photoresist layer is exposed and developed using a mask to remove the photoresist layer in the PMOS region II, forming the first patterned photoresist layer 30 covering the NMOS region I.

[0043] In step S3, please refer to Figure 4 and Figure 5 As shown, grooves are formed in the substrate 10 at both sides of the gate structure 20 in the PMOS region II, and a partial thickness of the amorphous carbon layer 25 is retained on the second hard mask layer 24 .

[0044] In this embodiment, the substrate 10 on both sides of the gate structure 20 in the PMOS region II may be first etched to form Figure 4 The first groove 41 shown in the figure is in the shape of a square, for example. Then, the substrate 10 in the first groove 41 is etched for the second time to form a Figure 5 The second groove 42 shown is, for example, a sigma shape. The etching conditions of the first etching and the second etching may be different. Of course, the groove finally formed is a sigma groove, and the etching method is not limited thereto.

[0045] refer to Figures 3 to 5 In the process of etching the substrate 10 on both sides of the gate structure 20, the amorphous carbon layer 25 on the top of the gate structure 20 will inevitably be etched, so that the thickness of the amorphous carbon layer 25 is continuously reduced, but it is necessary to ensure that at the end of etching, a part of the thickness of the amorphous carbon layer 25 is still retained on the top of the gate structure 20 to avoid the loss of the second hard mask layer 24 under the amorphous carbon layer 25. The thickness of the amorphous carbon material layer 15 can be adjusted to ensure that the amorphous carbon layer 25 of the remaining thickness remains after the etching is completed.

[0046] The presence of the amorphous carbon layer 25 can prevent the second hard mask layer 24 from being lost during the process of etching to form grooves, and can ensure that the thickness of the second hard mask layer 24 in the PMOS region II is consistent with the thickness of the second hard mask layer 24 in the NMOS region I, thereby ensuring that the height of the pseudo gate 22 in the NMOS region is consistent with that in the PMOS region, thereby avoiding affecting the subsequent electrical performance, thereby ultimately improving the electrical performance of the device.

[0047] In step S4, please refer to Figure 5 and Figure 6 As shown, the first patterned photoresist layer 30 is removed. In this embodiment, the first patterned photoresist layer 30 can be removed by wet etching to avoid affecting the remaining amorphous carbon layer 25. Of course, other removal methods known to those skilled in the art that will not affect the amorphous carbon layer 25 can also be used to remove the first patterned photoresist layer 30.

[0048] In step S5, please refer to Figure 7 As shown, the amorphous carbon layer 25 in the NMOS region I and the PMOS region II is removed by an ashing process to expose the second hard mask layer 24 .

[0049] The thickness of the amorphous carbon layer 25 in the NMOS region I and the PMOS region II is not the same. In this embodiment, the amorphous carbon layer 25 is removed by an ashing process, which does not affect the second hard mask layer 24 below the amorphous carbon layer 25 and the side wall 25 below the side, and there is no problem of residual amorphous carbon layer 25. Exemplarily, the temperature of the ashing process is between 300°C and 350°C. At this temperature, the amorphous carbon layer 25 can be quickly removed without affecting the remaining structures. Of course, the ashing temperature is not limited to this, and can also be determined according to actual process conditions.

[0050] After removing the amorphous carbon layer 25, the upper surface of the side wall 25 is flush with the upper surface of the second hard mask layer 24, that is, in the NMOS region I and the PMOS region II, the upper surface of the side wall 25 is flush with the upper surface of the second hard mask layer 24, so that when the second hard mask layer 24 and the first hard mask layer 23 are subsequently removed by chemical mechanical polishing, the existence of the side wall 26 will not affect the polishing, and the polishing amount in the NMOS region I is consistent with that in the PMOS region II, thereby further ensuring that the height of the pseudo gate 22 in the NMOS region I and the PMOS region II is consistent.

[0051] After removing the amorphous carbon layer 25, the upper surface of the second hard mask layer 24 of the NMOS region I is flush with the upper surface of the second hard mask layer 24 of the PMOS region II, so that when chemical mechanical polishing is subsequently used to remove the second hard mask layer 24 and the first hard mask layer 23, the polishing amount in the NMOS region I is consistent with that in the PMOS region II, thereby ensuring that the height of the pseudo gate 22 in the NMOS region I and the PMOS region II is consistent after chemical mechanical polishing.

[0052] In one embodiment of the present invention, when the cross-sectional widths of the pseudo gates 22 in different gate structures 20 are different, or in other words, the pseudo gates 22 have different cross-sectional widths, when the amorphous carbon layer 25 is not provided in the prior art, the thickness of the second hard mask layer 24 in the PMOS region II will be consumed in the process of etching to form the groove, resulting in different thicknesses of the second hard mask layer 24 in the two regions. When removing the second hard mask layers 24 with different thicknesses, chemical mechanical polishing cannot be used, and wet etching and other methods are required to remove them. When removing the second hard mask layer 24 on the pseudo gate 22 with a large width, a large cleaning force is required, which will cause serious damage to the sidewall 26 of the pseudo gate 22 with a small width. In the actual process, in order to remove the second hard mask layer 24 on the pseudo gate 22 with a large width, a mask, yellow light, etc. are required, which will increase the process and increase the process cost. In the embodiment of the present invention, the provision of the amorphous carbon layer 25 and the ashing removal of the remaining amorphous carbon layer 25 are not limited by the different cross-sectional widths of the pseudo gate 22 and will not cause damage to the remaining structures. Therefore, there is no need to add masks and other processes, thereby saving process costs.

[0053] In one embodiment of the present invention, after removing the amorphous carbon layer 25, the manufacturing method further includes: cleaning the substrate 10, filling silicon germanium in the second groove 42 to form an epitaxial structure, and then removing the second hard mask layer 24 and the first hard mask layer 23 in the NMOS region I and the PMOS region II by chemical mechanical polishing. Since the thickness of the second hard mask layer 24 in the two regions is consistent, the height of the dummy gate 22 in the two regions can be ensured to be consistent after chemical mechanical polishing.

[0054] In the method for manufacturing a semiconductor device provided by the present invention, a substrate 10 is first provided, the substrate 10 includes an NMOS region I and a PMOS region II, a gate structure 20 is formed on the substrate 10 in the NMOS region I and the PMOS region II, the gate structure 20 includes a gate dielectric layer 21, a dummy gate 22, a first hard mask layer 23, a second hard mask layer 24 and an amorphous carbon layer 25 sequentially formed on the substrate 10, and a sidewall 26 is formed on the sidewall of the gate structure 20; then a first patterned photoresist layer 30 covering the NMOS region I is formed, and then grooves are formed in the substrate 10 on both sides of the gate structure 20 in the PMOS region II, and a part of the thickness of the amorphous carbon layer 25 is retained on the second hard mask layer 24, and then the first patterned photoresist layer 30 is removed, and then an ashing process is used to remove the amorphous carbon layer 25 in the NMOS region I and the PMOS region II. The unexpected effect of the present invention is that an amorphous carbon layer 25 is formed on the second hard mask layer 24. In the process of forming grooves in the substrate 10 on both sides of the gate structure 20 in the PMOS region II, the amorphous carbon layer 25 is used to protect the second hard mask layer 24 below from being thinned. After the remaining amorphous carbon layer 25 is subsequently removed, the thickness of the second hard mask layer 24 in the NMOS region I and the PMOS region II can be ensured to be consistent, thereby ensuring that the height of the pseudo gate 22 in the NMOS region I and the PMOS region II is consistent, thereby improving the electrical performance of the device. At the same time, removing the remaining amorphous carbon layer 25 through the ashing process will not affect the remaining structures, there will be no residual problems, and will not cause other effects on the semiconductor device.

[0055] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above. Figure 7 As shown, the semiconductor device comprises: A substrate 10, wherein the substrate 10 includes an NMOS region I and a PMOS region II, a gate structure 20 is formed on the substrate 10 in the NMOS region I and the PMOS region II, the gate structure 20 includes a gate dielectric layer 21, a dummy gate 22, a first hard mask layer 23, a second hard mask layer 24 and an amorphous carbon layer 25 sequentially formed on the substrate 10, and a sidewall 26 is formed on the sidewall of the gate structure 20; A second groove 42 is located in the substrate 10 on both sides of the gate structure 20 in the PMOS region II; In the gate structure 20 , the thickness of the second hard mask layer 24 in the NMOS region I is consistent with that of the second hard mask layer 24 in the PMOS region II.

[0056] In one embodiment of the present invention, the cross-sectional widths of the dummy gates 22 in different gate structures 20 are different.

[0057] In one embodiment of the present invention, the upper surface of the spacer 26 is flush with the upper surface of the second hard mask layer 24 .

[0058] In summary, in the semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, the substrate comprising an NMOS region and a PMOS region, a gate structure is formed on the substrate in the NMOS region and the PMOS region, the gate structure comprises a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer sequentially formed on the substrate, and a sidewall of the gate structure is formed with a sidewall; then a first patterned photoresist layer covering the NMOS region is formed, and then grooves are formed in the substrate on both sides of the gate structure in the PMOS region, and a partial thickness of the amorphous carbon layer is retained on the second hard mask layer, and then the first patterned photoresist layer is removed, and then an ashing process is used to remove the amorphous carbon layer in the NMOS region and the PMOS region. The unexpected effect of the present invention is that an amorphous carbon layer is formed on the second hard mask layer, and in the process of forming grooves in the substrate on both sides of the gate structure in the PMOS region, the amorphous carbon layer is used to protect the second hard mask layer below from being thinned. After the remaining amorphous carbon layer is subsequently removed, the thickness of the second hard mask layer in the NMOS region and the PMOS region can be guaranteed to be consistent, thereby ensuring that the height of the pseudo gate in the NMOS region and the PMOS region is consistent, thereby improving the electrical performance of the device. At the same time, removing the remaining amorphous carbon layer through the ashing process will not affect the remaining structures, there will be no residual problems, and will not cause other effects on the semiconductor device.

[0059] In addition, the cross-sectional widths of the pseudo gates in different gate structures may be different. An amorphous carbon layer is used to protect the second hard mask layer and an ashing process is used to remove it. This is not limited by the different cross-sectional widths of the pseudo gates. Compared with the prior art, this can save process steps and process costs.

[0060] Moreover, the upper surface of the side wall is flush with the upper surface of the second hard mask layer. After removing the remaining amorphous carbon layer, the upper surface of the side wall is flush with the upper surface of the gate structure. Therefore, when chemical mechanical polishing is subsequently used to remove the second hard mask layer and the first hard mask layer, the existence of the side wall will not affect the polishing. The polishing amount in the NMOS region is consistent with that in the PMOS region, thereby further ensuring that the height of the pseudo gates in the NMOS region and the PMOS region are consistent.

[0061] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that The following steps are involved: Providing a substrate, the substrate comprising an NMOS region and a PMOS region, a gate structure is formed on the substrate in both the NMOS region and the PMOS region, the gate structure comprises a gate dielectric layer, a dummy gate, a first hard mask layer, a second hard mask layer and an amorphous carbon layer sequentially formed on the substrate, and a sidewall of the gate structure is formed with a sidewall; Forming a first patterned photoresist layer, wherein the first patterned photoresist layer covers the substrate and the gate structure in the NMOS region; forming grooves in the substrate at both sides of the gate structure in the PMOS region, and retaining a partial thickness of the amorphous carbon layer on the second hard mask layer; removing the first patterned photoresist layer; as well as The amorphous carbon layer in the NMOS region and the PMOS region is removed by an ashing process.

2. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The cross-sectional widths of the dummy gates in different gate structures are different.

3. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that In the step of providing a substrate, an upper surface of the spacer is flush with an upper surface of the second hard mask layer.

4. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that After the amorphous carbon layer is removed by an ashing process, the upper surface of the spacer is flush with the upper surface of the second hard mask layer.

5. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that After the amorphous carbon layer is removed by an ashing process, the upper surface of the second hard mask layer in the NMOS region is flush with the upper surface of the second hard mask layer in the PMOS region.

6. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The temperature of the ashing process is between 300°C and 350°C.

7. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The method of forming the gate structure includes: forming a gate dielectric material layer, a dummy gate material layer, a first hard mask material layer, a second hard mask material layer and an amorphous carbon material layer on the substrate in sequence; forming a second patterned photoresist layer, wherein the second patterned photoresist layer covers the area where the gate structure is to be formed and exposes the remaining area; Using the second patterned photoresist layer as a mask, sequentially etching the amorphous carbon material layer, the second hard mask material layer, the first hard mask material layer, the dummy gate material layer, and the gate dielectric material layer until a portion of the substrate is exposed; and The second patterned photoresist layer is removed.

8. The method for manufacturing a semiconductor device according to claim 7, It is characterized in that The first patterned photoresist layer and the second patterned photoresist layer are removed by a wet etching process.

9. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that After removing the amorphous carbon layer, the manufacturing method further comprises: filling silicon germanium in the groove to form an epitaxial structure.

10. A semiconductor device, It is characterized in that The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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