Memristor-based brain-like neuromorphic circuit architecture

Abstract

The invention discloses a memristor-based brain-like neural morphological circuit architecture, which comprises a plurality of operational amplifiers, a plurality of resistors and a plurality of brain-like neural network circuit system units with row and column structures, the brain-like neural network circuit system unit comprises a voltage source, a memristor and an NMOS (N-channel Metal Oxide Semiconductor) tube; the voltage source is used for providing input for the cranial nerve-like morphological circuit architecture; the NMOS transistor is used for regulating the positive and negative of the synaptic weight represented by the memristor; the last row of cranial nerve-like network circuit system units of the cranial nerve-like morphological circuit architecture are connected with an arithmetic unit and a resistor, and the resistor is connected between the operational amplifiers. The electrical behavior of the metal oxide memristor is better shown through the improved memristor model, and compared with other traditional architectures, the cranial nerve-like morphological circuit architecture built based on the memristor model greatly reduces the scale of the circuit architecture, reduces the energy loss of system operation, and improves the reliability of the system. And the entity cost is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and relates to metal oxide memristor model simulation, brain-like neuromorphic circuits, and in particular to a brain-like neuromorphic circuit architecture based on memristors. Background Art

[0002] Artificial neural networks are inspired by the electrochemical communication between human brain neurons and other biological neural systems. Their application reveals power efficiency and good application prospects in very low energy consumption and mobile electronic solutions and devices. The memristor predicted by Leon Chua is a two-port electronic passive device that can store charge passing through its structure. Its conductance value is adjusted by applying an electrical signal such as an electric pulse or a sinusoidal voltage. Therefore, neuromorphic integrated chips based on memristors can perform complex calculations quickly and efficiently with minimal power consumption. Some electronic synapses based on a single memristor element and a MOS transistor only guarantee positive weights. More complex schematics use multiple memristors and many operational amplifiers for each synapse to work together to simulate positive, negative and zero synaptic weights, but increase the area and power consumption of the neural network simulation circuit. Therefore, the present invention proposes a brain-like neuromorphic circuit architecture based on memristors to simulate neural network weights and realize neural network forward propagation. Summary of the invention

[0003] In order to solve the above technical problems, the present invention proposes a brain-like neuromorphic circuit architecture based on memristors to solve the problems existing in the above-mentioned prior art.

[0004] To achieve the above-mentioned purpose, the present invention provides a brain-like neuromorphic circuit architecture based on a memristor, comprising a plurality of operational amplifiers, a plurality of resistors, and a plurality of brain-like neural network circuit system units having a row-column structure; the brain-like neural network circuit system unit comprises a voltage source, a memristor, and an NMOS tube; the memristor has a threshold voltage and an initial resistance value;

[0005] The voltage source is used to provide input for the brain-like neuromorphic circuit architecture;

[0006] The NMOS tube is used to control the positive or negative value of the synaptic weight represented by the memristor;

[0007] The last row of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is connected with operators and resistors, and resistors are connected between operational amplifiers.

[0008] Optionally, the number of rows and columns of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is the same as the size of the output layer of the simulated neural network.

[0009] Optionally, the brain-like neural network circuit system unit includes two voltage sources, a memristor, and two NMOS tubes;

[0010] The TE end of the memristor is connected to the output end of a single voltage source, the BE end of the memristor is connected to the sources of two NMOS tubes respectively, and the gates of the two NMOS tubes are connected to another voltage source.

[0011] Optionally, the drains of the two NMOS tubes are respectively connected to the drains of different NMOS tubes in the next row of brain-like neural network circuit system units, and the last row of brain-like neural network circuit system units is connected to an operator and a resistor.

[0012] Optionally, the operational amplifier is divided into a positive weight amplifier and a negative weight amplifier, the inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be positive, the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be negative, the positive and negative power supply input terminals of the positive weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, the positive and negative power supply input terminals of the negative weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, and the two voltage sources are in a connected relationship.

[0013] Optionally, in a single column of the brain-like neuromorphic circuit architecture, a resistor is connected between the output of the positive weight amplifier and the inverting input of the negative weight amplifier; a resistor is connected between the inverting input of the positive weight amplifier and the output of the positive weight amplifier; the positive input of the positive weight amplifier is connected to the positive input of the negative weight amplifier; and a resistor is connected between the inverting input of the negative weight amplifier and the output of the negative weight amplifier.

[0014] Optionally, the NMOS tubes are all NMOS tubes with an internal resistance of 1 ohm.

[0015] Optionally, the memristors in each row of brain-like neural network circuit system units are connected to the same voltage source.

[0016] Optionally, a mathematical model of the memristor model is obtained based on two key equations, which are as follows:

[0017] i=v·[R ON x+R OFF (1-x)] -1

[0018] x=k·sin 2 (πx)·v m ·stp(|v|-v thr )

[0019] The first equation is the iv relationship, and the second equation is the relationship between the time derivative of the state variable x and the memristor current i. Among them, i is the memristor current, k is a constant that depends on the physical parameters of the memristor nanostructure, m is an odd and integer index, v is the input voltage, R on The memristor is in the on-resistance state, R off The memristor is in the on-resistance state.

[0020] Compared with the prior art, the present invention has the following advantages and technical effects:

[0021] The present invention better demonstrates the electrical behavior of metal oxide memristors through an improved memristor model. The brain-like neuromorphic circuit architecture built based on this memristor model greatly reduces the scale of the circuit architecture, reduces the energy loss of system operation, and greatly reduces the physical cost problem, compared with other traditional memristor storage and computing integrated architectures that rely on two memristors as differential pairs to simulate the positive and negative values ​​of synaptic weights. It provides a new idea for storage and computing integrated chips in terms of saving energy and reducing area. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0023] Figure 1 A test IV curve of a memristor model according to an embodiment of the present invention;

[0024] Figure 2 This is a diagram of a single-row system unit architecture of a brain-like neuromorphic circuit according to an embodiment of the present invention;

[0025] Figure 3 This is a general architecture diagram of a brain-like neural network circuit according to an embodiment of the present invention;

[0026] Figure 4 Graph showing the output electrical signals of the brain-like neuromorphic circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0029] Embodiment 1

[0030] like Figure 1-4 As shown, this embodiment provides a brain-like neuromorphic circuit architecture based on a memristor, including:

[0031] In order to better build a brain-like neural network circuit model, the memristor model should have the following characteristics: simple operation, high working speed, good accuracy, and allow precise and detailed fine-tuning process. The process of simulating neural networks with memristor array circuits is mainly divided into two stages: weight input and matrix operation of forward propagation. Since both processes require electrical signal input, the memristor model needs to perform conductivity modulation according to its electrical characteristic curve to change its conductivity in the weight input stage, and needs to behave as a stable resistor device to perform matrix operation in the forward propagation stage, so the threshold voltage V is added to the memristor model code. thr and the initial resistance m0. In this model, the threshold voltage is set to 3V. In the conductivity modulation stage, an input voltage greater than 3V is used to modulate the conductivity of the memristor to the corresponding weight according to its electrical curve. In the forward propagation process, the resistance value represented by the memristor model needs to stably represent the conductance value modulated in the previous stage.

[0032] The mathematical model of the memristor model is based on the following two key equations.

[0033] i=v·[R ON x+R OFF (1-x)] -1

[0034] x=k·sin 2 (πx)·v m ·stp(|v|-v thr )

[0035] The first relation provides the iv relation, and the second one connects the time derivative of the state variable x and the memristor current i (or memristor voltage v). Where k is a constant that depends on the physical parameters of the memristor nanostructure, and m is an odd and integer exponent. In addition, the initial resistance R is set in the source code. init , the memristor model has a simple mathematical structure, and the applied Hann window function is independent of the terminal state problem. The resistance of the memristor has two extreme values, usually denoted by R on (turn on resistance state) and R off (Closed resistance state). If the input voltage v is lower than the activation threshold voltage V thr, then it is the time derivative of the state variable. When x=dx / dt is zero, the memristor behaves as a simple linear resistor device with a constant conductance. This operating mode is used to adjust the function of metal oxide memristors in neural networks after completing the training process and establishing synaptic weights.

[0036] Among them, the threshold voltage V thr Set to 3, turn on the resistor R on Set to 10, turn off the resistor R off Set to 16K, constant k to 10, exponent m to 3, and initial resistance m0 to 300.

[0037] The classification neural network in this embodiment is a binary classification neural network, and the classification content is vehicles and pedestrians. The constructed brain-like neural network circuit simulates the output layer of the binary classification neural network.

[0038] Based on the above content, the brain-like neural network circuit system unit used to simulate the output layer of the binary classification neural network is constructed as follows:

[0039] Step 1: Use a voltage source as the input segment of the neural network, and use the output voltage of the voltage source to represent the input data in the neural network. Its numerical value is proportionally reduced from the input end of the neural network to a range of 0 to 3.

[0040] Step 2: The output end of the voltage source is directly connected in series with the TE end (i.e., the top electrode) of a single memristor. After the input voltage of the voltage source is input, the resistance of the memristor represents the synaptic weight in the neural network. The input voltage of the voltage source and the conductivity of the memristor are operated according to Ohm's law, that is, multiplication is performed. The signal output from the BE end (i.e., the bottom electrode) of the memristor is the output signal of the multiplication operation.

[0041] Step 3: The BE end of the memristor is connected in parallel with the source electrodes of two MOS tubes. The two MOS tubes are used to adjust the positive and negative values ​​of the synaptic weights represented by the memristor in the circuit system unit. During operation, only one MOS tube stack is opened to control the positive and negative values ​​of the synaptic weights of the memristor.

[0042] Step 4: The two MOS tubes are respectively connected to the reverse input terminals of the two amplifiers. The amplifier connected to the drain of the MOS tube that controls the positive weight of the memristor is the positive weight amplifier of the system unit, and the other is called the negative weight amplifier. Both amplifiers are respectively connected to a resistor with a resistance value of 1K ohms, and the output of the positive weight amplifier is connected to the inverting input terminal of the negative weight amplifier after being connected in series with a resistor with a resistance value of 100 ohms. The output of the negative reverse amplifier is the output of the neural network system unit.

[0043] In this embodiment, a brain-like neuromorphic circuit architecture based on memristor is as follows Figure 3As shown, it includes several operational amplifiers, several resistors, and several brain-like neural network circuit system units with row and column structures; the brain-like neural network circuit system units include a voltage source, a memristor, and an NMOS tube;

[0044] The voltage source is used to provide input for the brain-like neuromorphic circuit architecture;

[0045] The NMOS tube is used to control the positive or negative value of the synaptic weight represented by the memristor;

[0046] The last row of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is connected with operators and resistors, and resistors are connected between operational amplifiers.

[0047] Preferably, the number of rows and columns of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is the same as the size of the output layer of the simulated neural network.

[0048] Preferably, the brain-like neural network circuit system unit includes two voltage sources, a memristor, and two NMOS tubes;

[0049] The TE end of the memristor is connected to the output end of a single voltage source, the BE end of the memristor is connected to the sources of two NMOS tubes respectively, and the gates of the two NMOS tubes are connected to another voltage source.

[0050] Preferably, the drains of the two NMOS tubes are respectively connected to the drains of different NMOS tubes in the next row of brain-like neural network circuit system units, and the last row of brain-like neural network circuit system units is connected to an operator and a resistor.

[0051] Specifically, the brain-like neural network circuit system unit is shown in Figure 2 , the TE end of the memristor U1 is connected to the output end of the voltage source V1, the BE end of the memristor U1 is connected to the source of the NMOS tube M1 and the NMOS tube M2 respectively, and the gates of the two NMOS tubes are connected to the voltage source V15. The memristors in each row of the brain-like neural network circuit system unit are connected to the same voltage source.

[0052] like Figure 3 As shown, the drains of the NMOS tube M1 and the NMOS tube M2 are respectively connected to the drains of the NMOS tube M5 and the NMOS tube M6 in the next row of brain-like neural network circuit system units.

[0053] Preferably, the operational amplifier is divided into a positive weight amplifier and a negative weight amplifier, the inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be positive, the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be negative, the positive and negative power supply input terminals of the positive weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, the positive and negative power supply input terminals of the negative weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, and the two voltage sources are in a connection relationship.

[0054] Preferably, in a single column of the brain-like neuromorphic circuit architecture, a resistor is connected between the output end of the positive weight amplifier and the inverting input end of the negative weight amplifier; a resistor is connected between the inverting input end of the positive weight amplifier and the output end of the positive weight amplifier; the positive input end of the positive weight amplifier is connected to the positive input end of the negative weight amplifier; and a resistor is connected between the inverting input end of the negative weight amplifier and the output end of the negative weight amplifier.

[0055] Specifically, the structure of the last row of brain-like neural network circuit system units, operational amplifiers and resistors is shown in Figure 3 ,

[0056] The operational amplifier is divided into a positive weight amplifier U25 and a negative weight amplifier U26. The inverting input terminal of the positive weight amplifier U25 is connected to the drain of the NMOS tube M45 that controls the memristor weight to be positive. The inverting input terminal of the negative weight amplifier U26 is connected to the drain of the NMOS tube M46 that controls the memristor weight to be negative. The positive and negative power supply input terminals of the positive weight amplifier U25 are respectively connected in phase with the positive pole of the voltage source V14 and the negative pole of another voltage source V38. The positive and negative power supply input terminals of the negative weight amplifier U26 are respectively connected in phase with the positive pole of the voltage source V14 and the negative pole of another voltage source V38. The two voltage sources are connected positively and negatively.

[0057] In a single row of the brain-like neuromorphic circuit architecture, a resistor R1 is connected between the output end of the positive weight amplifier U25 and the inverting input end of the negative weight amplifier U26; a resistor R2 is connected between the inverting input end and the output end of the positive weight amplifier U25; the positive input end of the positive weight amplifier U25 is connected to the positive input end of the negative weight amplifier U26; and a resistor R3 is connected between the inverting input end of the negative weight amplifier and the output end of the negative weight amplifier.

[0058] Preferably, all NMOS tubes have an internal resistance of 1 ohm.

[0059] The output layer size of the binary classification neural network in this embodiment is 500*2, so the circuit proposed by the present invention is constructed by the system units composed of the above steps one, two, and three according to the scale of 500 rows and 2 columns, and the drain of the MOS tube of the system unit in each row is connected to the drain of the MOS tube of the system unit in the next row, and the drain of the two groups of MOS tubes in the last row is constructed according to the above step four, and the outputs of its two negative weight amplifiers respectively represent the people and vehicles in the classification content, and the output value is the output of the binary classification neural network simulated by this type of brain neuromorphic circuit.

[0060] When simulating the classification neural network in the brain-like neuromorphic circuit architecture, first use the pictures of people and vehicles as the input of the classification neural network on the computer, output the values ​​of 500 input units and 1000 weights of the output layer of the neural network, and then in the memristor modulation stage, follow the following steps: Figure 1 The IV curve of the memristor model shown uses the sinusoidal voltage output by the voltage source to modulate the conductivity of the memristor model, modulating the conductivity of all memristors to the 1000 weights output from the neural network in advance, and then in the forward propagation stage, first the true value of the input unit obtained by the test is proportionally reduced to the interval between 0 and 3, and then used as the output voltage value of the 500 voltage sources in the circuit architecture in turn. In the circuit operation stage, the 500 voltage sources are simultaneously input into the memristor array to perform matrix addition operations based on Ohm's law and Kirchhoff's law, and finally the electrical signals are obtained at the two output ports of the circuit architecture, as shown in FIG. Figure 4 The person or vehicle represented by the larger output port of the two electrical signals is taken as the classification result of the neuromorphic circuit architecture.

[0061] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A brain-like neuromorphic circuit architecture based on memristors, characterized in that: It includes several operational amplifiers, several resistors, and several brain-like neural network circuit system units with row and column structures; the brain-like neural network circuit system units include a voltage source, a memristor, and an NMOS tube; the memristor has a threshold voltage and an initial resistance value; The voltage source is used to provide input for the brain-like neuromorphic circuit architecture; The NMOS tube is used to control the positive or negative value of the synaptic weight represented by the memristor; The last row of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture is connected with operators and resistors, and resistors are connected between operational amplifiers.

2. The memristor-based brain-like neuromorphic circuit architecture according to claim 1, characterized in that: The number of rows and columns of brain-like neural network circuit system units in the brain-like neuromorphic circuit architecture are the same as the size of the output layer of the simulated neural network.

3. The memristor-based brain-like neuromorphic circuit architecture according to claim 2, characterized in that: The brain-like neural network circuit system unit includes two voltage sources, a memristor, and two NMOS tubes; The TE end of the memristor is connected to the output end of a single voltage source, the BE end of the memristor is connected to the sources of two NMOS tubes respectively, and the gates of the two NMOS tubes are connected to another voltage source.

4. The memristor-based brain-like neuromorphic circuit architecture according to claim 3, characterized in that: The drains of the two NMOS tubes are respectively connected to the drains of different NMOS tubes in the next row of brain-like neural network circuit system units, and the last row of brain-like neural network circuit system units is connected to an operator and a resistor.

5. The memristor-based brain-like neuromorphic circuit architecture according to claim 4, characterized in that: The operational amplifier is divided into a positive weight amplifier and a negative weight amplifier. The inverting input terminal of the positive weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be positive, and the inverting input terminal of the negative weight amplifier is connected to the drain of the NMOS tube that controls the memristor weight to be negative. The positive and negative power supply input terminals of the positive weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, and the positive and negative power supply input terminals of the negative weight amplifier are respectively connected in phase with the positive pole of the voltage source and the negative pole of another voltage source, and the two voltage sources are in a connection relationship.

6. The memristor-based brain-like neuromorphic circuit architecture according to claim 5, characterized in that: In a single row of the brain-like neuromorphic circuit architecture, a resistor is connected between the output of the positive weight amplifier and the inverting input of the negative weight amplifier; a resistor is connected between the inverting input of the positive weight amplifier and the output of the positive weight amplifier; the positive input of the positive weight amplifier is connected to the positive input of the negative weight amplifier; A resistor is connected between the inverting input terminal of the negative weight amplifier and the output terminal of the negative weight amplifier.

7. The memristor-based brain-like neuromorphic circuit architecture according to claim 3, characterized in that: The NMOS tubes are all NMOS tubes with an internal resistance of 1 ohm.

8. The memristor-based brain-like neuromorphic circuit architecture according to claim 1, characterized in that: The memristors in each row of brain-like neural network circuit system units are connected to the same voltage source.

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