Photoelectric chip and manufacturing method thereof

Abstract

The invention discloses a photoelectric chip and a manufacturing method thereof. The photoelectric chip comprises a triode group array, a conductive substrate and a first insulating layer, the triode group array is composed of a plurality of triode groups which are distributed in an array mode. The triode group comprises a photoelectric triode, at least one common triode and a second insulating layer; the photoelectric triode and the common triode are isolated from each other through a second insulating layer; and the collector of the photoelectric triode is connected with the collectors of all the common triodes through a substrate to form the collector of the triode group. The structure is simple, the triode group comprises photoelectric triodes and common triodes, the number of the common triodes can be adjusted to adjust the photocurrent and the photocurrent / dark current ratio, and the device can be used for different solutions; the two triodes are manufactured at the same time, so that the process steps are reduced and the cost is reduced; relatively high light current is realized by relatively weak light, so that damage to cells due to high light intensity in the photoelectric tweezers is avoided; the photocurrent and the dark current are independently controlled, and the device performance and the application range are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an optoelectronic chip and a manufacturing method thereof. Background Art

[0002] Currently, transistor-based photoelectric tweezers technology has been applied to manipulate (e.g., select or move) micro-objects such as cells, microspheres, etc. The typical structure of this type of photoelectric tweezers device is to set a microfluidic channel between two upper and lower electrodes, where the upper electrode is usually a glass plate coated with indium tin oxide (ITO), and the lower electrode is a metal electrode, on which a phototransistor array is arranged to replace the ordinary photoelectric layer. When patterned light is irradiated on a specific area on the phototransistor array, the activated transistor allows current to pass, thereby forming a non-uniform electric field in the microfluidic channel, generating a dielectrophoresis (DEP) force that can manipulate micro-objects.

[0003] In the prior art, the magnitude of the DEP force is subject to factors such as the volume of the controlled micro-object and the medium in which it is located. For a given substance to be tested, increasing the illumination intensity and / or illumination area of ​​the phototransistor can obtain a larger photocurrent, which is conducive to establishing a more significant non-uniform electric field, thereby generating a larger DEP manipulation force. However, since too high an illumination intensity may damage micro-objects (such as cells), in order to increase the photocurrent, it is more inclined to increase the photoelectric conversion efficiency.

[0004] Document CN107223074B discloses a transistor optical tweezer and a microfluidic device thereof. In the scheme, each transistor structure includes a lateral transistor and a vertical transistor. In each transistor structure, a P-type base region surrounds an N-type emitter region, an N-type collector region surrounds a P-type base region, and both the base region and the collector region include a lateral part and a longitudinal part. Compared with optical tweezers with only longitudinal transistors, under the same light intensity, lateral current and longitudinal current are generated simultaneously. The additional lateral transistor is said to increase the intensity of the generated current, thereby allowing more robust control of micro-objects.

[0005] However, the photocurrent and photocurrent / dark current ratio generated by this transistor structure are still unsatisfactory in some applications. For example, the simulated value of the photocurrent / dark current ratio of this transistor structure is at the level of 10^4, which does not meet the requirements of microfluidic devices. In addition, its structure is complex and the production cost is high.

[0006] Therefore, how to design a transistor optoelectronic chip with a high photocurrent / dark current ratio, simple structure, and simple manufacturing process is a technical problem to be solved. Summary of the invention

[0007] Based on this, it is necessary to provide an optoelectronic chip and a method for manufacturing the same in response to the existing problems.

[0008] The embodiment of the present application provides an optoelectronic chip, including a triode group array, a conductive substrate and a first insulating layer;

[0009] Wherein, the triode group array is composed of a plurality of triode groups distributed in an array;

[0010] Among them, the triode group includes a phototransistor, at least one ordinary triode and a second insulating layer; the phototransistor and the ordinary triode are isolated from each other by the second insulating layer; the collector of the phototransistor is connected to the collectors of all the ordinary triodes through a conductive substrate to form the collector of the triode group.

[0011] Preferably, when one of the triode groups includes one of the phototransistors and at least two of the common triodes;

[0012] The emitter of the phototransistor is connected to the base of all common transistors; the emitters of all common transistors are all electrically connected to form the emitter of the transistor group;

[0013] or

[0014] The emitter of the phototransistor is connected to the base of an ordinary transistor, the emitter of the ordinary transistor is connected to the base of the next ordinary transistor until the bases of all ordinary transistors are electrically connected, and the emitter of the last ordinary transistor that is not electrically connected to other ordinary transistors constitutes the emitter of the transistor group.

[0015] Preferably, the transistor group is of NPN type or PNP type.

[0016] Preferably, the longitudinal thickness of the emitter of the triode group ranges from 10 nm to 500 nm;

[0017] The emitter of the triode group is N-type or P-type doped and is composed of one or more elements of antimony, arsenic, and phosphorus;

[0018] The doping concentration range of the emitter of the triode group is 10 18 cm -3 -10 21 cm -3 .

[0019] Preferably, the longitudinal thickness of the base of the triode group is in the range of 200nm-10000nm;

[0020] The base of the triode group is N-type or P-type doped and is composed of one or more elements selected from boron, aluminum, beryllium, zinc, and cadmium;

[0021] The doping concentration range of the base of the triode group is 1015 cm -3 -10 18 cm -3 .

[0022] Preferably, the longitudinal thickness of the collector electrode of the triode group is in the range of 300nm-30000nm;

[0023] The collector of the triode group is N-type or P-type doped and is composed of one or more elements of antimony, arsenic, and phosphorus.

[0024] Preferably, the resistivity of the collector of the transistor group is in the range of 5Ω·cm-10Ω·cm.

[0025] Preferably, the first insulating layer and the second insulating layer are made of silicon oxide material or a composite layer material consisting of silicon oxide and silicon nitride.

[0026] Preferably, the thickness of the conductive substrate ranges from 100 μm to 700 μm;

[0027] The resistivity of the conductive substrate is in the range of 0.01 Ω·cm-0.2 Ω·cm.

[0028] Another embodiment of the present application discloses a method for manufacturing an optoelectronic chip, comprising the following steps:

[0029] S1: forming an epitaxial structure on a conductive substrate, wherein the epitaxial structure constitutes a collector region;

[0030] S2: implanting specific elements into the surface of the epitaxial structure and performing thermal annealing to form a base region;

[0031] S3: coating photoresist on the base region, exposing it through a photolithography mask to open an emitter window, and performing element doping to form a first region;

[0032] S4: removing the photoresist, doping elements, and annealing in the first region of the transistor group to form a second region;

[0033] S5: coating a photoresist, exposing a photomask, doping with elements, removing the photoresist, and annealing the second region of the transistor group to form an emitter region;

[0034] S6: removing the photoresist in the area between the common transistor and the phototransistor by photolithography, and then performing silicon etching to a depth of the substrate layer to isolate the transistors;

[0035] S7: depositing a passivation layer on the surface of the structure formed in step S6;

[0036] S8: coating a photoresist on the surface of the passivation layer, removing the photoresist on the surface of the emitter region by photolithography exposure, and then ion etching the passivation layer to expose the emitter and form a contact hole;

[0037] S9: depositing a metal layer by magnetron sputtering, and connecting the emitters of each transistor by spin coating photoresist, photolithography, development, and etching;

[0038] S10: depositing a passivation layer again, and performing spin coating of photoresist, photolithography, development, and etching of the passivation layer to expose the emitter of the transistor.

[0039] Compared with the prior art, the technical solution disclosed in the present invention has the following beneficial effects:

[0040] (1) The optoelectronic chip has a simple structure and is composed of a transistor array including a plurality of transistor groups distributed in an array. Each transistor group includes a phototransistor and at least one ordinary transistor. Therefore, the photocurrent and the photocurrent / dark current ratio of the optoelectronic chip can be adjusted by adjusting the number of ordinary transistors, and can be effectively applied to the use of solutions with different conductivity in the optoelectronic tweezers chip; (2) The phototransistor and the ordinary transistor are manufactured at the same time, which not only reduces the process steps but also reduces the manufacturing cost; (3) The excellent optoelectronic properties of the present invention can achieve higher photocurrents with weaker light. In the application of optoelectronic tweezers, the risk of cell damage caused by too high light intensity is avoided; (4) By separating the light absorption and current amplification functions, independent control of the photocurrent and dark current is achieved, thereby improving the performance and application range of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] By referring to the following drawings, the exemplary embodiments of the present invention can be more completely understood. The drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present invention and do not constitute a limitation of the present invention. In the drawings, the same reference numerals generally represent the same parts or steps.

[0042] Figure 1 A circuit diagram of a transistor group of an optoelectronic chip provided according to an exemplary embodiment of the present application;

[0043] Figure 2 A circuit diagram of a transistor group of an optoelectronic chip provided according to another exemplary embodiment of the present application;

[0044] Figure 3 A circuit diagram of a transistor array of an optoelectronic chip provided according to an exemplary embodiment of the present application;

[0045] Figure 4A circuit diagram of a transistor group of an optoelectronic chip provided according to another exemplary embodiment of the present application;

[0046] Figure 5 A circuit diagram of a transistor array of an optoelectronic chip provided according to another exemplary embodiment of the present application;

[0047] Figure 6-14 A schematic diagram of steps of a method for manufacturing an optoelectronic chip according to another exemplary embodiment of the present application;

[0048] Fig.15 A top view of an optoelectronic chip provided according to another exemplary embodiment of the present application;

[0049] Fig.16 A side view of an optoelectronic chip provided according to another exemplary embodiment of the present application;

[0050] Fig.17 The figure is a top view of an optoelectronic chip provided according to another exemplary embodiment of the present application.

[0051] Reference numerals

[0052] 1-conductive substrate, 2-epitaxial structure, 3-base region, 4-photoresist, 5-emitter window, 6-first region, 7-second region, 8-passivation layer, 9-contact hole, 10-metal layer. DETAILED DESCRIPTION

[0053] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0054] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0055] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0057] Example 1

[0058] An embodiment of the present application provides an optoelectronic chip, which is described below with reference to the accompanying drawings.

[0059] Some embodiments of the present application provide an optoelectronic chip including a transistor group array, a conductive substrate and a first insulating layer.

[0060] The transistor group array of this embodiment is composed of a plurality of transistor groups distributed in an array.

[0061] Specifically, Figure 1 A schematic diagram of the circuit structure of the transistor group of this embodiment is given. The transistor group is composed of a phototransistor and a common transistor. In this embodiment, only the NPN transistor is used as an example for description.

[0062] The phototransistor and the common transistor are isolated from each other by a second insulating layer; the collector of the phototransistor is connected with the collector of the common transistor through a conductive substrate to form the collector of the transistor group, and the emitter of the common transistor forms the emitter of the transistor group.

[0063] Specifically, the phototransistor is also called a photosensitive transistor. Its current is controlled by external light and is a semiconductor photoelectric device. The phototransistor is a transistor that is equivalent to a phototransistor connected between the base and collector of the transistor. The current of the phototransistor is equivalent to the base current of the transistor. Because of its current amplification effect, the phototransistor is much more sensitive than the phototransistor and can output a large photocurrent at the collector.

[0064] Phototransistors have a variety of packaging structures such as plastic packaging, metal packaging (with a glass mirror window on the top), ceramic, and resin. The pins are divided into two-pin and three-pin types. Generally, the pins of a two-pin phototransistor are the collector and emitter, and the optical window is the base.

[0065] When there is no light, the phototransistor is in the cut-off state and no electrical signal is output. When the light signal shines on the base of the phototransistor, the phototransistor is turned on, firstly the photoelectric conversion is realized through the phototransistor, then the photocurrent is amplified through the transistor, and the amplified electrical signal is output from the emitter or collector.

[0066] In a preferred embodiment, the transistor group may also be of PNP type.

[0067] Specifically, the emitter of the present embodiment has a longitudinal thickness ranging from 10 nm to 500 nm; in some embodiments, the emitter is N-type doped and can be formed by doping one or more elements of antimony, arsenic, and phosphorus. The doping concentration of the emitter of the triode group ranges from 10 18 cm -3 -10 21 cm -3 .

[0068] Specifically, the vertical thickness of the base of the triode group is in the range of 200nm-10000nm; in some embodiments, the base of the triode group is P-type doped and is composed of one or more elements of boron, aluminum, beryllium, zinc, and cadmium; the doping concentration of the base of the triode group is in the range of 10 15 cm -3 -10 18 cm -3 .

[0069] Specifically, the longitudinal thickness of the collector of the triode group is in the range of 300nm-30000nm; the collector of the triode group is N-type or P-type doped, and is composed of one or more elements of antimony, arsenic, and phosphorus.

[0070] Specifically, the resistivity of the collector of the triode group is in the range of 5Ω·cm-10Ω·cm.

[0071] Specifically, the first insulating layer and the second insulating layer are made of silicon oxide material or a composite layer material composed of silicon oxide and silicon nitride.

[0072] Specifically, the thickness of the conductive substrate is in the range of 100 μm to 700 μm, and the resistivity thereof is in the range of 0.01 Ω·cm to 0.2 Ω·cm.

[0073] Example 2

[0074] In this embodiment, refer to Figure 2 , gives another circuit structure of a triode group, which is composed of a phototransistor and three ordinary triodes in cascade. The circuit diagram of the triode array composed of two triode groups is shown in Figure 3 shown.

[0075] In this embodiment, the phototransistor and the three ordinary transistors are isolated from each other by a second insulating layer (not shown in the schematic diagram); the collector of the phototransistor is connected to the collectors of the three ordinary transistors through a conductive substrate to form the collector of the transistor group; the emitter of the phototransistor is connected to the bases of the three ordinary transistors through a conductive substrate, and the emitters of the three ordinary transistors are all electrically connected to form the emitter of the transistor group in this embodiment.

[0076] Example 3

[0077] In this embodiment, if Figure 4 As shown in the figure, another circuit structure of the triode group is shown. The triode group is composed of a phototransistor and three ordinary triodes connected in parallel. Figure 4 The circuit diagram of the transistor array composed of two transistor groups is as follows Figure 5 shown.

[0078] In this transistor group, the collector of the ordinary transistor is connected to the collectors of three phototransistors through a conductive substrate to form the collector of the transistor group; the emitter of the phototransistor is connected to the base of the first ordinary transistor, the emitter of the first ordinary transistor is connected to the base of the second ordinary transistor, and the emitter of the third ordinary transistor constitutes the emitter of the transistor group in this embodiment.

[0079] The optoelectronic chip of this example has the following advantages: (1) It has a simple structure and is composed of a transistor array including a plurality of transistor groups distributed in an array. Each transistor group includes a phototransistor and at least one ordinary transistor. Therefore, the photocurrent and the photocurrent / dark current ratio of the optoelectronic chip can be adjusted by adjusting the number of ordinary transistors, and can be effectively applied to the use of solutions with different conductivity in the optoelectronic tweezers chip; (2) The phototransistor and the ordinary transistor are manufactured at the same time, which not only reduces the process steps but also reduces the manufacturing cost; (3) The excellent optoelectronic properties of the present invention can achieve higher photocurrents with weaker light. In the application of optoelectronic tweezers, the risk of cell damage caused by too high light intensity is avoided; (4) By separating the light absorption and current amplification functions, independent control of the photocurrent and dark current is achieved, thereby improving the performance and application range of the device.

[0080] Example 4

[0081] Reference Figure 6-14 The present application embodiment provides a method for manufacturing an optoelectronic chip of embodiments 1-3, taking the NPN type as an example, comprising the following steps:

[0082] S1: forming an epitaxial structure 2 on a conductive substrate 1, wherein the epitaxial structure 2 constitutes a collector region;

[0083] Specifically, an N-type substrate is selected, and an N-type epitaxial layer is formed on the upper surface of the N-type substrate. The N-type substrate is a conductive substrate 1, and its thickness is 650±50μm, the resistivity of the substrate is 0.002-0.004Ω·cm, the resistivity of the N-type epitaxial structure is 5-10Ω·cm, and the thickness is 10μm. The N-type substrate and the N-type epitaxial structure can be formed by doping a single element or multiple elements of antimony, arsenic and phosphorus.

[0084] S2: implanting specific elements into the surface of the epitaxial structure 2 and performing thermal annealing to form a base region 3;

[0085] Specifically, boron ions are implanted, and the ion implantation dose is 2e 12 The ion implantation energy is 60 keV, the annealing is nitrogen annealing, the temperature is 1150°C, and the time is 40 min.

[0086] S3: coating a photoresist 4 on the base region 3, and opening an emitter window 5 after exposure through a photolithography mask, and performing element doping to form a first region 6;

[0087] Specifically, a photoresist 4 of a certain thickness is evenly applied on the P-type base region, an emitter window 5 is opened after exposure through a photolithography mask, and phosphorus or arsenic ion implantation is performed to form an N-type emitter. In this embodiment, the first region is an N-type emitter region.

[0088] S4: removing the photoresist, doping elements, and annealing in the first region 6 of the transistor group to form a second region 7;

[0089] Specifically, after removing the photoresist 4 by dry method, the doped part of the N-type emitter region is subjected to annealing process in a furnace tube to serve as a shallow junction emitter region, namely, the second region 7 .

[0090] S5: coating the second region 7 of the transistor group with photoresist, exposing the photomask, doping with elements, removing the photoresist and annealing to form an emitter region;

[0091] Specifically, a certain thickness of photoresist is evenly applied on the N-type emitter region, a P+ region window is opened after exposure through a photolithography mask, and doping is performed through boron ion implantation to form a P+ region (i.e., emitter region) for forming ohmic contact with the metal.

[0092] S6: removing the photoresist in the area between the common transistor and the phototransistor by photolithography, and then performing silicon etching to a depth of the substrate layer to isolate the transistors;

[0093] Specifically, after removing the photoresist by dry method, a nitrogen annealing process is performed in a furnace tube to form a P+ type region.

[0094] S7: depositing a passivation layer 8 on the surface of the structure formed in step S6;

[0095] Specifically, a passivation layer is deposited on the surface through a PECVD process, and the passivation layer may be silicon oxide or silicon nitride.

[0096] S8: coating a photoresist on the surface of the passivation layer, removing the photoresist on the surface of the collector region by photolithography exposure, and then ion etching the passivation layer to expose the emitter region, thereby forming a contact hole 9;

[0097] Specifically, photoresist is coated on the surface of the passivation layer, the photoresist on the surface of the P+ region is developed by photolithography exposure, and the passivation layer is etched by a plasma etching process to expose the P+ region and the N+ emitter region to form a contact hole.

[0098] S9: depositing a metal layer 10 by a magnetron sputtering process, and connecting the emitters of the transistors by spin coating photoresist, photolithography, development, and etching;

[0099] Specifically, a layer of metal is deposited using a magnetron sputtering process, and then photoresist is spin-coated and photolithography and development are performed, and then the metal is etched using a wet process, thereby connecting the P+ and N+ emitters through metal. The metal can be aluminum, gold, and other commonly used semiconductor metals.

[0100] S10: depositing a passivation layer again, and performing spin coating of photoresist, photolithography, development, and etching of the passivation layer to expose the emitter of the transistor.

[0101] Specifically, the passivation layer is deposited again by PECVD, and then the photoresist is spin-coated, photolithography is performed, and development is performed, and then the passivation layer is etched by a wet process to expose the emitter of the ordinary triode. The passivation layer can be silicon oxide or silicon nitride.

[0102] Preferably, the thickness of the conductive substrate is in the range of 100 μm to 700 μm, and the resistivity thereof is in the range of 0.01 Ω·m to 0.2 Ω·m.

[0103] Specifically, Fig.15 A top view of the triode group manufactured by the above method is given. Fig.16 : shows a side view of a triode array consisting of two triode groups manufactured by the above method; Fig.17 A top view of a transistor array consisting of four transistor groups manufactured by the above method is given.

[0104] It should be noted that the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0105] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0109] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application.

Claims

1. An optoelectronic chip, characterized in that: It includes a triode group array, a conductive substrate and a first insulating layer; Wherein, the triode group array is composed of a plurality of triode groups distributed in an array; Among them, the triode group includes a phototransistor, at least one ordinary triode and a second insulating layer; the phototransistor and the ordinary triode are isolated from each other by the second insulating layer; the collector of the phototransistor is connected to the collectors of all the ordinary triodes through a conductive substrate to form the collector of the triode group.

2. The optoelectronic chip according to claim 1, characterized in that: When one of the triode groups includes one of the phototransistors and at least two of the common triodes; The emitter of the phototransistor is connected to the base of all common transistors; the emitters of all common transistors are all electrically connected to form the emitter of the transistor group; or The emitter of the phototransistor is connected to the base of an ordinary transistor, the emitter of the ordinary transistor is connected to the base of the next ordinary transistor until the bases of all ordinary transistors are electrically connected, and the emitter of the last ordinary transistor that is not electrically connected to other ordinary transistors constitutes the emitter of the transistor group.

3. An optoelectronic chip according to claim 1 or 2, characterized in that: The transistor group is of NPN type or PNP type.

4. An optoelectronic chip according to claim 1 or 2, characterized in that: The emitter of the triode group has a longitudinal thickness ranging from 10 nm to 500 nm; The emitter of the triode group is N-type or P-type doped and is composed of one or more elements of antimony, arsenic, and phosphorus; The doping concentration range of the emitter of the triode group is 10 18 cm -3 -10 21 cm -3 .

5. An optoelectronic chip according to claim 1 or 2, characterized in that: The longitudinal thickness of the base of the triode group is in the range of 200nm-10000nm; The base of the triode group is N-type or P-type doped and is composed of one or more elements selected from boron, aluminum, beryllium, zinc, and cadmium; The doping concentration range of the base of the triode group is 10 15 cm -3 -10 18 cm -3 .

6. An optoelectronic chip according to claim 1 or 2, characterized in that: The longitudinal thickness of the collector electrode of the triode group is in the range of 300nm-30000nm; The collector of the triode group is N-type or P-type doped and is composed of one or more elements of antimony, arsenic, and phosphorus.

7. An optoelectronic chip according to claim 1 or 2, characterized in that: The resistivity of the collector of the triode group is in the range of 5Ω·cm-10Ω·cm.

8. An optoelectronic chip according to claim 1 or 2, characterized in that: The first insulating layer and the second insulating layer are made of silicon oxide material or a composite layer material consisting of silicon oxide and silicon nitride.

9. The optoelectronic chip according to claim 1 or 2, characterized in that: The thickness of the conductive substrate ranges from 100 μm to 700 μm; The resistivity of the conductive substrate is in the range of 0.01 Ω·cm-0.2 Ω·cm.

10. A method for manufacturing an optoelectronic chip, characterized in that: The steps include: S1: forming an epitaxial structure on a conductive substrate, wherein the epitaxial structure constitutes a collector region; S2: implanting specific elements into the surface of the epitaxial structure and performing thermal annealing to form a base region; S3: coating photoresist on the base region, exposing it through a photolithography mask to open an emitter window, and performing element doping to form a first region; S4: removing the photoresist, doping elements, and annealing in the first region of the transistor group to form a second region; S5: coating a photoresist, exposing a photomask, doping with elements, removing the photoresist, and annealing the second region of the transistor group to form an emitter region; S6: removing the photoresist in the area between the common transistor and the phototransistor by photolithography, and then performing silicon etching to a depth of the substrate layer to isolate the transistors; S7: depositing a passivation layer on the surface of the structure formed in step S6; S8: coating a photoresist on the surface of the passivation layer, removing the photoresist on the surface of the emitter region by photolithography exposure, and then ion etching the passivation layer to expose the emitter and form a contact hole; S9: depositing a metal layer by magnetron sputtering, and connecting the emitters of each transistor by spin coating photoresist, photolithography, development, and etching; S10: depositing a passivation layer again, and performing spin coating of photoresist, photolithography, development, and etching of the passivation layer to expose the emitter of the transistor.

Images