Test method of memory

Abstract

The invention provides a memory testing method. The memory testing method comprises the step of performing repeated addressing testing on a memory based on an intrinsic initial value of the memory. According to the memory testing method provided by the invention, the problems that all addressing faults cannot be detected by an existing fault testing method with a simple algorithm and the fault testing method with a complex algorithm needs too many testing vectors and the testing time is too long are solved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory testing method. Background Art

[0002] Static Random Access Memory (SRAM) is mainly used in the periphery of the processor as a data cache space, and its characteristic is fast speed; the high speed characteristic of SRAM makes it suitable for the main memory of the processor, and it is widely used in industrial electronics, instrumentation, aerospace and other fields.

[0003] like Figure 1 As shown in the figure, the SRAM device has a regular array of memory cells and a large number of logic devices, such as control circuits, sensitive amplifiers, and write circuits, which can directly participate in access operations. Since each memory cell may be in a different state, and the state change of any memory cell may cause changes in other memory cells, memory fault testing is particularly important.

[0004] Common fault testing methods (including addressing fault testing and functional fault testing) are as follows:

[0005] The simplest method is to first write 0 to each storage cell and then read it out for verification, then write 1 and then read it out for verification. The process is very fast, but the fault coverage is limited.

[0006] The test process of the chessboard method is to assign a value to each storage cell first, so that the value of each storage cell is different from that of each adjacent storage cell. It can detect stuck-at faults (SAFs) and bridging faults of adjacent cells, and the fault coverage is low.

[0007] The March algorithm is the most commonly used algorithm at present. It writes different code types by performing a series of complex operations on the memory. It has a comprehensive fault coverage rate, but the number of write and read times is large.

[0008] Among the above commonly used fault testing methods, the method with simple algorithm may have the problem of incomplete addressing and cannot detect all addressing faults, while the method with complex algorithm requires too many test vectors and the testing time will be very long. In view of this, a new testing method is proposed to solve the addressing fault (i.e. repeated addressing) problem through a relatively simple method. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a memory testing method to solve the problem that the existing fault testing method with simple algorithm cannot detect all addressing faults and the problem that the fault testing method with complex algorithm requires too many test vectors and the testing time is too long.

[0010] To achieve the above-mentioned object and other related objects, the present invention provides a memory testing method, the testing method comprising: performing a repeated addressing test on the memory based on an intrinsic initial value of the memory.

[0011] Optionally, the testing method comprises:

[0012] Determining whether the memory meets a test condition based on storage capacity and data bit width;

[0013] When the memory meets the test condition, a repeated addressing test is performed on the memory based on the intrinsic initial value of the memory.

[0014] Optionally, the method for determining whether a memory satisfies a test condition based on storage capacity and data bit width includes:

[0015] Acquire the number of address spaces of the memory based on the storage capacity and the data bit width, and acquire the number of intrinsic initial value combinations of the storage units in the memory based on the data bit width;

[0016] Comparing the number of address spaces with the number of intrinsic initial value combinations;

[0017] If the number of the address spaces is at least two orders of magnitude smaller than the number of the intrinsic initial value combinations, the memory satisfies the test condition; otherwise, the memory does not satisfy the test condition.

[0018] Optionally, the number of address spaces is equal to the ratio of the storage capacity to the data bit width, and the number of intrinsic initial value combinations is equal to 2 raised to the power of the data bit width.

[0019] Optionally, the method for performing repeated addressing test on the memory based on the intrinsic initial value of the memory includes:

[0020] Performing a read operation on the memory after power-on to obtain an intrinsic initial value of each storage unit in the memory;

[0021] Based on the repetition rate of the intrinsic initial value of each of the storage units, a repeated addressing test is performed on the memory.

[0022] Optionally, the method for obtaining the intrinsic initial value of each storage unit in the memory includes:

[0023] Based on a positive address sequence, a reverse address sequence or a random address sequence, a read operation is performed on each of the storage units in the memory after power-on to obtain an intrinsic initial value of each of the storage units.

[0024] Optionally, the method for performing repeated addressing test on the memory based on the repetition rate of the intrinsic initial value of each storage unit includes:

[0025] Obtaining a repetition rate of an intrinsic initial value of each of the storage units;

[0026] comparing the repetition rate with a set threshold;

[0027] If the repetition rate is less than or equal to the set threshold, then the memory does not have a repeated addressing fault; otherwise, the memory has a repeated addressing fault.

[0028] Optionally, the threshold value is set to satisfy the formula Among them, t s To set the threshold, m is the number of address spaces, n is the number of eigenvalue combinations; n is equal to 2 to the power of the data bit width.

[0029] Optionally, before performing the repeated addressing test on the memory, the testing method further comprises: a step of performing an open circuit test and / or a short circuit test on the memory.

[0030] Optionally, after performing the repeated addressing test on the memory, the testing method further comprises: a step of performing a functional failure test on the memory.

[0031] As described above, the memory testing method of the present invention utilizes the PUF characteristics of the memory to verify whether the memory has a repeated addressing fault by reading the intrinsic initial value of the storage unit in the memory. There is no need to design a test vector, and the addressing fault test can be implemented with only one read operation, which is beneficial to reducing the test complexity and improving the test efficiency and reliability; moreover, it can make up for and improve the deficiencies of subsequent functional fault tests when a simple algorithm is used to implement it, which is beneficial to simplify the algorithm complexity of the functional fault test and achieve high fault coverage through a simple algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Shown is a schematic diagram of the overall structure of a static random access memory.

[0033] Figure 2 Shown is a flow chart of a memory testing method of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] See also Figure 2It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0036] like Figure 2 As shown, an embodiment of the present application provides a memory testing method, including step S3; further, it also includes step S1, step S2 and step S4.

[0037] It should be noted that the memory involved in the embodiments of the present application is any type of memory with PUF (Physical Unclonable Function) characteristics, such as static random access memory (SRAM), etc. PUF is a physical entity contained in a physical structure. PUF utilizes deep submicron changes that occur naturally in the semiconductor production process and gives each transistor slightly random electrical characteristics, so it has a unique identity.

[0038] See below. Figure 2 , each step (including step S1-step S4) of the memory testing method in the embodiment of the present application is described in detail.

[0039] Step S1: Determine whether the memory satisfies the test conditions based on the storage capacity and the data bit width, so as to determine whether the memory can perform the repeated addressing test recorded in step S3 in the embodiment of the present application.

[0040] As an example, the method for determining whether a memory satisfies a test condition based on storage capacity and data bit width includes step S11 and step S12.

[0041] Step S11: acquiring the number of address spaces of the memory based on the storage capacity and the data bit width, and acquiring the number of intrinsic initial value combinations of the storage units in the memory based on the data bit width.

[0042] Specifically, the number of address spaces is equal to the ratio of storage capacity to data bit width (e.g., m represents the number of address spaces, one storage unit corresponds to one address space; x represents the storage capacity; y represents the data bit width, then m = x / y), and the number of intrinsic initial value combinations is equal to 2 to the power of the data bit width (e.g., n represents the number of intrinsic initial value combinations, then n = 2 y ).

[0043] Step S12: Compare the number of address spaces and the number of intrinsic initial value combinations; if the number of address spaces is much smaller than the number of intrinsic initial value combinations, the memory meets the test conditions and can continue to execute subsequent test steps; otherwise, the memory does not meet the test conditions and cannot continue to execute subsequent test steps, and the test ends.

[0044] In some embodiments, the number of address spaces is much smaller than the number of intrinsic initial value combinations, that is, the number of address spaces is at least two orders of magnitude smaller than the number of intrinsic initial value combinations.

[0045] The embodiment of the present application compares the number of address spaces and the number of intrinsic initial value combinations to screen out memories whose number of address spaces is much smaller than the number of intrinsic initial value combinations, that is, to screen out memories that can perform the repeated addressing test recorded in step S3; the intrinsic initial value of each storage unit in the memory is used as a characteristic value, and when the number of address spaces is much smaller than the number of intrinsic initial value combinations, it is almost impossible for characteristic value duplication to occur in the address space to be found. In this way, it is possible to determine whether the memory has a repeated addressing fault based on the repetition rate of the characteristic value, thereby determining whether the address space to be found is complete and valid.

[0046] It should be noted that repeated addressing includes two situations: one situation is that one address corresponds to multiple storage units, and the other situation is that multiple addresses correspond to one storage unit; if any of the above situations occurs, it means that there is a repeated addressing fault in the memory.

[0047] Step S2: performing an open circuit test and / or a short circuit test on the memory to determine whether the memory has an open circuit and / or a short circuit fault, so as to ensure that the circuit connection of the memory is normal, thereby ensuring the executability of subsequent tests.

[0048] In actual applications, after performing an open circuit test and / or a short circuit test on the memory, if it is determined that the memory does not have an open circuit and / or a short circuit fault, the subsequent test steps can be continued, otherwise, the subsequent test steps cannot be continued and the test ends. It should be noted that when retesting the repaired faulty memory, step S1 can be skipped and step S2 can be directly executed to save the time cost of the test.

[0049] In step S2, the memory may be subjected to only an open circuit test, only a short circuit test, or both an open circuit test and a short circuit test. In practical applications, the memory is usually subjected to both an open circuit test and a short circuit test, but there is no restriction on the order in which the two tests are performed.

[0050] When performing open circuit and short circuit tests on the memory, it is generally achieved by applying a current measurement voltage, which is a technology well known to those skilled in the art and will not be described in detail.

[0051] Step S3: Perform a repeated addressing test on the memory based on the PUF characteristics of the memory to determine whether the memory has a repeated addressing fault, so as to ensure that the addressing of the memory completely covers all storage units, thereby ensuring the executability of subsequent tests.

[0052] In some embodiments, the PUF characteristic of the memory means that each storage unit of the memory is subject to the asymmetry of the constituent pairs of tubes, and the intrinsic initial value remains fixed for the same storage unit after power-on, and is randomly distributed between different storage units; based on this, step S3 can be regarded as a repeated addressing test of the memory based on the intrinsic initial value of the memory.

[0053] As an example, the method for performing repeated addressing test on the memory based on the intrinsic initial value of the memory includes step S31 and step S32. Among them:

[0054] Step S31: performing a read operation on the memory after power-on to obtain the intrinsic initial value of each storage unit in the memory, so as to obtain the repetition rate of the intrinsic initial value later.

[0055] Specifically, a read operation is performed on each storage unit in the memory after power-on in a positive address order or a reverse address order to obtain an intrinsic initial value of each storage unit; y represents the data bit width, a storage unit includes y bits, and the intrinsic initial value is composed of y binary code values, and the binary code value is "0" or "1".

[0056] Among them, the positive address order refers to the ascending order from the low address to the high address, and the reverse address order refers to the descending order from the high address to the low address. It should be noted that performing a read operation on each storage unit in the positive address order or the reverse address order is a preferred solution. In fact, performing a read operation on each storage unit in other address orders (such as random address order) is also feasible, as long as all addresses are covered.

[0057] In actual applications, when performing a read operation on each storage unit in the memory, the tester can also verify the bandwidth capability of the address signal and data signal transmission link when the memory is working at high speed, thereby compensating for the problem that the existing fault testing method cannot verify the bandwidth capability of the address signal and data signal transmission link when the memory is working at high speed.

[0058] In the embodiment of the present application, when a read operation after power-on is performed on each storage unit in the memory in a positive address order or a reverse address order:

[0059] If there is no repeated addressing fault, one address corresponds to one storage unit. Due to the PUF characteristics of the memory, when the memory meets the test conditions, the repetition rate of the intrinsic initial value of each storage unit is extremely low, and it can be said that there is almost no repetition;

[0060] If there is a repeated addressing fault, no matter one address corresponds to multiple storage units or multiple addresses correspond to one storage unit, the intrinsic initial value of one storage unit will be read multiple times, which increases the repetition rate of the intrinsic initial value.

[0061] Step S32: Based on the repetition rate of the intrinsic initial value of each storage unit, a repeated addressing test is performed on the memory to determine whether the memory has a repeated addressing fault.

[0062] Specifically, the method for performing repeated addressing test on the memory based on the repetition rate of the intrinsic initial value of each memory cell includes step S321 and step S322. Among them:

[0063] Step S321: Obtain the intrinsic initial value repetition rate of each storage unit.

[0064] The repetition rate of the intrinsic initial value of each storage unit can be counted based on any method in the prior art; in a certain embodiment, the repetition rate of the intrinsic initial value of each storage unit can be obtained based on a hash table. Specifically: based on an array composed of each intrinsic initial value, each intrinsic initial value in the array is scanned sequentially from the beginning to the end. Every time an intrinsic initial value is scanned, it is determined whether the sequence is already included in the hash table. If the sequence does not exist in the hash table, the sequence is added to the hash table. If the sequence already exists in the hash table, the sequence is a repeated sequence, and the number of repeated sequences is increased by 1. Finally, the repetition rate is obtained based on the ratio of the number of repeated sequences to the total number of sequences.

[0065] Step S322: Compare the repetition rate with the set threshold; if the repetition rate is less than or equal to the set threshold, the memory does not have a repeated addressing fault, and the subsequent test steps can be continued; otherwise, the memory has a repeated addressing fault, and the subsequent test steps cannot be continued, and the test ends. It should be noted that when retesting the repaired faulty memory, steps S1 and S2 can be skipped and step S3 can be directly executed to save the time cost of the test.

[0066] Among them, the set threshold is obtained based on the classical probability model; in the embodiment of the present application, the number of addresses of the memory is limited, the output results are limited, and at the same time, the value of the permutation and combination of each storage unit is random, which meets the conditions of the classical probability model, and the set threshold can be calculated based on the classical probability model.

[0067] Set the threshold to satisfy the formula Among them, t s To set the threshold, m is the number of address spaces, satisfying the formula m = x / y, x represents the storage capacity, y represents the data bit width, and n is the number of intrinsic initial value combinations, satisfying the formula n = 2 y ,.

[0068] Step S4: Perform functional fault test on the memory to determine whether the memory has corresponding functional faults, such as stuck-at fault (SAF), transition fault (TF), write disturb fault (WDF), read disturb fault (RDF), coupling fault (CF), etc. The functional fault test includes functional fault diagnosis test based on chessboard algorithm, functional fault diagnosis test based on March algorithm, etc.

[0069] In the embodiment of the present application, since step S3 has been executed, that is, the addressing fault test of the memory has been completed, when executing step S4, only a functional fault test needs to be performed, and there is no need to perform an addressing fault test. In this way, the algorithm of step S4 can be simplified, and a high fault coverage rate can be achieved with a simple algorithm.

[0070] Compared with the prior art, under the condition of the same fault coverage, the test method of the embodiment of the present application has lower algorithm complexity and shorter test time; under the condition of the same algorithm complexity, the test method of the embodiment of the present application has higher fault coverage.

[0071] In practical applications, after performing a functional fault test on the memory, if it is determined that the memory does not have a functional fault, the performance test of the memory can continue, otherwise, the test ends. It should be noted that when retesting the repaired faulty memory, steps S1 to S3 can be skipped and step S4 can be directly executed to save the time cost of the test.

[0072] In summary, a memory test method of the present invention utilizes the PUF characteristics of the memory to verify whether the memory has repeated addressing faults by reading the intrinsic initial values ​​of the storage units in the memory. There is no need to design a test vector, and only one read operation is required to implement the addressing fault test, which is beneficial to reducing the test complexity and improving the test efficiency and reliability; moreover, it can make up for and improve the shortcomings of the subsequent functional fault test when a simple algorithm is used to implement it, which is beneficial to simplify the algorithm complexity of the functional fault test and achieve high fault coverage through a simple algorithm. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A memory testing method, characterized in that: The testing method comprises: performing a repeated addressing test on the memory based on an intrinsic initial value of the memory.

2. The memory testing method according to claim 1, characterized in that: The test method includes: Determining whether the memory meets a test condition based on storage capacity and data bit width; When the memory meets the test condition, a repeated addressing test is performed on the memory based on the intrinsic initial value of the memory.

3. The memory testing method according to claim 2, characterized in that: The method for determining whether a memory meets a test condition based on storage capacity and data bit width includes: Acquire the number of address spaces of the memory based on the storage capacity and the data bit width, and acquire the number of intrinsic initial value combinations of the storage units in the memory based on the data bit width; Comparing the number of address spaces with the number of intrinsic initial value combinations; If the number of the address spaces is at least two orders of magnitude smaller than the number of the intrinsic initial value combinations, the memory satisfies the test condition; otherwise, the memory does not satisfy the test condition.

4. The memory testing method according to claim 3, characterized in that: The number of address spaces is equal to the ratio of the storage capacity to the data bit width, and the number of intrinsic initial value combinations is equal to 2 raised to the power of the data bit width.

5. The memory testing method according to claim 1 or 2, characterized in that: The method for performing repeated addressing test on a memory based on an intrinsic initial value of the memory includes: Performing a read operation on the memory after power-on to obtain an intrinsic initial value of each storage unit in the memory; Based on the repetition rate of the intrinsic initial value of each of the storage units, a repeated addressing test is performed on the memory.

6. The memory testing method according to claim 5, characterized in that: The method for obtaining the intrinsic initial value of each storage unit in the memory includes: Based on a positive address sequence, a reverse address sequence or a random address sequence, a read operation is performed on each of the storage units in the memory after power-on to obtain an intrinsic initial value of each of the storage units.

7. The memory testing method according to claim 5, characterized in that: The method for performing repeated addressing test on a memory based on the repetition rate of the intrinsic initial value of each memory cell comprises: Obtaining a repetition rate of an intrinsic initial value of each of the storage units; comparing the repetition rate with a set threshold; If the repetition rate is less than or equal to the set threshold, then the memory does not have a repeated addressing fault; otherwise, the memory has a repeated addressing fault.

8. The memory testing method according to claim 7, characterized in that: The threshold is set to satisfy the formula Among them, t s To set the threshold, m is the number of address spaces, n is the number of eigenvalue combinations; n is equal to 2 to the power of the data bit width.

9. The memory testing method according to claim 1 or 2, characterized in that: Before performing the repeated addressing test on the memory, the testing method further comprises: performing an open circuit test and / or a short circuit test on the memory.

10. The memory testing method according to claim 9, characterized in that: After performing the repeated addressing test on the memory, the testing method further comprises: a step of performing a functional failure test on the memory.

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