Resistive memory structure and manufacturing method thereof

Abstract

The invention discloses a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion located outside the dielectric layer. A resistive memory device is on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacers are on sidewalls of the resistive memory device. The protection layer is located on the side wall of the protruding part and between the first electrode and the dielectric layer. According to the resistive memory structure, the reliability and the data storage capability of the resistive memory device can be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a resistive memory structure and a manufacturing method thereof. Background Art

[0002] Resistive memory devices have the potential advantages of low power consumption and high-speed operation, and are therefore very suitable as next-generation memory devices. However, how to further improve the reliability and data retention capabilities of resistive memory devices is a goal that is constantly being worked on. Summary of the invention

[0003] The invention provides a resistive memory structure and a manufacturing method thereof, which can improve the reliability and data storage capability of the resistive memory device.

[0004] The present invention proposes a resistive memory structure, including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer and a protective layer. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on the sidewall of the resistive memory device. The protective layer is located on the sidewall of the protrusion and between the first electrode and the dielectric layer.

[0005] According to an embodiment of the present invention, in the resistive memory structure, a top surface of the conductive plug may be higher than a top surface of the dielectric layer.

[0006] According to an embodiment of the present invention, in the resistive memory structure, the top surface of the conductive plug and the top surface of the protection layer may be coplanar.

[0007] According to an embodiment of the present invention, in the resistive memory structure, the protection layer can directly contact the first electrode, the dielectric layer and the protrusion.

[0008] According to an embodiment of the present invention, in the resistive memory structure, the spacer may directly contact the first electrode, the variable resistance layer and the second electrode.

[0009] According to an embodiment of the present invention, in the resistive memory structure, the spacer may directly contact the protection layer.

[0010] According to an embodiment of the present invention, in the resistive memory structure, the spacer may completely cover the sidewall of the first electrode.

[0011] According to an embodiment of the present invention, in the resistive memory structure, the spacer may completely cover the sidewall of the variable resistance layer.

[0012] According to an embodiment of the present invention, in the resistive memory structure, a top portion of the spacer may be lower than a top surface of the second electrode.

[0013] According to an embodiment of the present invention, in the resistive memory structure, the material of the first electrode is, for example, titanium.

[0014] According to an embodiment of the present invention, in the resistive memory structure, the material of the variable resistance layer is, for example, tantalum oxide (TaO) or hafnium oxide.

[0015] According to an embodiment of the present invention, in the resistive memory structure, the material of the second electrode is, for example, titanium.

[0016] According to an embodiment of the present invention, in the resistive memory structure, the material of the spacer is, for example, silicon nitride.

[0017] According to an embodiment of the present invention, in the resistive memory structure, the material of the protection layer is, for example, silicon nitride.

[0018] The present invention provides a method for manufacturing a resistive memory structure, comprising the following steps: providing a substrate; forming a dielectric layer on the substrate; forming a conductive plug in the dielectric layer; the conductive plug having a protrusion located outside the dielectric layer; forming a resistive memory device on the conductive plug; the resistive memory device comprising a first electrode, a variable resistance layer and a second electrode; the first electrode is located on the conductive plug; the variable resistance layer is located on the first electrode; the second electrode is located on the variable resistance layer; forming a spacer on the sidewall of the resistive memory device; forming a protective layer on the sidewall of the protrusion and between the first electrode and the dielectric layer.

[0019] According to an embodiment of the present invention, in the manufacturing method of the resistive memory structure, the method for forming the conductive plug may include the following steps: forming a protective material layer on the dielectric layer; forming an opening in the protective material layer and the dielectric layer; forming a conductive layer on the protective material layer and in the opening; and removing the conductive layer outside the opening to form a conductive plug.

[0020] According to an embodiment of the present invention, in the method for manufacturing the resistive memory structure, the method for removing the conductive layer outside the opening is, for example, chemical mechanical polishing (CMP).

[0021] According to an embodiment of the present invention, in the manufacturing method of the resistive memory structure, the method for forming the spacer and the protective layer may include the following steps: forming a spacer material layer on the resistive memory device and the protective material layer; performing an etch back process on the spacer material layer and the protective material layer to form the spacer and the protective layer.

[0022] According to an embodiment of the present invention, in the manufacturing method of the resistive memory structure, the etch-back process is, for example, a dry etching process.

[0023] According to an embodiment of the present invention, in the manufacturing method of the resistive memory structure, the protection layer can directly contact the first electrode, the dielectric layer and the protrusion.

[0024] Based on the above, in the resistive memory structure and its manufacturing method proposed in the present invention, the protective layer is located on the side wall of the protrusion and between the first electrode and the dielectric layer, thereby preventing ions (such as oxygen ions) in the dielectric layer from diffusing into the first electrode and the variable resistance layer, thereby improving the reliability and data retention capability of the resistive memory device.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1H 2 is a cross-sectional view of the manufacturing process of the resistive memory structure according to some embodiments of the present invention.

[0027] Description of Figure Numbers:

[0028] 10: Resistive Memory Structure

[0029] 100: substrate

[0030] 102,108: Dielectric layer

[0031] 104: Interconnection structure

[0032] 106: Termination layer

[0033] 110: Protective material layer

[0034] 110a: Protective layer

[0035] 112: Patterned photoresist layer

[0036] 114: Conductive layer

[0037] 114a: Conductive plug

[0038] 116,120: Electrode material layer

[0039] 116a,120a:Electrode

[0040] 118: variable resistance material layer

[0041] 118a: variable resistance layer

[0042] 122: Resistive memory device

[0043] 124: Spacer material layer

[0044] 124a: Spacer

[0045] OP1: Opening

[0046] P1: protrusion

[0047] T1: Top

[0048] TS1,TS2,TS3,TS4: Top surface DETAILED DESCRIPTION

[0049] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0050] Figures 1A to 1H FIG. 4 is a cross-sectional view of a manufacturing process of a resistive memory structure according to some embodiments of the present invention.

[0051] Please refer to Figure 1A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, a dielectric layer 102 may be formed on the substrate 100. The material of the dielectric layer 102 is, for example, silicon oxide, a low dielectric constant (low-k) dielectric material, or an ultra low dielectric constant (ultra low-k, ULK) dielectric material. The dielectric layer 102 may be formed by, for example, chemical vapor deposition. In some embodiments, an interconnect structure 104 may be formed in the dielectric layer 102. In some embodiments, the interconnect structure 104 may be a conductive wire. The material of the interconnect structure 104 is, for example, a conductive material such as copper. In some embodiments, the interconnect structure 104 may be formed by an interconnect process.

[0052] In addition, Figure 1AAlthough not shown, the substrate 100 may have semiconductor devices (such as active devices and / or passive devices), other dielectric layers and / or other interconnection structures and other required components, and their description is omitted here. In addition, the interconnection structure 104 can be electrically connected to the corresponding interconnection structure (not shown) or semiconductor device (not shown).

[0053] Next, a termination layer 106 may be formed on the dielectric layer 102 and the interconnect structure 104. The termination layer 106 may be made of, for example, nitrogen doped silicon carbide (NDC), such as silicon carbide nitride (SiCN). The termination layer 104 may be formed by, for example, chemical vapor deposition.

[0054] Then, a dielectric layer 108 is formed on the substrate 100. In some embodiments, the dielectric layer 108 may be formed on the termination layer 106. The material of the dielectric layer 108 is, for example, silicon oxide, a low-k dielectric material, or an ultra-low-k dielectric material. The dielectric layer 108 may be formed by, for example, chemical vapor deposition.

[0055] Next, a protective material layer 110 may be formed on the dielectric layer 108. The material of the protective material layer 110 is, for example, silicon nitride. The protective material layer 110 may be formed by, for example, chemical vapor deposition.

[0056] Please refer to Figure 1B , a patterned photoresist layer 112 may be formed on the protective material layer 110. The patterned photoresist layer 112 may be formed by a photolithography process.

[0057] Next, the patterned photoresist layer 112 may be used as a mask to remove a portion of the protective material layer 110, a portion of the dielectric layer 108, and a portion of the termination layer 106 to form an opening OP1. Thus, an opening OP1 may be formed in the protective material layer 110, the dielectric layer 108, and the termination layer 106. In some embodiments, the opening OP1 may expose the interconnection structure 104.

[0058] Please refer to Figure 1C , the patterned photoresist layer 112 can be removed. The method for removing the patterned photoresist layer 112 is, for example, a dry stripping method or a wet stripping method.

[0059] Next, a conductive layer 114 may be formed on the protective material layer 110 and in the opening OP1. The conductive layer 114 may be made of a conductive material such as tungsten, etc. The conductive layer 114 may be formed by chemical vapor deposition, for example.

[0060] Please refer to Figure 1D, the conductive layer 114 located outside the opening OP1 can be removed to form a conductive plug 114a. Thus, the conductive plug 114a can be formed in the dielectric layer 108. The conductive plug 114a can also be formed in the protective material layer 110 and the termination layer 106. The conductive plug 114a has a protrusion P1 located outside the dielectric layer 108. The top surface TS1 of the conductive plug 114a can be higher than the top surface TS2 of the dielectric layer 108. The conductive plug 114a can be electrically connected to the interconnect structure 104. In some embodiments, the conductive plug 114a can be a conductive via. In some embodiments, the method for removing the conductive layer 114 located outside the opening OP1 is, for example, a chemical mechanical polishing method.

[0061] Please refer to Figure 1E , an electrode material layer 116, a variable resistance material layer 118, and an electrode material layer 120 may be sequentially formed on the conductive plug 114a and the protective material layer 110. The material of the electrode material layer 116 is, for example, a conductive material such as titanium. The electrode material layer 116 may be formed by, for example, physical vapor deposition. The material of the variable resistance material layer 118 may be a metal oxide. In some embodiments, the material of the variable resistance material layer 118 is, for example, tantalum oxide or hafnium oxide. The variable resistance material layer 118 may be formed by, for example, physical vapor deposition. The material of the electrode material layer 120 is, for example, a conductive material such as titanium. The electrode material layer 120 may be formed by, for example, physical vapor deposition.

[0062] Please refer to Figure 1F , the electrode material layer 120, the variable resistance material layer 118 and the electrode material layer 116 may be patterned to form an electrode 120a, a variable resistance layer 118a and an electrode 116a. Thus, a resistive memory device 122 may be formed on the conductive plug 114a. In some embodiments, the resistive memory device 122 may also be formed on the protective material layer 110. The resistive memory device 122 includes an electrode 116a, a variable resistance layer 118a and an electrode 120a. The electrode 116a is located on the conductive plug 114a. The electrode 116a may be electrically connected to the conductive plug 114a. The material of the electrode 116a is, for example, a conductive material such as titanium. The variable resistance layer 118a is located on the electrode 116a. The material of the variable resistance layer 118a may be a metal oxide. In some embodiments, the material of the variable resistance layer 118a is, for example, tantalum oxide or hafnium oxide. The electrode 120a is located on the variable resistance layer 118a. The material of the electrode 120 a is, for example, a conductive material such as titanium.

[0063] Please refer to Figure 1G, a spacer material layer 124 may be formed on the resistive memory device 122 and the protective material layer 110. The material of the spacer material layer 124 is, for example, silicon nitride. The spacer material layer 124 may be formed by, for example, chemical vapor deposition.

[0064] Please refer to Figure 1H , the spacer material layer 124 and the protective material layer 110 are etched back to form a spacer 124a and a protective layer 110a. Thus, the spacer 124a can be formed on the sidewall of the resistive memory device 122, and the protective layer 110a can be formed on the sidewall of the protrusion P1 and between the electrode 116a and the dielectric layer 108. The protective layer 110a can also be formed between the spacer 124a and the dielectric layer 108. In addition, since the protective layer 110a is located on the sidewall of the protrusion P1 and between the electrode 116a and the dielectric layer 108, it can prevent ions (such as oxygen ions) in the dielectric layer 108 from diffusing into the electrode 116a and the variable resistance layer 118a, thereby improving the reliability and data retention capability of the resistive memory device 122. In some embodiments, the etch-back process is, for example, a dry etching process.

[0065] The protection layer 110a may directly contact the electrode 116a, the dielectric layer 108 and the protrusion P1. The top surface TS1 of the conductive plug 114a and the top surface TS3 of the protection layer 110a may be coplanar. The material of the protection layer 110a is, for example, silicon nitride.

[0066] The spacer 124a may directly contact the electrode 116a, the variable resistance layer 118a and the electrode 120a. The spacer 124a may also directly contact the protection layer 110a. The spacer 124a may completely cover the sidewall of the electrode 116a. The spacer 124a may completely cover the sidewall of the variable resistance layer 118a. The top T1 of the spacer 124a may be lower than the top surface TS4 of the electrode 120a. The material of the spacer 124a is, for example, silicon nitride.

[0067] Below, through Figure 1H In order to illustrate the resistive memory structure 10 of the above embodiment. In addition, although the method of forming the resistive memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

[0068] Please refer to Figure 1H, the resistive memory structure 10 includes a substrate 100, a dielectric layer 108, a conductive plug 114a, a resistive memory device 122, a spacer 124a and a protective layer 110a. The dielectric layer 108 is located on the substrate 100. The conductive plug 114a is located in the dielectric layer 108. The conductive plug 114a has a protrusion P1 located outside the dielectric layer 108. The resistive memory device 122 is located on the conductive plug 114a. The resistive memory device 122 includes an electrode 116a, a variable resistance layer 118a and an electrode 120a. The electrode 116a is located on the conductive plug 114a. The variable resistance layer 118a is located on the electrode 116a. The electrode 120a is located on the variable resistance layer 118a. The spacer 124a is located on the sidewall of the resistive memory device 122. The protection layer 110 a is located on the sidewall of the protrusion P1 and between the electrode 116 a and the dielectric layer 108 .

[0069] In some embodiments, the resistive memory structure 10 may further include at least one of a dielectric layer 102, an interconnect structure 104, and a termination layer 106. The dielectric layer 102 is located between the dielectric layer 108 and the substrate 100. The interconnect structure 104 is located in the dielectric layer 102. The termination layer 106 is located between the dielectric layer 108 and the dielectric layer 102 and between the dielectric layer 108 and the interconnect structure 104. The conductive plug 114a may pass through the termination layer 106 and be connected to the interconnect structure 104.

[0070] In addition, the details of each component in the resistive memory structure 10 (eg, material, configuration, formation method and function, etc.) have been described in detail in the above embodiments and will not be described again here.

[0071] Based on the above embodiments, it can be seen that in the resistive memory structure 10 and the manufacturing method thereof, the protective layer 110a is located on the side wall of the protrusion P1 and between the electrode 116a and the dielectric layer 108, thereby preventing ions (such as oxygen ions) in the dielectric layer 108 from diffusing into the electrode 116a and the variable resistance layer 118a, thereby improving the reliability and data retention capability of the resistive memory device 122.

[0072] In summary, in the resistive memory structure and the manufacturing method thereof of the above-mentioned embodiments, since the protective layer can prevent ions (such as oxygen ions) in the dielectric layer from diffusing into the electrodes and the variable resistance layer of the resistive memory device, the reliability and data retention capability of the resistive memory device can be improved.

[0073] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A resistive memory structure, characterized in that: include: substrate; a dielectric layer, located on the substrate; a conductive plug located in the dielectric layer and having a protrusion located outside the dielectric layer; A resistive memory device is located on the conductive plug and includes: A first electrode, located on the conductive plug; a variable resistance layer, located on the first electrode; and A second electrode, located on the variable resistance layer; a spacer located on a sidewall of the resistive memory device; and A protection layer is located on the sidewall of the protrusion and between the first electrode and the dielectric layer.

2. The resistive memory structure according to claim 1, characterized in that: A top surface of the conductive plug is higher than a top surface of the dielectric layer.

3. The resistive memory structure according to claim 1, characterized in that: A top surface of the conductive plug is coplanar with a top surface of the protection layer.

4. The resistive memory structure according to claim 1, wherein: The protection layer directly contacts the first electrode, the dielectric layer, and the protrusion.

5. The resistive memory structure according to claim 1, characterized in that: The spacer directly contacts the first electrode, the variable resistance layer, and the second electrode.

6. The resistive memory structure according to claim 5, characterized in that: The spacer also directly contacts the protective layer.

7. The resistive memory structure according to claim 1, characterized in that: The spacer completely covers a side wall of the first electrode.

8. The resistive memory structure according to claim 1, characterized in that: The spacer completely covers a sidewall of the variable resistance layer.

9. The resistive memory structure according to claim 1, characterized in that: A top portion of the spacer is lower than a top surface of the second electrode.

10. The resistive memory structure according to claim 1, characterized in that: The material of the first electrode includes titanium.

11. The resistive memory structure according to claim 1, characterized in that: The material of the variable resistance layer includes tantalum oxide or hafnium oxide.

12. The resistive memory structure according to claim 1, wherein: The material of the second electrode includes titanium.

13. The resistive memory structure according to claim 1, wherein: The material of the spacer includes silicon nitride.

14. The resistive memory structure according to claim 1, wherein: The material of the protection layer includes silicon nitride.

15. A method for manufacturing a resistive memory structure, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate; forming a conductive plug in the dielectric layer, wherein the conductive plug has a protrusion located outside the dielectric layer; forming a resistive memory device on the conductive plug, wherein the resistive memory device comprises: A first electrode, located on the conductive plug; a variable resistance layer, located on the first electrode; and A second electrode, located on the variable resistance layer; forming spacers on sidewalls of the resistive memory device; and A protection layer is formed on the sidewall of the protrusion and between the first electrode and the dielectric layer.

16. The method for manufacturing a resistive memory structure according to claim 15, wherein: The method for forming the conductive plug includes: forming a protective material layer on the dielectric layer; forming openings in the protective material layer and the dielectric layer; forming a conductive layer on the protective material layer and in the opening; and The conductive layer located outside the opening is removed to form the conductive plug.

17. The method for manufacturing a resistive memory structure according to claim 16, wherein: The method of removing the conductive layer outside the opening includes a chemical mechanical polishing method.

18. The method for manufacturing a resistive memory structure according to claim 16, wherein: The method for forming the spacer and the protective layer includes: forming a spacer material layer on the resistive memory device and the protective material layer; and The spacer material layer and the protection material layer are subjected to an etch-back process to form the spacer and the protection layer.

19. The method for manufacturing a resistive memory structure according to claim 18, wherein: The etch-back process includes a dry etching process.

20. The method for manufacturing a resistive memory structure according to claim 15, wherein: The protection layer directly contacts the first electrode, the dielectric layer, and the protrusion.

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