Optimization design method based on DSP + FPGA architecture microsystem circuit

Abstract

The invention relates to an optimization design method based on a DSP + FPGA architecture microsystem circuit, the optimization design method utilizes an innovative power supply simulation technology, optimizes the power supply integrity design, simplifies the design and manufacturing process of a microsystem, and comprises the following steps: determining a simulation target and requirement, establishing a power supply network model, setting simulation parameters and conditions, and establishing a power supply network model; and analyzing a simulation result and a problem, proposing an optimization design scheme, evaluating an optimization effect and summarizing. According to the optimization design method, the power supply integrity design is optimized through the innovative power supply simulation technology, and the external power supply voltage is effectively improved in the real installation design stage. The remarkable improvement lies in that the power supply and the signal can be ensured to stably meet various requirements of chip application without adding any redundant passive device on the ceramic tube shell. The method not only ensures the normal work of the microsystem, but also greatly simplifies the design and manufacturing process of the microsystem.

Description

Technical Field

[0001] The present invention relates to the field of microsystem design, manufacturing and application technology, and in particular to an optimization design method for a microsystem circuit based on a DSP+FPGA architecture. Background Art

[0002] With the rapid progress of electronic technology, integrated circuits and packaging processes have achieved significant breakthroughs. Microsystem technology, namely System in Package, has become one of the important strategies for system integration. With this technology, we can efficiently interconnect bare chips, microcomponents and passive devices and integrate them into a single ceramic tube package. This not only achieves a high degree of system integration, but also helps to achieve miniaturization, low power design, high reliability and high efficiency operation of products, providing strong technical support for the future development of electronic systems.

[0003] In electronic systems, the number of passive devices usually accounts for more than 80% of the total BOM devices, and the area occupied on the circuit board is nearly as high as 70%. Therefore, how to effectively reduce the packaging volume of these devices has become one of the important challenges in achieving the miniaturization of electronic systems. Integrated passive devices (IPDs) are an ideal solution that aims to integrate multiple passive devices into one unit. However, the current yield rate of passive devices made into IPDs is not ideal, resulting in high prices, which undoubtedly increases the cost of packaging IPDs into microsystem circuits and may have a negative impact on the yield of microsystems. In addition, since passive devices have low functional density when they exist in discrete form and their physical sizes vary, packaging them separately into microsystem circuits will also have an adverse effect on the overall physical size of the microsystem. Therefore, how to solve these problems while ensuring performance has become a key issue that needs to be solved in microsystem design and manufacturing. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an optimization design method for a microsystem circuit based on a DSP+FPGA architecture. The optimization design method utilizes innovative power simulation technology to optimize the power integrity design and simplify the design and manufacturing process of the microsystem, and includes the following steps:

[0005] Step S1: Determine the simulation goals and requirements, clarify the purpose of power integrity simulation, such as reducing voltage fluctuations or reducing noise interference, and determine the accuracy and performance requirements required for the simulation;

[0006] Step S2: Establishing a power network model: establishing a power network model according to the actual circuit layout and device characteristics, while taking into account the impedance, capacitance, and inductance in the power network;

[0007] Step S3: Setting simulation parameters and conditions: according to the simulation objectives and requirements, setting appropriate simulation parameters, such as simulation time and step length, and setting boundary conditions, excitation sources and loads;

[0008] Step S4: Analyze simulation results and problems, analyze the simulation results, find out the problems and bottlenecks in the power supply network; compare the simulation results with the target requirements, and evaluate the pros and cons of the power supply integrity;

[0009] Step S5: Propose an optimization design plan. According to the simulation results and problem analysis, propose a targeted optimization design plan; consider optimizing the layout of the power supply network, device selection, parameter adjustment, etc.;

[0010] Implement optimization design and verify that the power supply network is improved and optimized according to the optimization design plan; otherwise, re-simulate and optimize iterative verification to ensure that the optimized power supply network meets the requirements;

[0011] Step S6: Evaluate the optimization effect and summarize and compare the simulation results before and after the optimization to evaluate the optimization effect.

[0012] In one embodiment of the present invention, in step S3, simulation parameters and conditions are set: according to different simulation objectives and requirements, simulation parameter settings are divided into: (1) DC parameter settings: including input voltage, power consumption current, allowable voltage drop range, current density threshold; (2) frequency domain parameter settings: including simulation frequency range, step size / number of points, target impedance, number of resonant modes; (3) time domain parameter settings: excitation source signal rate, code type, level amplitude, rising / falling edge.

[0013] In one embodiment of the present invention, the design scheme is optimized in step S5. Due to cost or other design considerations, the method of optimizing the power / ground plane structure is subject to many restrictions. A reasonable decoupling capacitor design is adopted, including: determining the resonant frequency according to the PDN impedance obtained by simulation, selecting a decoupling capacitor with a suitable self-resonant frequency and Q value according to the PDN resonant frequency, modifying the existing capacitor model or adding a suitable capacitor model in the EDA software, and using the self-resonant frequency of the decoupling capacitor to suppress the PDN plane resonance.

[0014] In one embodiment of the present invention, the decoupling capacitor is located close to the chip power pin, or the resonance distribution of the power / ground plane is obtained through planar resonance simulation, and the decoupling capacitor is placed at the resonance location.

[0015] The above technical solution of the present invention has the following advantages over the prior art: the optimization design method described in the present invention optimizes the power integrity design through innovative power simulation technology, and effectively improves the external power supply voltage during the actual design stage. This improvement is significant in that it is possible to ensure that the power supply and signal stability meet the various requirements of chip applications without adding any redundant passive components to the ceramic tube shell. This method not only ensures the normal operation of the microsystem, but also greatly simplifies the design and manufacturing process of the microsystem. At the same time, it successfully avoids the risk of low yield caused by integrated IPD in traditional microsystem design, thereby significantly improving the integration and manufacturing yield of the microsystem, and bringing significant improvements to the performance and reliability of the microsystem. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0017] Figure 1 It is a flow chart of the optimization design method of the DSP+FPGA architecture microsystem power integrity simulation of the present invention;

[0018] Figure 2 It is a system block diagram of the principle prototype of the DSP+FPGA architecture microsystem of the present invention;

[0019] Figure 3a This is a plane distribution result diagram of the DC voltage drop of the power supply according to the present invention;

[0020] Figure 3b This is a diagram showing the current density distribution result on the power plane of the present invention;

[0021] Figure 3c This is a diagram of the PDN impedance simulation result of the present invention;

[0022] Figure 3d is a diagram of the simulation results of the planar resonance distribution of the present invention;

[0023] Figure 4 It is a screenshot of the simulation results of the microsystem ceramic shell of the present invention. DETAILED DESCRIPTION

[0024] like Figure 1 As shown, this embodiment provides an optimization design method for a microsystem circuit based on a DSP+FPGA architecture. The optimization design method utilizes innovative power simulation technology to optimize the power integrity design and simplify the design and manufacturing process of the microsystem, and includes the following steps:

[0025] Step S1: Determine the simulation goals and requirements, clarify the purpose of power integrity simulation, such as reducing voltage fluctuations or reducing noise interference, and determine the accuracy and performance requirements required for the simulation;

[0026] Step S2: Establishing a power network model: establishing a power network model according to the actual circuit layout and device characteristics, while taking into account the impedance, capacitance, and inductance in the power network;

[0027] Step S3: Setting simulation parameters and conditions: according to the simulation objectives and requirements, setting appropriate simulation parameters, such as simulation time and step length, and setting boundary conditions, excitation sources and loads;

[0028] Step S4: Analyze simulation results and problems, analyze the simulation results, find out the problems and bottlenecks in the power supply network; compare the simulation results with the target requirements, and evaluate the pros and cons of the power supply integrity;

[0029] Step S5: Propose an optimization design plan. According to the simulation results and problem analysis, propose a targeted optimization design plan; consider optimizing the layout of the power supply network, device selection, parameter adjustment, etc.;

[0030] Implement optimization design and verify that the power supply network is improved and optimized according to the optimization design plan; otherwise, re-simulate and optimize iterative verification to ensure that the optimized power supply network meets the requirements;

[0031] Step S6: Evaluate the optimization effect and summarize and compare the simulation results before and after the optimization to evaluate the optimization effect.

[0032] Specifically, simulation parameters and condition settings: Depending on the simulation objectives and requirements, simulation parameter settings are divided into the following aspects: (1) DC parameter settings: including input voltage, current consumption, allowable voltage drop range, current density threshold, etc.; (2) Frequency domain parameter settings: including simulation frequency range, step size / number of points, target impedance, number of resonant modes, etc.; (3) Time domain parameter settings: excitation source signal rate, code type, level amplitude, rising / falling edge, etc.

[0033] The details of the DC simulation optimization method include:

[0034] 1) Ensure the integrity of the power / ground plane, avoid structures such as narrow bridges and slender traces, and increase the cross-sectional area of ​​the power / ground plane;

[0035] 2) Try to ensure that the power and ground planes are adjacent plane layers, and the medium between the planes should be as thin as possible;

[0036] 3) Add sufficient number of power / ground vias between layers;

[0037] 4) Under the conditions that meet the processing requirements, choose metal materials with higher electrical conductivity;

[0038] 5) The thickness of the metal layer can be appropriately increased without affecting parameters such as line width and line spacing;

[0039] 6) Simulation tools can be used to view voltage distribution and current density hot spots, and perform targeted optimization designs.

[0040] Due to cost or other design considerations, the methods for optimizing the power / ground plane structure are subject to many restrictions. Reasonable decoupling capacitor design is a more flexible and effective method:

[0041] 1) The general method for optimizing the design of decoupling capacitors is to determine the resonant frequency based on the PDN impedance obtained by simulation, select a decoupling capacitor with a suitable self-resonant frequency and Q value based on the PDN resonant frequency, modify the existing capacitor model or add a suitable capacitor model in the EDA software, and use the self-resonant frequency of the decoupling capacitor to suppress the PDN plane resonance.

[0042] 2) Generally, the location of the decoupling capacitor should be as close to the chip power pin as possible. The resonance distribution of the power / ground plane can also be obtained through plane resonance simulation, and the decoupling capacitor can be placed at the location where the resonance occurs.

[0043] Furthermore, power integrity simulation is performed, and simulation software or tools are used to perform simulation calculations of power integrity, and observe characteristics such as voltage fluctuations and noise in the power supply network.

[0044] Analyze simulation results and problems, analyze simulation results, find problems and bottlenecks in the power network. Compare simulation results with target requirements and evaluate the pros and cons of power integrity.

[0045] Propose an optimization design plan. According to the simulation results and problem analysis, propose a targeted optimization design plan. Consider optimizing the layout, device selection, parameter adjustment and other aspects of the power network. Implement the optimization design and verify that the power network is improved and optimized according to the optimization design plan. Re-simulate and verify to ensure that the optimized power network meets the requirements. Evaluate the optimization effect and summarize the simulation results before and after optimization to evaluate the optimization effect. Summarize the experience and lessons learned from this power integrity simulation and optimization design.

[0046] The optimization design method described in this embodiment corresponds to the prototype verification principle prototype system block diagram as shown in Figure 2 As shown in the figure, in the microsystem of DSP+FPGA architecture, the DSP chip is the core, and the FPGA chip is hung on the DSP through the PCIe interface. At the same time, the microsystem integrates 2 DDR3 microcomponents, 1 DDR2 microcomponent, 1 PROM bare core and several passive devices.

[0047] The microsystem was simulated and optimized. When the ambient temperature was 25°C, the heat generation area of ​​the overall temperature distribution under natural heat dissipation conditions was concentrated in the DSP chip area, where the highest chip temperature was 325.90°C. The main heat dissipation path was conduction through the cover and substrate, which was 175°C higher than the failure temperature of the Si chip.

[0048] At the same time, the invention patent is simulated and optimized. The tasks in the simulation result analysis phase include the determination of DC voltage drop and current density:

[0049] like Figure 3a The figure shows an example of the DC voltage drop plane distribution result. The figure shows the voltage distribution and voltage drop trend on the power plane. The working voltage of the power supply is 0.9V, and the allowable voltage fluctuation is ±3. The actual minimum working voltage obtained by simulation is 0.8956V, and the actual voltage drop is 0.49%, which meets the requirements.

[0050] like Figure 3b The following is an example of the planar current density distribution result, where the current density hotspot area can be seen. The current density threshold is set to 100A / mm2 according to the process capability of the substrate manufacturer. The maximum planar current density of the power supply is 31.82A / mm2, which meets the processing requirements.

[0051] The above results are analyzed for the patent of this invention:

[0052] Check the Z parameter. The target impedance frequency range of this patent is 100MHz (higher frequency impedance results can be checked during simulation to determine the resonant frequency position). The planar impedance simulation results are as follows Figure 3c shown.

[0053] Also view the resonance distribution of the power / ground plane of interest to determine where the resonance occurs. An example of a resonance simulation result is shown below: Figure 3d shown.

[0054] The main reason is that the maximum current of the 0.9V DSP core power is as high as 30A, which requires high power stability, and inevitably requires the addition of many filter capacitors. According to statistics, there are 88 0.9V filter capacitors on the prototype.

[0055] The microsystem adopts a 54mm×46mm×8.65mm CCGA ceramic package. The overall model contains 6 components and several resistors and capacitors. The assembly form is FC (bottom-fill). The overall model parameters and geometric dimensions are shown in the following table.

[0056]

[0057] There is not enough space on the ceramic tube shell to accommodate 88 filter capacitors, so the power plane and the number of capacitors were optimized through power simulation. Before the capacitor reduction, the number of filter capacitors for the DSP core power 0.9V was 88. After the reduction, only 3 were retained.

[0058] The power supplies of the microsystem design ceramic tube shell are simulated. The DC voltage drop of the DSP core power supply VDD_0V9_DSPVDD is 0.0257V, which exceeds the required fluctuation range of 3%. The DC voltage drops of other power supplies can meet the requirements, such as Figure 4 The risk needs to be further verified on the prototype.

[0059] Specifically, through the DC voltage drop simulation of all power planes, it can be found that the DC voltage drop of FT_VDD_CORE, MGTAVCC, MGTAVTT, VCCINT, and VDD_DDR power supplies cannot meet the requirements, such as Figure 4 Metal material: tungsten, conductivity: 6.67x10 6 S / m.

[0060] According to the DSP chip manual, the minimum operating voltage of VDD_0V9_DSPVDD is 0.81V and the maximum is 0.99V. VDD_0V9_DSPVDD is powered by the DCDC power chip. Adjust the DCDC output voltage and confirm that the voltage of VDD_0V9_DSPVDD at the DSP end of the prototype can be as low as 0.845V and as high as 0.939V, and it can work normally.

[0061] The DSP+FPGA architecture microsystem was installed on the microsystem actual test board for testing and application. The external DCDC power supply circuit was adjusted to make the DSP core power VDD_0V9_DSPVDD_DSPVDD voltage 0.926V. The 0.0257V DC voltage drop caused by transmission attenuation on the ceramic tube shell was removed, and the power supply voltage at the foot of the microsystem DSP core power pin was 0.9V, which met the rated working voltage requirements of the DSP device. The functional performance of the actual test microsystem was consistent with the principle prototype.

[0062] On the microsystem actual installation test board, the core power voltage corresponding to the DSP bare core in the microsystem was raised to 0.926V. The measured microsystem function and performance were consistent with the principle prototype.

[0063] This technology innovatively implements a power integrity optimization design for a signal processing microsystem based on the DSP+FPGA architecture. By using power simulation to reduce the number of passive components required by the microsystem and raising the external power supply voltage when combining the actual application of the microsystem, the microsystem can be quickly designed, manufactured and applied, greatly saving the cost of developing IPDs, improving the microsystem yield and system integration, and improving the efficiency of microsystem development and application.

[0064] The DSP+FPGA architecture microsystem described in this embodiment uses simulation and actual installation optimization design to achieve the simplification of filter capacitors, improve the utilization rate of the microsystem ceramic tube shell, reduce the microsystem design cost and the requirements for processing technology, the technical difficulty is relatively controllable, and the microsystem yield rate is improved. The realized microsystem has the characteristics of many interconnection layers, high integration density, strong mechanical stress, stable shape, etc., and is particularly suitable for aerospace and military electronic devices.

[0065] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. An optimization design method for a microsystem circuit based on a DSP+FPGA architecture, wherein the optimization design method utilizes innovative power simulation technology to optimize the power integrity design and simplify the design and manufacturing process of the microsystem, and is characterized in that: The steps include: Step S1: Determine the simulation goals and requirements, clarify the purpose of power integrity simulation, such as reducing voltage fluctuations or reducing noise interference, and determine the accuracy and performance requirements required for the simulation; Step S2: Establishing a power network model: establishing a power network model according to the actual circuit layout and device characteristics, while taking into account the impedance, capacitance, and inductance in the power network; Step S3: Setting simulation parameters and conditions: according to the simulation objectives and requirements, setting appropriate simulation parameters, such as simulation time and step length, and setting boundary conditions, excitation sources and loads; Step S4: Analyze simulation results and problems, analyze the simulation results, find out the problems and bottlenecks in the power supply network; compare the simulation results with the target requirements, and evaluate the pros and cons of the power supply integrity; Step S5: Propose an optimization design plan. According to the simulation results and problem analysis, propose a targeted optimization design plan; consider optimizing the layout of the power supply network, device selection, parameter adjustment, etc.; Implement optimization design and verify that the power network is improved and optimized according to the optimization design plan; otherwise, re-simulate and optimize iterative verification to ensure that the optimized power network meets the requirements; Step S6: Evaluate the optimization effect and summarize and compare the simulation results before and after the optimization to evaluate the optimization effect.

2. The optimization design method according to claim 1, characterized in that: Simulation parameter and condition setting in step S3: According to different simulation objectives and requirements, simulation parameter setting is divided into: (1) DC parameter setting: including input voltage, power consumption current, allowable voltage drop range, and current density threshold; (2) Frequency domain parameter settings: including simulation frequency range, step size / number of points, target impedance, and number of resonant modes; (3) Time domain parameter settings: excitation source signal rate, code type, level amplitude, rising / falling edge.

3. The optimization design method according to claim 1, characterized in that: In step S5, the design scheme is optimized. Due to cost or other design considerations, the method of optimizing the power / ground plane structure is subject to many restrictions. A reasonable decoupling capacitor design is adopted, including: determining the resonant frequency according to the PDN impedance obtained by simulation, selecting a decoupling capacitor with a suitable self-resonant frequency and Q value according to the PDN resonant frequency, modifying the existing capacitor model or adding a suitable capacitor model in the EDA software, and using the self-resonant frequency of the decoupling capacitor to suppress the PDN plane resonance.

4. The optimization design method according to claim 3, characterized in that: The decoupling capacitor is located close to the chip power pin, or the resonant distribution of the power / ground plane is obtained through planar resonance simulation, and the decoupling capacitor is placed at the location where the resonance occurs.

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