Super-large imaging dynamic infrared focal plane, reading circuit and reading circuit preparation method

Abstract

The invention provides a super-large imaging dynamic infrared focal plane, a readout circuit and a readout circuit preparation method. The preparation method comprises the following steps: equally dividing a focal plane array into a plurality of pixel blocks; according to a focal plane imaging dynamic range demand and an imaging demand, sub-integral time of each pixel in the pixel block is determined; configuring a pixel-level integral circuit of a pixel; a time sequence control circuit is configured and used for controlling all pixels of the whole focal plane array to be started at the same time to carry out integration on the photocurrent of the detector, the pixels with different sub-integration time are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port according to the sequence of pixel blocks; and carrying out layout design and tape-out, and preparing a reading circuit. According to the infrared focal plane reading circuit, the imaging dynamic range of the infrared focal plane reading circuit can be remarkably enlarged on the premise that the focal plane pixel area is not sacrificed, the infrared focal plane reading circuit with the ultra-large dynamic range is achieved, and the problem that the focal plane imaging dynamic range is enlarged with the small pixel area is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of infrared focal plane technology, and in particular to an ultra-large imaging dynamic infrared focal plane, a readout circuit and a method for preparing the readout circuit. Background Art

[0002] Infrared imaging technology is widely used in complex environments such as low-light conditions and extremely high or extremely low background radiation. In these scenarios, infrared detectors need to be able to clearly capture and distinguish between high-radiation and low-radiation targets, which places high demands on the dynamic range of the detector.

[0003] The readout circuit is a key part of the infrared detector, responsible for converting the infrared radiation signal collected by the detector into an electrical signal and outputting image information. The dynamic range of the readout circuit is an important indicator of the imaging quality of the infrared detector and directly affects the imaging quality of the infrared detector.

[0004] The method of improving the dynamic range of the readout circuit in the related art is to use a multi-level integrating capacitor. This method adapts to radiation signals of different intensities by changing the capacitance of the integrating capacitor, thereby improving the dynamic range. However, using an integrating capacitor with a large capacitance will occupy more pixel area, which is unacceptable for some small pixel area focal planes that pursue high pixel density. Therefore, how to significantly improve the imaging dynamic range without sacrificing the focal plane pixel area has become an urgent need for high-quality infrared imaging to meet application scenarios such as low-light night vision and night-time assisted driving of automobiles. Summary of the invention

[0005] The present invention provides an ultra-large imaging dynamic infrared focal plane, a readout circuit and a method for preparing the readout circuit, which solve the problem in the related art of how to significantly improve the imaging dynamic range without sacrificing the focal plane pixel area.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a method for preparing a large-scale imaging dynamic infrared focal plane readout circuit is provided, comprising:

[0008] Dividing the focal plane array into a plurality of identical pixel blocks, each of which includes adjacent n×n pixels;

[0009] Determining the sub-integration time of each pixel in the pixel block according to the focal plane imaging dynamic range requirement and the imaging requirement;

[0010] According to the sub-integration time of each pixel in the pixel block, configuring the pixel-level integration circuit corresponding to the pixel with different sub-integration time;

[0011] A timing control circuit is configured to control the pixels of the entire focal plane array to simultaneously start integrating the detector photocurrent, the pixels with different sub-integration times are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port in the order of the pixel blocks;

[0012] Carry out layout design and tape-out, and prepare readout circuit.

[0013] In a first possible implementation manner of the first aspect, determining the sub-integration time of each pixel in the pixel block according to the focal plane imaging dynamic range requirement and the imaging requirement includes:

[0014] Determine a frame integration time, and divide the frame integration time into n×n sub-integration times;

[0015] Determining a proportional relationship between the longest sub-integration time and the shortest sub-integration time according to the focal plane imaging dynamic range requirement;

[0016] Determining the proportional relationship of the other sub-integration times according to the imaging requirement;

[0017] The sub-integration time of each of the picture elements is configured according to a proportional relationship.

[0018] In a second possible implementation manner of the first aspect, configuring the pixel-level integration circuits of the pixels corresponding to different sub-integration times according to the sub-integration time of each pixel in the pixel block includes:

[0019] Each pixel in each pixel block is equipped with an independent pixel-level integration circuit, and the pixel injection tube size corresponding to the pixel-level integration circuit is configured according to the injection efficiency, linearity, junction resistance and junction capacitance of the pixel.

[0020] In a third possible implementation manner of the first aspect, the readout circuit is configured to start reading data of a portion of the pixels that have completed integration while the pixels continue to integrate.

[0021] Based on any possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the timing control circuit is triggered according to an external clock signal.

[0022] In a second aspect, an ultra-large imaging dynamic infrared focal plane is provided, wherein the focal plane array includes a plurality of identical pixel blocks, each of the pixel blocks includes adjacent n×n pixels;

[0023] The focal plane readout circuit includes a pixel-level integration circuit and a timing control circuit;

[0024] Each of the pixels in the pixel block has a corresponding pixel-level integration circuit, and the pixel-level integration circuit is used to perform signal integration of the photocurrent signal received by the focal plane in the respective pixel-level integration circuit, and each of the pixels in the pixel block has a different sub-integration time;

[0025] The timing control circuit is used to control the pixels of the entire focal plane array to simultaneously start integrating the photocurrent of the focal plane detector, the pixels with different sub-integration times are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port in the order of the pixel blocks.

[0026] In a first possible implementation manner of the second aspect, the integral sub-time is determined according to a focal plane imaging dynamic range requirement and an imaging requirement, comprising the following steps:

[0027] Determine a frame integration time, and divide the frame integration time into n×n sub-integration times;

[0028] Determining a proportional relationship between the longest sub-integration time and the shortest sub-integration time according to the focal plane imaging dynamic range requirement;

[0029] Determining the proportional relationship of the other sub-integration times according to the imaging requirement;

[0030] The sub-integration time of each of the picture elements is configured according to a proportional relationship.

[0031] In a second possible implementation manner of the second aspect, the pixel-level integration circuit configures a pixel injection tube size corresponding to the pixel-level integration circuit according to the injection efficiency, linearity, junction resistance, and junction capacitance of the pixel.

[0032] In a third possible implementation of the second aspect, the readout circuit is configured to start reading data of a portion of the pixels that have completed integration while the pixels continue to integrate.

[0033] In a third aspect, an ultra-large imaging dynamic infrared focal plane readout circuit is provided, which is prepared according to the preparation method described in the first aspect.

[0034] The present application can significantly improve the imaging dynamic range without sacrificing the focal plane pixel area, and realize an ultra-large dynamic range infrared focal plane readout circuit. The present application forms a pixel block with an n×n pixel array, reasonably allocates the integration time of each pixel in the pixel block, and realizes the modulation of the infrared focal plane imaging dynamic range through the maximum integration time ratio. After each pixel completes the photoelectric signal integration through its own high injection efficiency and high linearity pixel unit circuit within its own integration time, the designed timing control circuit is used to realize the orderly output of each pixel according to the integration time length, which reduces the difficulty of large dynamic image processing and memory capacity of the back-end, and greatly improves the dynamic range of infrared focal plane imaging. Within a limited integration time, it provides a new technical solution for the large dynamic realization of infrared focal plane detectors with small pixel areas, and effectively solves the problem that the small pixel area cannot improve the dynamic range of focal plane imaging through an ultra-large integration capacitor ratio.

[0035] This application uses the triggering of the timing circuit by an external clock signal to achieve the synchronization of all pixels for photocurrent integration, and at the same time, the output signals of pixels with different integration times are output in an orderly manner from their corresponding ports, which reduces the difficulty of large dynamic image processing and memory capacity in the back-end. The method is simple and easy to operate and implement, reducing the need for complex timing control logic, thereby simplifying the architecture design of the entire system and facilitating subsequent maintenance and upgrades. At the same time, stable timing control helps to reduce errors caused by timing deviations, ensures the integrity and accuracy of image data, and thus improves the reliability and stability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic flow chart of a method for preparing a super-large imaging dynamic infrared focal plane readout circuit provided in an embodiment of the present application;

[0037] Figure 2 A focal plane full array 2×2 pixel block combination allocation block diagram provided in an embodiment of the present application;

[0038] Figure 3 A schematic block diagram of the principle of pixel readout with different integration times in pixel block order provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined purpose, the technical solutions in the embodiments of the present application are clearly described. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0040] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0041] The description of the method flow in the specification of the present application and the steps of the flowchart in the drawings of the present specification do not have to be strictly executed according to the step numbers, and the method steps can be executed in a different order. Moreover, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be decomposed into multiple steps.

[0042] The following is a detailed description of the ultra-large imaging dynamic infrared focal plane, readout circuit and readout circuit preparation method provided in the embodiments of the present application in combination with the accompanying drawings and preferred embodiments.

[0043] First, the application scenarios of the ultra-large imaging dynamic infrared focal plane, the readout circuit and the readout circuit preparation method of the embodiments of the present application are described in detail.

[0044] With the development of infrared imaging technology, the demand for detection under low-light conditions and high-quality imaging in complex environments such as extremely high and low backgrounds is becoming more and more urgent, such as low-light night vision infrared cameras, car night assisted driving and other application scenarios, which puts forward higher requirements on the dynamic range and anti-interference performance of the infrared focal plane. The larger the readout dynamic range, the better the readout circuit of the detector can process and output image information of targets and backgrounds in complex environments.

[0045] When imaging extremely high radiation energy targets and extremely low radiation energy targets simultaneously in the same scene, the detector imaging dynamics needs to reach 120dB or even higher. As the key to limiting the imaging dynamics of infrared detectors, the dynamic range of the infrared readout circuit needs to be further improved.

[0046] The method of improving the dynamic range of infrared readout circuit in related technology is to use multi-level integral capacitors. The higher the capacitance ratio between the integral capacitors, the larger the dynamic range of the readout circuit. However, large integral capacitors consume more pixel area, and this method is not suitable for focal planes with small pixel areas. In view of this, the present application explores a new working mode of the readout circuit to significantly improve the imaging dynamics of focal planes with small pixel areas.

[0047] This application breaks the integration method of consistent integration time for each pixel, groups adjacent pixels into pixel blocks, and uses a timing control circuit to modulate the integration time of each pixel in the pixel block on the focal plane, so that the integration time of each pixel in the pixel block is different. The ratio of the longest integration time to the shortest integration time is the improvement of the imaging dynamic range. At the same time, the timing control circuit is used to output pixels with the same integration time from the same port in an orderly manner. The pixel output is a large dynamic range image signal, which greatly reduces the difficulty of large dynamic image processing and memory capacity at the back end. The method of this application is not only easy to understand in principle, but also simpler in the later layout design, and it is very easy to implement.

[0048] See also Figure 1 , the present application embodiment provides a method for preparing a large imaging dynamic infrared focal plane readout circuit, such as Figure 1 As shown, the preparation method of the embodiment of the present application includes:

[0049] Step S1, dividing the focal plane array into a plurality of identical pixel blocks, each pixel block including adjacent n×n pixels.

[0050] The focal plane array is equally divided into N pixel blocks, and adjacent n×n pixel arrays are combined into a pixel block, which serves as a group of long-short integration units.

[0051] In the specific implementation process, when determining the size of n in each pixel block, factors such as the actual application conditions of the focal plane detector, the characteristics of the detection target, the pixel spacing, and the frame rate should be fully considered. In addition, when designing specifically, considering the difficulty of implementing the back-end signal processing, the number of pixels in each pixel block should not be too large, for example: n×n can usually be 2×2 or 3×3.

[0052] Step S2, determining the sub-integration time of each pixel in the pixel block according to the focal plane imaging dynamic range requirement and the imaging requirement.

[0053] Specifically include:

[0054] Step S201, determine the frame integration time, and divide the frame integration time into n×n sub-integration times.

[0055] Step S202: determining a proportional relationship between a longest sub-integration time and a shortest sub-integration time according to a focal plane imaging dynamic range requirement.

[0056] Step S203: determining the proportional relationship of other sub-integration times according to imaging requirements.

[0057] Step S204, configuring the sub-integration time of each pixel according to the proportional relationship.

[0058] In the specific implementation process, the proportional relationship between each sub-integration time is determined, and the limited one-frame time of the focal plane is divided into n×n different sub-integration times, and the sum of each sub-divided time is equal to one-frame integration time. The proportional relationship between the longest sub-integration time int_l and the shortest sub-integration time int_s determines the dynamic range of focal plane imaging, which needs to be determined according to the typical application scenario of the focal plane. In the pixel block, the sub-integration time of other pixels can be equally divided between the longest sub-integration time int_l and the shortest sub-integration time int_s, or can be allocated according to actual detection needs. For example, in some cases, some pixels may require longer integration times to capture weak signals, while others require shorter times to avoid overexposure.

[0059] Step S3, configuring pixel-level integration circuits corresponding to pixels with different sub-integration times according to the sub-integration time of each pixel in the pixel block.

[0060] Specifically, each pixel in each pixel block is configured with a set of independent pixel-level integration circuits, and the pixel injection tube size corresponding to the pixel-level integration circuit is configured according to the injection efficiency, linearity, junction resistance and junction capacitance of the pixel.

[0061] The pixel-level integration circuit is used to integrate the photocurrent signal received by the infrared focal plane detector in each pixel-level integration circuit. Since the detector photocurrent will increase sharply under short integration time, the size of the pixel-level integration circuit injection tube should be fully considered when designing the pixel-level integration circuit of pixels with different sub-integration times, so that the injection efficiency of photocurrents of different intensities can be maintained at a high level. If necessary, the size of the pixel-level integration circuit injection tube of each pixel in each pixel block may not be completely consistent. In addition, the matching of the junction resistance and junction capacitance of the infrared focal plane detector, as well as linearity and other factors should also be considered when designing the pixel-level integration circuit.

[0062] Step S4, configuring a timing control circuit to control all pixels in the entire focal plane array to simultaneously start integrating the detector photocurrent, pixels with different sub-integration times are read out in order from short to long, and pixels with the same sub-integration time are output from the same output port in the order of pixel blocks.

[0063] The working timing of the infrared focal plane readout circuit is designed so that all pixels in the entire focal plane array start to integrate the detector photocurrent at the same time, and the pixels with different sub-integration times in each pixel block are output from different output ports. That is to say, for all pixel blocks, the integration is in the order of the pixel blocks, and the pixels with the same sub-integration time are output from the same output port.

[0064] The setting of the working sequence of the readout circuit realizes the high frame rate working mode in which the pixels with the same integration time in each pixel block are read out in order, and the pixels with different integration times are read out in order from short to long. The pixel integration time is increased within a limited frame time to improve the sensitivity of the focal plane. In other words, in order to increase the pixel integration time within a limited frame time, the readout circuit is designed to be able to start reading the data of some pixels that have completed integration while the pixel continues to integrate. This mode is called the high frame rate working mode of "integrate while readout". This method allows the system to read out pixel data multiple times within a frame period, thereby achieving a higher frame rate.

[0065] Step S5, perform layout design and tape-out, and prepare a readout circuit.

[0066] Based on the design completed in steps S1-S5, the physical implementation of the layout is completed, and the processing and tape-out are carried out to finally obtain the ultra-large imaging dynamic infrared focal plane readout circuit chip. During the layout design, the pixels in a pixel block should be well isolated to prevent the electrical crosstalk between pixels caused by inconsistent integrated signals of each pixel.

[0067] The present application can significantly improve the imaging dynamic range without sacrificing the focal plane pixel area, and realize an ultra-large dynamic range infrared focal plane readout circuit. The present application forms a pixel block with an n×n pixel array, reasonably allocates the integration time of each pixel in the pixel block, and realizes the modulation of the infrared focal plane imaging dynamic range through the maximum integration time ratio. After each pixel completes the photoelectric signal integration through its own high injection efficiency and high linearity pixel unit circuit within its own integration time, the designed timing control circuit is used to realize the orderly output of each pixel according to the integration time length, which reduces the difficulty of large dynamic image processing and memory capacity of the back-end, and greatly improves the dynamic range of infrared focal plane imaging. Within a limited integration time, it provides a new technical solution for the large dynamic realization of infrared focal plane detectors with small pixel areas, and effectively solves the problem that the small pixel area cannot improve the dynamic range of focal plane imaging through an ultra-large integration capacitor ratio.

[0068] Exemplarily, a pixel block composed of 2×2 pixels is taken as an example to fully illustrate the above embodiment.

[0069] See also Figure 2, the 4 pixels of adjacent rows / columns are combined into a 2×2 pixel block. For an array specification of X×Y, there are a total of (X×Y) / 4 identical pixel blocks. The integration time of the 4 pixels in each 2×2 pixel block is int1, int2, int3, int4. The proportional relationship of the 4 integration times is designed according to the application scenario of the infrared focal plane and the actual detection requirements. In addition, the working integration time is allocated to the 4 pixels in the pixel block within a limited frame time. The ratio of the longest integration time to the shortest integration time determines the imaging dynamic range of the focal plane.

[0070] exist Figure 2 In the design, the four pixels in each pixel block are equipped with an independent pixel-level integration circuit to integrate the photocurrent signal generated by the detector pixel. The four pixels with different integration times in each pixel block will receive detector photocurrents of different intensities. In order to ensure that the four pixels in each pixel block have high injection efficiency and high linearity, the size of each pixel injection tube should be adjusted during design, and the changes in junction resistance and junction capacitance of the detector pixel in different working states should be considered.

[0071] See also Figure 3 In order to ensure that each pixel in the focal plane integrates the detector photocurrent signal at the same time, the array pixels are read out in an orderly manner, and at the same time reduce the difficulty of back-end large dynamic image processing and memory capacity, the following specific measures are taken in the design:

[0072] First, in order to achieve synchronization of photocurrent integration of all pixels and orderliness of output signals, the trigger generation circuit of the timing circuit module is integrated and read out the timing clock signals required for the working mode through the external clock signal.

[0073] Secondly, under the control of the readout circuit timing, all pixels with integration time int1 are stored in the MUX1 register from top to bottom in column order, and at the same time, pixels with integration time int2, int3, and int4 are stored in registers MUX2, MUX3, and MUX4 respectively from top to bottom in column order.

[0074] Again, in some possible implementations, in order to improve the driving capability of the output signal to the subsequent circuit, a unit-gain driving circuit is added to the back end of the four registers MUX1 to MUX4. After the voltage signal of each pixel in the register passes through the driving circuit, the final output voltage signal of the pixel is formed.

[0075] Finally, complete the physical implementation of the circuit layout and proceed to tape-out. When designing the layout, it is necessary to focus on the layout of the pixel-level circuit; considering the possible electrical crosstalk between the integrated signals of each pixel, the signal transmission lines must be isolated and shielded; the layout and wiring of each pixel within the pixel level should be as symmetrical as possible, and the grounding plates of the pixel integration capacitors should not be connected.

[0076] This application uses the triggering of the timing circuit by an external clock signal to achieve the synchronization of all pixels for photocurrent integration, and at the same time, the output signals of pixels with different integration times are output in an orderly manner from their corresponding ports, which reduces the difficulty of large dynamic image processing and memory capacity in the back-end. The method is simple and easy to operate and implement, reducing the need for complex timing control logic, thereby simplifying the architecture design of the entire system and facilitating subsequent maintenance and upgrades. At the same time, stable timing control helps to reduce errors caused by timing deviations, ensures the integrity and accuracy of image data, and thus improves the reliability and stability of the entire system.

[0077] Based on the above-mentioned method for preparing a super-large imaging dynamic infrared focal plane readout circuit, the embodiment of the present application provides a super-large imaging dynamic infrared focal plane readout circuit, which is prepared according to the above-mentioned preparation method. It implements the steps of the above-mentioned method for preparing a super-large imaging dynamic infrared focal plane readout circuit embodiment and each process of the embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0078] Based on the above-mentioned ultra-large imaging dynamic infrared focal plane readout circuit preparation method, the embodiment of the present application provides an ultra-large imaging dynamic infrared focal plane, the focal plane array includes a plurality of identical pixel blocks, each pixel block includes adjacent n×n pixels;

[0079] The focal plane readout circuit includes a pixel-level integration circuit and a timing control circuit;

[0080] Each pixel in the pixel block has a corresponding pixel-level integration circuit, and the pixel-level integration circuit is used to integrate the photocurrent signal received by the focal plane in the respective pixel-level integration circuit, and each pixel in the pixel block has a different sub-integration time;

[0081] The timing control circuit is used to control all pixels of the entire focal plane array to start integrating the photocurrent of the focal plane detector at the same time, and the pixels with different sub-integration times are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port in the order of the pixel blocks.

[0082] Furthermore, the integration sub-time is determined according to the focal plane imaging dynamic range requirement and the imaging requirement, including the following steps:

[0083] Determine a frame integration time, and divide the frame integration time into n×n sub-integration times;

[0084] According to the requirements of the dynamic range of focal plane imaging, the ratio between the longest sub-integration time and the shortest sub-integration time is determined;

[0085] According to the imaging requirements, determine the proportional relationship of other sub-integration times;

[0086] Configure the sub-integration time for each pixel based on the proportional relationship.

[0087] Furthermore, the pixel-level integration circuit configures the pixel injection tube size corresponding to the pixel-level integration circuit according to the injection efficiency, linearity, junction resistance and junction capacitance of the pixel.

[0088] Further, the readout circuit is configured to be able to start reading data of some of the pixels that have completed integration while the pixels continue to integrate.

[0089] The readout circuit of the above-mentioned ultra-large imaging dynamic infrared focal plane is prepared based on the steps and various processes of the above-mentioned ultra-large imaging dynamic infrared focal plane readout circuit preparation method embodiment, and can achieve the same technical effect. In order to avoid repetition, it will not be repeated here.

[0090] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0091] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for preparing a large-scale imaging dynamic infrared focal plane readout circuit, characterized in that: include: Dividing the focal plane array into a plurality of identical pixel blocks, each of which includes adjacent n×n pixels; Determining the sub-integration time of each pixel in the pixel block according to the focal plane imaging dynamic range requirement and the imaging requirement; According to the sub-integration time of each pixel in the pixel block, configuring the pixel-level integration circuit corresponding to the pixel with different sub-integration time; A timing control circuit is configured to control the pixels of the entire focal plane array to simultaneously start integrating the detector photocurrent, the pixels with different sub-integration times are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port in the order of the pixel blocks; Carry out layout design and tape-out, and prepare readout circuit.

2. The method for preparing a super-large imaging dynamic infrared focal plane readout circuit according to claim 1, characterized in that: The step of determining the sub-integration time of each pixel in the pixel block according to the focal plane imaging dynamic range requirement and the imaging requirement includes: Determine a frame integration time, and divide the frame integration time into n×n sub-integration times; Determining a proportional relationship between the longest sub-integration time and the shortest sub-integration time according to the focal plane imaging dynamic range requirement; Determining the proportional relationship of the other sub-integration times according to the imaging requirement; The sub-integration time of each of the picture elements is configured according to a proportional relationship.

3. The method for preparing a super-large imaging dynamic infrared focal plane readout circuit according to claim 1, characterized in that: The configuration of the pixel-level integration circuits of the pixels corresponding to different sub-integration times according to the sub-integration time of each pixel in the pixel block comprises: Each pixel in each pixel block is equipped with an independent pixel-level integration circuit, and the pixel injection tube size corresponding to the pixel-level integration circuit is configured according to the injection efficiency, linearity, junction resistance and junction capacitance of the pixel.

4. The method for preparing a super large imaging dynamic infrared focal plane readout circuit according to claim 1, characterized in that: The readout circuit is configured to be able to start reading data of a portion of the picture elements that have completed integration while the picture elements continue to integrate.

5. The method for preparing a super-large imaging dynamic infrared focal plane readout circuit according to any one of claims 1 to 4, characterized in that: The timing control circuit is triggered according to the external clock signal.

6. Ultra-large imaging dynamic infrared focal plane, characterized by: The focal plane array includes a plurality of identical pixel blocks, each of which includes adjacent n×n pixels; The focal plane readout circuit includes a pixel-level integration circuit and a timing control circuit; Each of the pixels in the pixel block has a corresponding pixel-level integration circuit, and the pixel-level integration circuit is used to perform signal integration of the photocurrent signal received by the focal plane in the respective pixel-level integration circuit, and each of the pixels in the pixel block has a different sub-integration time; The timing control circuit is used to control the pixels of the entire focal plane array to simultaneously start integrating the photocurrent of the focal plane detector, the pixels with different sub-integration times are read out in order from short to long, and the pixels with the same sub-integration time are output from the same output port in the order of the pixel blocks.

7. The ultra-large imaging dynamic infrared focal plane according to claim 6, characterized in that: The integration sub-time is determined according to the focal plane imaging dynamic range requirement and the imaging requirement, and includes the following steps: Determine a frame integration time, and divide the frame integration time into n×n sub-integration times; Determining a proportional relationship between the longest sub-integration time and the shortest sub-integration time according to the focal plane imaging dynamic range requirement; Determining the proportional relationship of the other sub-integration times according to the imaging requirement; The sub-integration time of each of the picture elements is configured according to a proportional relationship.

8. The ultra-large imaging dynamic infrared focal plane according to claim 6, characterized in that: The pixel-level integration circuit configures the pixel injection tube size corresponding to the pixel-level integration circuit according to the injection efficiency, linearity, junction resistance and junction capacitance of the pixel.

9. The ultra-large imaging dynamic infrared focal plane according to claim 6, characterized in that: The readout circuit is configured to be able to start reading data of a portion of the picture elements that have completed integration while the picture elements continue to integrate.

10. Ultra-large imaging dynamic infrared focal plane readout circuit, characterized in that ， The preparation is carried out according to the preparation method according to any one of claims 1 to 5.

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