Power device and preparation method thereof

Abstract

The invention discloses a power device and a preparation method thereof, and the preparation method comprises the following steps: providing an epitaxial layer doped with a first conductive material, forming a well region in the epitaxial layer, and forming an active region in the well region; a first shielding part is arranged above one side of the epitaxial layer, the epitaxial layer which is not covered by the first shielding part is doped with a first conductive material to form a first region, and the doping concentration of the first region is larger than that of the epitaxial layer; etching the first region to obtain a second region, and doping a second conductive material on the bottom wall of the second region to form a shielding region; and forming a thick oxygen structure in contact with the first region and the shielding region in the second region. According to the invention, the conduction performance and reliability of the power device can be improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a power device and a method for manufacturing the same. Background Art

[0002] As a common power device, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has two structural forms: planar and trench. Among them, the gate of the planar MOSFET is located on the top surface of the power device and is arranged parallel to the substrate.

[0003] Compared with trench MOSFET, planar MOSFET has the advantages of simple structure, simple preparation process, and strong voltage resistance, but its conduction performance and reliability need to be further improved. Summary of the invention

[0004] The embodiment of the present application provides a power device and a method for manufacturing the same, which introduces a shielding region into a JFET region of a planar power device to improve the conduction performance and reliability of the power device.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a power device, the method comprising:

[0006] Providing an epitaxial layer doped with a first conductive material, forming a well region in the epitaxial layer, and forming an active region in the well region;

[0007] A first shielding portion is provided above one side of the epitaxial layer, and a first conductive material is doped into the epitaxial layer not covered by the first shielding portion to form a first region, wherein the doping concentration of the first region is greater than the doping concentration of the epitaxial layer;

[0008] Etching the first region to obtain a second region, and doping a second conductive material into a bottom wall of the second region to form a shielding region;

[0009] A thick oxide structure is formed in the second region to contact the first region and the shielding region.

[0010] In some embodiments, the step of forming a well region in the epitaxial layer and forming an active region in the well region includes:

[0011] The epitaxial layer has a first portion and a second portion, a first mask sub-portion is arranged above one side of the first portion, and the first portion is doped with a second conductive material to form a well region;

[0012] A second mask sub-section is added above the first section, and a third mask sub-section is arranged above the second section, and the epitaxial layer is doped with a first conductive material to form an active region in the well region and a stop ring in the second section.

[0013] In some embodiments, the step of etching the first region to obtain the second region, and doping the bottom wall of the second region with a second conductive material to form a shielding region comprises:

[0014] A second shielding portion is disposed above one side of the first portion, the second shielding portion at least covers a portion of the first area, and the first portion not covered by the second shielding portion is etched to obtain a second area;

[0015] A third shielding portion is disposed above the second portion, and a second conductive material is doped into the bottom wall of the second region and the second portion not covered by the third shielding portion, so that a shielding region is formed in the first region and a junction terminal structure is formed in the second portion.

[0016] In some embodiments, the junction termination structure is formed by an ion implantation process, and the doping concentration of the junction termination structure is less than the doping concentration of the well region.

[0017] In some embodiments, the power device manufacturing method further includes:

[0018] A sacrificial layer is disposed above the junction terminal structure, and the sacrificial layer is etched to form a shallow groove structure, and a distance h between the shallow groove structure and the junction terminal structure remains unchanged or decreases in a direction away from the first portion.

[0019] In some embodiments, the step of forming a thick oxide structure in the second region that contacts the first region and the shielding region comprises:

[0020] epitaxially growing an oxide layer in the second region and on the epitaxial layer;

[0021] A fourth shielding portion is disposed above the oxide layer, and the oxide layer not covered by the fourth shielding portion is etched to form a thick oxide structure in the second region that contacts the first region and the shielding region, and a passivation layer is formed above the second portion.

[0022] In some embodiments, the orthographic projection of the second region on the epitaxial layer is consistent with the orthographic projection of the shielding region on the epitaxial layer, or the orthographic projection of the second region on the epitaxial layer falls within the orthographic projection of the shielding region on the epitaxial layer.

[0023] In some embodiments, the step of doping the epitaxial layer not covered by the first shielding portion with the first conductive material to form the first region includes performing a high temperature annealing process on the first region.

[0024] In some embodiments, the power device manufacturing method further includes:

[0025] The well region is doped with a second conductive material to form a heavily doped region, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the well region.

[0026] In the second aspect, an embodiment of the present application provides a power device, which is prepared based on the power device preparation method provided by any of the aforementioned embodiments, and the power device includes an epitaxial layer, a well region located in the epitaxial layer, a guide region located in the epitaxial layer, a shielding region located in the guide region, and a thick oxygen structure located in the guide region, wherein the well region is located on the first surface of the epitaxial layer; the guide region is located on the first surface of the epitaxial layer and between two adjacent well regions, and the ion doping concentration of the guide region is greater than the ion doping concentration of the epitaxial layer; the shielding region is arranged in contact with the epitaxial layer, and both sides of the shielding region along the first direction are arranged in contact with the guide region; the thick oxygen structure is located above the shielding region; wherein the epitaxial layer and the guide region are of the first conductivity type, and the well region and the shielding region are of the second conductivity type.

[0027] The power device manufacturing method of the embodiment of the present application reduces the on-resistance of the power device in the epitaxial layer by forming a first region with a higher ion doping concentration in the epitaxial layer. The manufacturing method forms a shielding region with an opposite conductivity type in the first region to adjust the electric field distribution of the first region, and at the same time, a thick oxide structure is arranged above the shielding region to cooperate with the shielding region to protect the gate oxide layer, reduce the probability of breakdown of the gate oxide layer above the first region, and improve the reliability of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0029] Figure 1 A schematic diagram of the structure of a power device in some embodiments of the present application;

[0030] Figure 2 A schematic diagram of the structure of a power device in some embodiments of the present application;

[0031] Figure 3 A schematic diagram of the structure of a power device in some embodiments of the present application;

[0032] Figure 4 A schematic diagram of a process for preparing a power device according to some embodiments of the present application;

[0033] Figure 5 A schematic diagram of a sub-process of a method for preparing a power device according to some embodiments of the present application;

[0034] Figure 6 A schematic diagram of a sub-process of a method for preparing a power device according to some embodiments of the present application;

[0035] Figure 7 A schematic diagram of a sub-process of a method for preparing a power device according to some embodiments of the present application;

[0036] Figure 8a to Figure 8h This is a schematic diagram of the process structure of a power device manufacturing method according to some embodiments of the present application.

[0037] The reference numerals in the specific implementation manner are as follows:

[0038] 10, first part; 100, cell region; 101, first region; 102, second region; 110, epitaxial layer; 120, well region; 121, active region; 122, heavily doped region; 130, guide region; 140, shielding region; 150, thick oxide structure;

[0039] 20, second part; 200, terminal area; 210, expansion area; 220, slope groove; 230, stop ring; 240, passivation layer;

[0040] 310, gate oxide layer; 320, gate; 330, isolation dielectric layer; 340, source; 350, drain;

[0041] First direction X; second direction Y. DETAILED DESCRIPTION

[0042] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0044] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0047] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0048] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0049] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0050] In order to solve the problems of the prior art, the embodiments of the present application provide a power device and a method for preparing the same. The power device provided by the embodiments of the present application is first introduced below.

[0051] See also Figure 1The embodiment of the present application provides a power device, which includes an epitaxial layer 110, a well region 120, and a guide region 130. The well region 120 is formed by extending from the first surface of the epitaxial layer 110 into the epitaxial layer 110. The guide region 130 is provided in two adjacent well regions 120 along the first direction. The guide region 130 is formed by extending from the first surface of the epitaxial layer 110 into the epitaxial layer 110. The guide region 130 and the epitaxial layer 110 are both of the first conductivity type, and the ion doping concentration of the guide region 130 is greater than the ion doping concentration of the epitaxial layer 110; the well region 120 is of the second conductivity type.

[0052] It can be understood that the first conductivity type is opposite to the second conductivity type, that is, the first conductivity type is one of N-type ion doping or P-type ion doping, and the second conductivity type is the other of N-type ion doping or P-type ion doping. Exemplarily, the first conductivity type is N-type ion doping, and the second conductivity type is P-type ion doping.

[0053] Therefore, the conduction region 130 is introduced into the JFET region which is unique to the planar power device. The conduction region 130 with a higher ion doping concentration has a lower resistivity, thereby reducing the on-resistance of the planar power device.

[0054] Furthermore, the power device also includes a shielding area 140 located in the guide area 130, the shielding area 140 is set to a second conductivity type opposite to the guide area 130, the shielding area 140 is set in contact with the epitaxial layer 110, and both sides of the shielding area 140 along the first direction are set in contact with the guide area 130.

[0055] Thus, the shielding region 140 can at least partially offset the significant increase in the electric field strength of the gate oxide layer 310 caused by the provision of the guide region 130, reduce the probability of breakdown of the gate oxide layer 310 above the guide region 130, and improve the voltage resistance performance of the planar power device.

[0056] Furthermore, the power device further includes a thick oxide structure 150 located in the guide region 130 , and the thick oxide structure 150 is disposed above the shielding region 140 along the second direction.

[0057] Optionally, the thick oxide structure 150 is flush with the first surface of the epitaxial layer 110 to facilitate the preparation of the gate oxide layer 310 later.

[0058] Optionally, the thick oxide structure 150 is made of silicon dioxide material.

[0059] Optionally, the thick oxide structure 150 is made of an insulating oxide material that is inconsistent with the gate oxide layer 310 .

[0060] Thus, the thick oxide structure 150 can cooperate with the shielding area 140 to weaken the increase of the electric field of the gate oxide layer 310 caused by the setting of the diversion area 130. After the thick oxide structure 150 is introduced, the ion doping concentration of the shielding area 140 can be appropriately reduced, while maintaining the same protection effect, reducing the negative impact of the shielding area 140 on the conduction performance of the power device.

[0061] Optionally, the power device is a vertical double diffusion metal-oxide semiconductor field effect transistor (Vertical Double Diffusion Metal-Oxide-Semiconductor Field Effetct Transistor, VDMOS) or an insulated gate bipolar transistor (Insulate-Gate Bipolar Transistor, IGBT).

[0062] Further optionally, the VDMOS includes silicon-based VDMOS and silicon carbide-based VDMOS.

[0063] See also Figure 1 According to certain embodiments of the present application, the power device further includes a heavily doped region 122 located in the well region 120 , the heavily doped region 122 is of the second conductivity type and the ion doping concentration of the heavily doped region 122 is greater than the ion doping concentration of the well region 120 .

[0064] Optionally, the heavily doped region 122 is disposed in contact with the active region 121 in the well region 120 , and along the second direction, the depth of the heavily doped region 122 is greater than or equal to the depth of the active region 121 .

[0065] Optionally, the heavily doped region 122 is formed by extending from the first surface of the epitaxial layer 110 into the well region 120 .

[0066] Therefore, the resistance of the well region 120 is adjusted to reduce the voltage drop of the well region 120, improve the latch effect in the power device, and enhance the reliability of the power device.

[0067] According to some embodiments of the present application, the guide region 130 is disposed at the center between two adjacent well regions 120 , that is, along the first direction, the midpoint of the guide region 130 coincides with the midpoint of the JFET region formed between the two adjacent well regions 120 .

[0068] Optionally, along the second direction, the depth of the guide region 130 is less than the depth of the well region 120 .

[0069] Optionally, the guide region 130 is disposed in contact with the well region 120 .

[0070] Optionally, the guide region 130 and the well region 120 are spaced apart by the epitaxial layer 110 .

[0071] Further optionally, along the first direction, the length of the guide region 130 accounts for greater than or equal to 70% of the length of the JFET region. Exemplarily, the length of the guide region 130 accounts for 5 / 7 of the length of the JFET region.

[0072] According to some embodiments of the present application, the ion doping concentration of the shielding region 140 is lower than the ion doping concentration of the well region 120 .

[0073] Optionally, the bottom of the shielding area 140 is flush with the bottom of the guide area 130 .

[0074] Optionally, along the second direction, the depth of the shielding region 140 is greater than the depth of the thick oxide structure 150 .

[0075] Optionally, along the first direction, the width of the shielding area 140 accounts for more than 30% and less than 1 of the width of the guide area 130. Exemplarily, the width of the shielding area 140 accounts for 40% of the width of the guide area 130.

[0076] According to some embodiments of the present application, the orthographic projection of the thick oxide structure 150 on the shielding region 140 falls within the shielding region 140, that is, along the first direction, the width of the thick oxide structure 150 is less than or equal to the width of the shielding region 140. Exemplarily, the width of the thick oxide structure 150 is equal to the width of the shielding region 140.

[0077] Optionally, along the second direction, the depth of the thick oxide structure 150 is greater than the depth of the gate oxide layer 310 between the gate 320 and the epitaxial layer 110 .

[0078] See also Figure 2 According to certain embodiments of the present application, the epitaxial layer 110 includes a cell region 100 and a terminal region 200 , and the terminal region 200 of the epitaxial layer 110 forms a junction terminal structure, the junction terminal structure is of the second conductivity type, and the ion doping concentration of the junction terminal structure is lower than the ion doping concentration of the well region 120 .

[0079] Optionally, referring to the figure, the junction terminal structure includes at least two extension regions 210, and at least two extension regions 210 are arranged in contact along the first direction. Among two adjacent extension regions 210, the depth of the extension region 210 close to the cell region 100 in the second direction is greater than the depth of the extension region 210 far from the cell region 100 in the second direction.

[0080] As a result, the anti-breakdown performance of the terminal part of the power device is improved while the area of ​​the power device is reduced, the on-resistance per unit area of ​​the power device is reduced, and the on-performance is improved.

[0081] See also Figure 2 or Figure 3According to some embodiments of the present application, the power device further includes a shallow trench structure, which is formed above the junction terminal structure along the second direction.

[0082] Optionally, the shallow groove structure includes a slope groove 220 , and a side of the slope groove 220 close to the cell region 100 is higher than a side away from the cell region 100 .

[0083] Optionally, the shallow groove structure includes at least two slope grooves 220 , and among two adjacent slope grooves 220 , the depth of the slope groove 220 close to the cell area 100 in the second direction is less than the depth of the slope groove 220 far from the cell area 100 in the second direction.

[0084] Optionally, the number of the slope grooves 220 and the expansion areas 210 are equal and are arranged in a one-to-one correspondence.

[0085] Further optionally, the slope groove 220 is disposed at a middle position of the expansion area 210 along the second direction.

[0086] Further optionally, along the second direction, the slope groove 220 is aligned with the edge of the expansion area 210 .

[0087] Therefore, the ion implantation distribution area of ​​the junction terminal structure is further adjusted through the shallow trench structure to form an ion concentration gradient to alleviate the electric field concentration phenomenon at the main junction and improve the reverse blocking capability of the power device.

[0088] According to some embodiments of the present application, the power device further includes a passivation layer 240 , and the passivation layer 240 is disposed above the epitaxial layer 110 in the terminal region 200 along the first direction.

[0089] Optionally, the passivation layer 240 is an insulating material layer.

[0090] Optionally, the passivation layer 240 is made of the same material as the thick oxide structure 150 .

[0091] According to some embodiments of the present application, the power device further includes a cut-off ring 230 . The cut-off ring 230 is of the first conductivity type and is disposed at the outer edge of the terminal region 200 of the epitaxial layer 110 .

[0092] Optionally, the ion doping concentration of the stop ring 230 is greater than the ion doping concentration of the epitaxial layer 110 .

[0093] Optionally, along the second direction, the stop ring 230 and the junction termination structure are spaced apart from each other by the epitaxial layer 110 .

[0094] On the other hand, the present invention also provides a method for preparing a power device, which can be used to manufacture Figures 1 to 3 For the power devices shown in Figure 4 and Figure 8a to Figure 8h, the power device preparation method comprises:

[0095] S100 , providing an epitaxial layer 110 doped with a first conductive material, forming a well region 120 in the epitaxial layer 110 , and forming an active region 121 in the well region 120 ;

[0096] S200, disposing a first shielding portion above one side of the epitaxial layer 110, and doping the epitaxial layer 110 not covered by the first shielding portion with a first conductive material to form a first region 101, wherein the doping concentration of the first region 101 is greater than the doping concentration of the epitaxial layer 110;

[0097] S300, etching the first region 101 to obtain the second region 102, and doping the bottom wall of the second region 102 with a second conductive material to form a shielding region 140;

[0098] S400 , forming a thick oxide structure 150 in the second region 102 , the thick oxide structure 150 being in contact with the first region 101 and the shielding region 140 .

[0099] According to an embodiment of the present application, a method for preparing a power device first forms a first region 101 with a higher ion doping concentration in the epitaxial layer 110 to reduce the on-resistance of the power device at the epitaxial layer 110, and then etches the second region 102 in the first region 101 to form a shielding region 140 located below the second region 102 and a thick oxide structure 150 located inside the second region 102, respectively, to adjust the increase in local electric field strength caused by the high doping concentration of the first region 101, thereby reducing the probability of breakdown of the gate oxide layer 310 above the first region 101, thereby improving the on-performance of the power device and enhancing the reliability of the power device.

[0100] It is understandable that the first conductive material and the second conductive material have opposite conductivity types. Exemplarily, the first conductive material is an N-type conductive ion, and the second conductive material is a P-type conductive ion.

[0101] See also Figure 5 and Figure 8a , Figure 8c According to some embodiments of the present application, in the method for preparing a power device, step S100 includes:

[0102] S110, providing a substrate doped with a first conductive material, and growing an epitaxial layer 110 on the substrate;

[0103] S130, the epitaxial layer 110 has a first portion 10 and a second portion 20, a first mask sub-portion is disposed above one side of the first portion 10, and the first portion 10 is doped with a second conductive material to form a well region 120;

[0104] S150 , adding a second mask sub-section above the first section 10 , setting a third mask sub-section above the second section 20 , doping the epitaxial layer 110 with a first conductive material, forming an active region 121 in the well region 120 , and forming a stop ring 230 in the second section 20 .

[0105] Optionally, in step S130 , the first portion 10 is doped with the second conductive material by an ion implantation process or a diffusion process.

[0106] Optionally, in step S130 , the first part 10 is used to prepare the cellular region 100 , and the second part 20 is used to prepare the terminal region 200 .

[0107] Optionally, in step S150 , the epitaxial layer 110 is doped with the first conductive material by an ion implantation process.

[0108] See also Figure 8b According to some embodiments of the present application, in the method for preparing a power device, step S100 further includes:

[0109] S140 , adding a fourth mask sub-portion above the first portion 10 , and doping the well region 120 with a second conductive material to form a heavily doped region 122 , wherein the doping concentration of the heavily doped region 122 is greater than the doping concentration of the well region 120 .

[0110] Optionally, in step S140 , the well region 120 is doped with a second conductive material by an ion implantation process or a diffusion process.

[0111] According to some embodiments of the present application, step S200 further includes performing a high temperature annealing treatment on the first region 101 .

[0112] See also Figure 6 and Figure 8d to Figure 8e According to some embodiments of the present application, in the method for preparing a power device, step S300 includes:

[0113] S310, disposing a second shielding portion above one side of the first portion 10, the second shielding portion at least covering a portion of the first area 101, and etching the first portion 10 not covered by the second shielding portion to obtain the second area 102;

[0114] S330, setting a third shielding portion above the second portion 20, doping the bottom wall of the second region 102 and the second portion 20 not covered by the third shielding portion with a second conductive material, forming a shielding region 140 in the first region 101 and forming a junction terminal structure in the second portion 20 at the same time.

[0115] Optionally, in step S310 , the etching process includes at least one of plasma etching and reactive ion etching.

[0116] Optionally, in step S330 , the orthographic projection of the shielding area 140 on the epitaxial layer 110 is consistent with the orthographic projection of the second area 102 on the epitaxial layer 110 , or the orthographic projection of the second area 102 on the epitaxial layer 110 falls within the orthographic projection of the shielding area 140 on the epitaxial layer 110 .

[0117] Optionally, in step S330 , the second portion 20 is doped with a second conductive material by an ion implantation process.

[0118] Optionally, in step S330, the extension region 210 and the shielding region 140 in the junction termination structure far from the first portion 10 are formed simultaneously, or the extension region 210 and the shielding region 140 in the junction termination structure close to the first portion 10 are formed simultaneously.

[0119] Optionally, in step S330, the third shielding portion is photoresist.

[0120] Thus, a shielding region 140 of the second conductivity type is formed in the first region 101 , and at the same time, other regions in the first region 101 form a conducting region 130 of the first conductivity type.

[0121] According to some embodiments of the present application, in the method for preparing a power device, step S300 further includes:

[0122] S320, etching the second portion 20 multiple times to obtain a step-shaped injection window.

[0123] See also Figure 2 , Figure 6 and Figure 8f According to some embodiments of the present application, step S300 further includes:

[0124] S350, a sacrificial layer is disposed above the junction terminal structure, and the sacrificial layer is etched to form a shallow groove structure, and along a direction away from the first portion 10, a distance h between the shallow groove structure and the junction terminal structure remains unchanged or decreases.

[0125] Optionally, in step S350 , deposition is performed multiple times on the junction termination structure to form an inverted step-shaped sacrificial layer.

[0126] Optionally, in step S350, a sacrificial layer with a uniform thickness is disposed above the junction terminal structure, and the sacrificial layer is etched multiple times to form an inverted step-shaped shallow groove structure.

[0127] See also Figure 7 and Figure 8g According to some embodiments of the present application, step S400 includes:

[0128] S410, epitaxially growing an oxide layer in the second region 102 and the epitaxial layer 110;

[0129] S430 , disposing a fourth shielding portion above the oxide layer, etching the oxide layer not covered by the fourth shielding portion, forming a thick oxide structure 150 in contact with the first region 101 and the shielding region 140 in the second region 102 , and forming a passivation layer 240 above the second portion 20 .

[0130] Optionally, in step S410 , an oxide layer is grown in the second region 102 by a high temperature wet oxidation process.

[0131] See also Figure 8h According to some embodiments of the present application, the power device manufacturing method further includes:

[0132] S500 , forming a gate oxide layer 310 , a gate 320 , an isolation dielectric layer 330 , and a source 340 on the first surface of the epitaxial layer 110 , and forming a drain 350 below the substrate.

[0133] Optionally, in step S500 , the gate oxide layer 310 is formed by a low-temperature dry oxidation process.

[0134] Optionally, in step S500 , the gate 320 is formed by depositing polysilicon and etching.

[0135] Optionally, in step S500 , the isolation dielectric layer 330 is formed by a deposition process.

[0136] Optionally, in step S500 , forming the source 340 includes: etching the isolation dielectric layer 330 to form a contact hole and expose at least a portion of the active area 121 , and preparing the source 340 in the contact hole to electrically connect the source 340 to the active area 121 .

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A method for preparing a power device, characterized in that: include: Providing an epitaxial layer doped with a first conductive material, forming a well region in the epitaxial layer, and forming an active region in the well region; A first shielding portion is provided above one side of the epitaxial layer, and a first conductive material is doped into the epitaxial layer not covered by the first shielding portion to form a first region, wherein the doping concentration of the first region is greater than the doping concentration of the epitaxial layer; Etching the first region to obtain a second region, and doping a second conductive material into a bottom wall of the second region to form a shielding region; A thick oxide structure is formed in the second region to contact the first region and the shielding region.

2. The method for preparing a power device according to claim 1, characterized in that: The steps of forming a well region in the epitaxial layer and forming an active region in the well region include: The epitaxial layer has a first portion and a second portion, a first mask sub-portion is arranged above one side of the first portion, and the first portion is doped with a second conductive material to form a well region; A second mask sub-section is added above the first section, and a third mask sub-section is arranged above the second section, and the epitaxial layer is doped with a first conductive material to form an active region in the well region and a stop ring in the second section.

3. The method for preparing a power device according to claim 2, characterized in that: The step of etching the first region to obtain the second region, and doping the bottom wall of the second region with a second conductive material to form a shielding region comprises: A second shielding portion is disposed above one side of the first portion, the second shielding portion at least covers a portion of the first area, and the first portion not covered by the second shielding portion is etched to obtain a second area; A third shielding portion is disposed above the second portion, and a second conductive material is doped into the bottom wall of the second region and the second portion not covered by the third shielding portion, so that a shielding region is formed in the first region and a junction terminal structure is formed in the second portion.

4. The method for preparing a power device according to claim 3, characterized in that: The junction terminal structure is formed by an ion implantation process, and the doping concentration of the junction terminal structure is less than the doping concentration of the well region.

5. The method for preparing a power device according to claim 3, characterized in that: The power device preparation method also includes: A sacrificial layer is disposed above the junction terminal structure, and the sacrificial layer is etched to form a shallow groove structure, and a distance h between the shallow groove structure and the junction terminal structure remains unchanged or decreases in a direction away from the first portion.

6. The method for preparing a power device according to claim 5, characterized in that: The step of forming a thick oxide structure in the second region in contact with the first region and the shielding region comprises: epitaxially growing an oxide layer in the second region and on the epitaxial layer; A fourth shielding portion is disposed above the oxide layer, and the oxide layer not covered by the fourth shielding portion is etched to form a thick oxide structure in the second region that contacts the first region and the shielding region, and a passivation layer is formed above the second portion.

7. The method for preparing a power device according to claim 1, characterized in that: The orthographic projection of the second region on the epitaxial layer is consistent with the orthographic projection of the shielding region on the epitaxial layer, or the orthographic projection of the second region on the epitaxial layer falls within the orthographic projection of the shielding region on the epitaxial layer.

8. The method for preparing a power device according to claim 1, characterized in that: The step of doping the epitaxial layer not covered by the first shielding portion with the first conductive material to form the first region includes performing a high temperature annealing process on the first region.

9. The method for preparing a power device according to claim 1, characterized in that: The power device preparation method also includes: The well region is doped with a second conductive material to form a heavily doped region, wherein the doping concentration of the heavily doped region is greater than the doping concentration of the well region.

10. A power device, characterized in that: The method for preparing a power device according to any one of claims 1 to 9 comprises: Epitaxial layer, a well region located in the epitaxial layer, wherein the well region is located on a first surface of the epitaxial layer; A guide region located in the epitaxial layer, the guide region is located on the first surface of the epitaxial layer and between two adjacent well regions, and the ion doping concentration of the guide region is greater than the ion doping concentration of the epitaxial layer; A shielding area located in the guide area, the shielding area is arranged in contact with the epitaxial layer, and both sides of the shielding area along the first direction are arranged in contact with the guide area; a thick oxygen structure located in the guide area, wherein the thick oxygen structure is located above the shielding area; The epitaxial layer and the guide region are of the first conductivity type, and the well region and the shielding region are of the second conductivity type.

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