Computing device

Abstract

The invention relates to the technical field of computing equipment, in particular to computing equipment. A computing device includes a logic device, a controller, and a plurality of single boards. Wherein the logic device is connected with at least one single board, the controller is respectively connected with the plurality of single boards, and the controller is connected with the logic device. The logic device is used for configuring the address of the target device on at least one single board, and the addresses of the target devices on the multiple single boards are different. And the controller communicates with the target device on the corresponding single board based on the different addresses. Therefore, when the controller in the application communicates with the target devices on the plurality of single boards, the target devices can be identified, and addresses of the target devices on the plurality of single boards connected with the controller are prevented from conflicting. Moreover, the computing equipment provided by the embodiment of the invention can prevent the addresses of the target devices on the plurality of single boards from conflicting without additionally adding hardware, so that the hardware cost and the system complexity of the computing equipment can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computing devices, and in particular, to a computing device. Background Art

[0002] The Inter-Integrated Circuit (I2C) bus is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). It is mainly used for short-distance communication between low-speed microcontrollers and peripheral devices.

[0003] For complex hardware systems, such as a scenario where a baseboard management controller (BMC) connects multiple boards through the same I2C bus, the boards are used for onboard I2C devices, and the I2C devices are used to store relevant information for the BMC to obtain through the I2C bus. When the circuits on multiple boards are exactly the same, manufacturers generally configure the same I2C address to the corresponding I2C devices on different boards. When these multiple boards are used in the same server, multiple I2C devices connected to the same I2C bus will have address conflicts. Summary of the invention

[0004] The embodiment of the present application provides a computing device, including multiple single boards, a logic device and a controller, wherein the logic device is respectively connected to at least one single board, the controller is respectively connected to multiple single boards, and the controller is connected to the logic device. The logic device is used to configure the address of the target device on at least one single board, wherein the addresses of the target devices on the multiple single boards are different; the target devices are devices of the same type. The controller communicates with the target devices on the corresponding single board based on different addresses.

[0005] In the embodiment of the present application, the address of the target device on at least one single board is configured by a logic device, so that the addresses of the target devices on multiple single boards are different. Based on this, when the controller in the embodiment of the present application communicates with the target devices on multiple single boards, it can identify the target device and prevent the addresses of the target devices on the multiple single boards connected to the controller from conflicting.

[0006] In a possible implementation, each target device has an address configuration circuit, the address configuration circuit has multiple signal input terminals; the level combination sequence of the multiple signal input terminals determines the address of the corresponding target device; the logic device has a signal configuration terminal, the signal configuration terminal is used to control the level of the signal input terminal of at least one target device, so that the level combination sequence of the signal input terminals of each target device is different. The levels of the signal input terminals of the target devices of multiple boards are controlled by the logic device, so that the level combination sequence of each target device is different, thereby making the address of each target device different.

[0007] In a possible implementation manner, the target device is any one of a fan, a sensor, or a memory.

[0008] In a possible implementation manner, the target device is a device of the same type.

[0009] In one possible implementation, the target device is an I2C device, and the controller is connected to the I2C devices on multiple boards via an I2C bus.

[0010] In a possible implementation, the address configuration circuit also includes multiple resistors; the first end of the resistor is connected to the power supply, and the second end of a resistor is correspondingly connected to a signal input end; or the first end of the resistor is grounded, and the second end of a resistor is correspondingly connected to a signal input end; wherein the signal configuration end of the logic device is electrically connected to the second end of the resistor in the address configuration circuit of at least one target device, and the signal configuration end is used to output a level signal to the second end of the resistor, so that the level combination sequence of multiple signal input ends of target devices on multiple boards is different. Through simple resistor pull-up or pull-down in conjunction with the logic device to configure the level of the signal input end, the address conflicts of target devices on multiple boards are prevented, and the circuit structure of the address configuration circuit is simple, which can reduce the circuit complexity and reduce the cost.

[0011] In a possible implementation, the number of target devices on multiple boards is N, each target device is provided with M signal input terminals, and the number of multiple resistors in each address configuration circuit is M; wherein the signal configuration terminal of the logic device is electrically connected to the second terminal of a resistor in the address configuration circuit of N-1 target devices, respectively, and the address configuration circuit of the remaining target devices is not connected to the logic device; wherein the logic device is used to configure the level signal of the signal configuration terminal to be all the same, so that the level combination sequence of the M signal input terminals of each target device is different. Since the logic device configures the signal configuration terminal to be all the same, the same signal configuration terminal can be used to connect the second terminal of a resistor in the address configuration circuit of each target device, thereby reducing the signal configuration terminal of the logic device required for address configuration and saving port resources of the logic device.

[0012] In a possible implementation, several signal configuration terminals of the logic device are electrically connected to the second terminal of each resistor in the address configuration circuit of each target device respectively; wherein the logic device is used to configure the level signals of the several signal configuration terminals so that the level combinations of the signal input terminals of each target device are different. In this way, the level combinations of the signal input terminals of each target device can be flexibly configured, the number of boards that can be configured by the logic device is increased, and the expansion of the target devices connected to the same controller is easily realized.

[0013] In one possible implementation, the controller is used to generate a write instruction according to the connection information between the resistor in the address configuration circuit of each target device and the logic device; the logic device is used to configure the level signal output by the signal configuration terminal connected to the resistor according to the write instruction. The logic device performs address configuration according to the write instruction of the controller, and can realize dynamic configuration of the address of the connected target device.

[0014] In one possible implementation, the address configuration circuit also includes multiple resistors and multiple control switches; the first end of the resistor is connected to the power supply, and the second end of a resistor is correspondingly connected to a signal input terminal; the first end of a control switch is correspondingly connected to the second end of a resistor, the second end of the control switch is grounded, the control end of at least one control switch is connected to the signal configuration terminal, and the control switch is used to turn on or off according to the level signal to change the level of the corresponding signal input terminal; or the first end of the resistor is grounded, and the second end of a resistor is correspondingly connected to a signal input terminal; the first end of a control switch is correspondingly connected to the second end of a resistor, the second end of the control switch is connected to the power supply, the control end of at least one control switch is connected to the signal configuration terminal, and the control switch is used to turn on or off according to the level signal to change the level of the corresponding signal input terminal.

[0015] In one possible implementation, the controller is connected to the logic device; the controller is used to generate a write instruction based on the connection information between the control switch and the logic device in the address configuration circuit of each target device; the logic device is used to configure the level signal output by the signal configuration terminal connected to the control switch according to the write instruction.

[0016] In a possible implementation, the computing device further includes a management board, and the logic device and the controller are disposed on the management board.

[0017] In a possible implementation, the single board is a CXL single board, at least one memory bar is arranged on the CXL single board, and a memory bar on the CXL single board is correspondingly arranged with a target device.

[0018] In a possible implementation, the controller includes a baseboard management controller, the logic device includes a complex programmable logic device, and the baseboard management controller is connected to the complex programmable logic device through an IO bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A first schematic diagram of a computing device provided in an embodiment of the present application.

[0020] Figure 2 A second schematic diagram of a computing device provided in an embodiment of the present application.

[0021] Figure 3 A third schematic diagram of a computing device provided in an embodiment of the present application.

[0022] Figure 4 A fourth schematic diagram of a computing device provided in an embodiment of the present application.

[0023] Figure 5 A fifth schematic diagram of a computing device provided in an embodiment of the present application.

[0024] Figure 6 A sixth schematic diagram of a computing device provided in an embodiment of the present application.

[0025] Figure 7 A schematic diagram of a server provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0026] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0027] It should be noted that in this application, "at least one" means one or more, and "more than one" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0028] In order to better understand the present application, various professional terms involved in the present application are first introduced.

[0029] A single board refers to an integrated circuit board widely used in the field of embedded computers. It is usually a circuit board with certain functions composed of chips, components, circuit boards, etc.

[0030] CXL (Compute Express Link, CXL) board refers to a memory expansion board. A CXL memory board can include a control chip and several memory bars. CXL boards can expand memory bandwidth and capacity based on the memory expansion mode, provide additional memory space for the server, and increase the storage density of the server.

[0031] The Inter-Integrated Circuit (I2C) bus is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). It is mainly used for short-distance communication between low-speed microcontrollers and peripheral devices.

[0032] An I2C device refers to a device with an I2C interface or a device that communicates with other devices based on the I2C protocol.

[0033] Baseboard Management Controller (BMC) is an embedded system control chip, usually integrated into computer systems such as servers and network devices, used to monitor, control, manage and maintain the hardware and software of the entire system. BMC usually includes multiple components such as processor, memory, network interface, clock, I / O interface, and runs an independent operating system. By cooperating with the main processor and other system components, BMC can achieve functions such as diagnosis, performance monitoring, firmware update, power management, and security management. BMC can also access and control the system physically and virtually, allowing administrators to remotely manage and control the system, thereby improving system reliability, availability, and maintainability.

[0034] Complex Programmable Logic Device (CPLD) can be reprogrammed to perform specific digital circuit functions, including calculation, control, scheduling and timing. CPLD is usually composed of programmable logic unit (PLU), programmable input / output (I / O) control circuit and programmable interconnect array (PIA). Among them, the programmable logic unit PLU is composed of several programmable logic macro cells (LMC). LMC mainly includes circuits such as AND array, OR array, NOT array, register, programmable trigger and multiplexer, which can be independently configured as timing or combination working mode. The AND or OR array in LMC is used to realize logical operation, and the programmable trigger is used to store status information. The programmable I / O control circuit is used to control the communication between CPLD and external devices, including input and output control and signal conversion. The programmable internal connection PIA is used to connect the circuits inside CPLD to realize data transmission and control signal transmission between different circuits. Different logic functions can be realized by changing the internal connection mode.

[0035] General Purpose Input / Output (GPIO) is one of the commonly used interface types in CPLD. It is often used to connect external devices to achieve data exchange and communication between CPLD and the external environment. GPIO has two basic functions: input and output. When GPIO is configured as input, it can read electrical signals from external devices, convert these signals into digital signals, and then pass them to the logic unit of CPLD for processing. When GPIO is configured as output, it can provide digital signals to external devices.

[0036] Field-Programmable Gate Array (FPGA) is a semi-customized circuit in application-specific integrated circuits. It is a programmable logic array that can effectively solve the problem of the small number of gate circuits in the original device. The basic structure of FPGA includes input and output units (IOB), configurable logic blocks (CLB) and internal connections (interconnect). FPGA uses a small lookup table (16×1 RAM) to implement combinational logic. Each lookup table is connected to the input of a D flip-flop, which then drives other logic circuits or input and output units, thus forming a basic logic unit module that can realize both combinational logic functions and sequential logic functions. These modules are connected to each other or to input and output units using metal wires. The logic of FPGA is realized by loading programming data into the internal static storage unit. The value stored in the memory unit determines the logic function of the logic unit and the connection between the modules or between the module and the input and output unit, and ultimately determines the functions that the FPGA can realize. FPGA allows unlimited programming. Because FPGA has the characteristics of rich wiring resources, repeatable programming, high integration and low investment, it has been widely used in the field of digital circuit design.

[0037] Register: In computer hardware, a register is a very fast, small storage element. In this case, it refers to the register inside the CPLD / FPGA, which is used to store and control the state of the IO pin.

[0038] The embodiment of the present application provides a computing device, which includes a logic device, a controller, and multiple boards. The logic device is connected to at least one board, the controller is connected to the multiple boards respectively, and the controller is connected to the logic device. The logic device is used to configure the address of the target device on at least one board, and the addresses of the target devices on the multiple boards are different. The controller communicates with the target devices on the corresponding boards based on different addresses.

[0039] In the embodiment of the present application, the address of the target device on at least one single board is configured by a logic device, so that the addresses of the target devices on multiple single boards are different. Based on this, when the controller in the embodiment of the present application communicates with the target devices on multiple single boards, it can identify the target device and prevent the address of the target devices on the multiple single boards connected to the controller from conflicting. Moreover, the computing device in the embodiment of the present application can prevent the address of the target devices on multiple single boards from conflicting without adding additional hardware, which can reduce the hardware cost and system complexity of the computing device.

[0040] In some embodiments, the target device may be a fan, a sensor, a memory, and other devices. Specifically, the fan may be a cooling fan in a computing device, the sensor may be a temperature sensor, a humidity sensor, a pressure sensor, a vibration sensor, and the like in the computing device, and the memory may be an EEPROM memory, and the like in the computing device. Of course, the target device may also be other devices in the computing device, and the embodiments of the present application are not limited thereto.

[0041] In some embodiments, the target device may be a device of the same type, wherein the device of the same type refers to a device having the same position, connection relationship and function on each board.

[0042] For example, the target devices on the multiple boards may be cooling fans on each board, or sensors on each board, or memories on each board, and so on.

[0043] In some embodiments, the target device is an I2C device, and the controller can communicate with the I2C devices on multiple boards through an I2C bus.

[0044] Of course, the target device of the embodiment of the present application is not limited to an I2C device, but may also be other devices that can communicate with a controller.

[0045] See also Figure 1 , Figure 1 A computing device 100 provided by an embodiment of the present application is shown, wherein the target device on multiple boards 130 in the computing device 100 is an I2C device 131 .

[0046] like Figure 1 As shown, the computing device 100 includes a management board 110 and at least two single boards 130. Each single board 130 is provided with at least one I2C device 131.

[0047] Each I2C device 131 has an address configuration circuit 132 , and the address configuration circuit 132 has a plurality of signal input terminals. The I2C device 131 determines its address according to the level combination sequence of the plurality of signal input terminals.

[0048] The management board 110 includes a logic device 112 and a controller 111. The logic device 112 has a signal configuration terminal. The signal configuration terminal is used to control the level of the signal input terminal of at least one I2C device 131 so that the level combination sequence of the signal input terminal of each I2C device 131 is different.

[0049] It can be understood that the logic device 112 can make the level combination sequence of multiple signal input terminals of each I2C device 131 different by configuring the level signal output by the signal configuration terminal. The level signal is used to instruct the corresponding address configuration circuit 132 to adjust the level of the corresponding signal input terminal according to the level signal, thereby making the level combination sequence of the signal input terminal of each I2C device 131 different.

[0050] It should be noted that in computing devices, there are situations where the baseboard management controller BMC connects to I2C devices on multiple boards through the same I2C bus, and the I2C devices and the baseboard management controller BMC exchange information through the I2C bus. Therefore, there is a scenario where multiple I2C devices are mounted on an I2C bus. Usually, the I2C device is connected to the address configuration circuit on the board through the address line, and the address configuration circuit controls the level of the address line (for example, pull the address line to "high level 1", or pull it down to low level 1) to configure the address of the I2C device. The device address of the I2C device will adopt the user semi-defined mode. The I2C device has already solidified the upper four-bit device address internally when the manufacturer designs it, and the remaining three-bit address is connected to the address configuration circuit through three address lines, which is defined by the circuit structure of the address configuration circuit of the I2C device.

[0051] In the embodiment of the present application, if the circuit structure of the single boards is exactly the same, the circuit structure of the address configuration circuit of the I2C device on each single board is the same, so that the address configured by the address configuration circuit of the I2C device is the same. When the baseboard management controller BMC connects multiple I2C devices on exactly the same single boards through the same I2C bus, the baseboard management controller BMC cannot identify and distinguish the I2C devices, which will cause address conflicts among multiple I2C devices connected to the same I2C bus.

[0052] The controller 111 is connected to the I2C devices 131 on at least two boards 130 through the I2C bus 120. The controller 111 communicates with the I2C devices 131 on the corresponding boards 130 based on different addresses. It can be understood that when the controller 111 communicates with the I2C devices 131 on the boards 130 through the I2C bus 120, the signal transmitted by the I2C bus 120 carries the address of the corresponding I2C device 131.

[0053] It can be understood that when the device address is fixed inside the I2C device 131, the address of the I2C device 131 is determined according to the device address and the level combination sequence of the signal input terminal. At this time, the logic device 112 controls the level combination sequence of multiple signal input terminals to be different, so that the addresses of the I2C devices 131 are different, and the controller 111 can identify and distinguish the I2C devices 131.

[0054] In the embodiment of the present application, the level of the signal input terminal of at least one I2C device 131 is controlled by the signal configuration terminal of the logic device 112, so that the level combination order of the multiple signal input terminals of each I2C device 131 is different, thereby making the addresses of the I2C devices 131 on each single board 130 different. Based on this, when the controller 111 in the embodiment of the present application communicates with the I2C device 131 on the single board 130, it can identify and distinguish the I2C device 131, thereby preventing the address of the multiple I2C devices 131 connected to the controller 111 through the I2C bus 120 from conflicting. Moreover, the computing device 100 in the embodiment of the present application can prevent the address of multiple I2C devices 131 from conflicting without adding additional hardware, which can reduce the hardware cost and system complexity of the computing device 100.

[0055] In some embodiments, the management board 110 may be provided with a plurality of connectors, and the single board 130 may be connected to the management board 110 through the connector, and then the I2C device on the single board 130 is also connected to the controller 111 on the management board 110 through the connector. Alternatively, the management board 110 may be connected to each single board 130 through a plurality of cables.

[0056] In the embodiment of the present application, the computing device 100 may be an electronic device that can perform data read and write operations. For example, the computing device 100 may be a server, a desktop computer, a laptop computer, a tablet computer, an artificial intelligence device, etc. The server may be, for example, a graphics processing unit (GPU) server or an AI server, etc.

[0057] In the embodiment of the present application, the controller 111 may be any one of BMC, IPMI, SOC and BIOS, wherein BMC is as described above and will not be described in detail here.

[0058] Intelligent Platform Management Interface (IPMI): is a standardized interface specification for remote access and control of computer system hardware management and monitoring functions. IPMI is usually supported by the BMC chip on the server motherboard and interacts with controllers such as CPLD to achieve remote management and control of the server system.

[0059] System-On-Chip (SOC): is a design that integrates the processor core, memory, network, storage and other peripheral devices on a single chip. SOC chips usually have the characteristics of low power consumption, high performance and reconfigurability, and can be used for control circuit design on server motherboards.

[0060] Basic Input / Output System (BIOS): A program embedded in the motherboard of a computer system, mainly used to initialize hardware devices, load the operating system, provide basic input / output support, etc. BIOS and CPLD usually communicate using protocols such as SPI or I2C.

[0061] Exemplarily, the controller 111 in the embodiment of the present application is a baseboard management controller BMC.

[0062] The logic device 112 may be any one of a CPLD, an FPGA, an application-specific integrated circuit (ASIC) and a microcontroller unit (MCU). For example, the logic device 112 in the embodiment of the present application is a CPLD.

[0063] In addition, the types of boards in the embodiments of the present application may be the following: Storage board: A storage board is a single-board hardware that integrates the storage controller, storage media, and other peripheral circuits to achieve higher storage density and faster storage access speed. It is usually used in data centers and cloud computing environments to meet the needs of high-efficiency storage.

[0064] Network board: A network board is a single-board hardware that integrates network-related components such as network processors, network cards, and switch chips on a single board. It is mainly used to provide network connection and data transmission functions, and can achieve high-speed, efficient, and reliable network communication services.

[0065] Graphics card board: A graphics card board is a single-board hardware that integrates the graphics card core, video memory, and related circuits. It is often used for graphics rendering and computing-intensive tasks, providing high performance and high-quality graphics output for server applications.

[0066] In addition to the types listed above, there are many other types of single boards. The design and application of each single board has its specific functions. The embodiment of the present application does not limit the type of single board 130. Different single board types can be combined together to achieve more complex server system configurations and application scenarios. Designers can make specific choices based on design and application purposes and requirements.

[0067] Specifically, the single board 130 in the embodiment of the present application may be a CXL single board. At least one memory bar is provided on the CXL single board, and one I2C device 131 is provided corresponding to one memory bar on the CXL single board. For example, if three memory bars are provided on a CXL single board, three I2C devices 131 are provided correspondingly on the CXL single board, and the I2C device 131 is used to store information such as the capacity, temperature or power consumption of the corresponding memory bar. The controller 111 may obtain information such as the capacity, temperature or power consumption of the corresponding memory bar from the I2C device 131 through the I2C bus.

[0068] It is understood that the memory stick can be pluggable on the CXL board. The I2C device 131 can be integrated on the board 130 or can be set on the memory stick. The I2C device 131 can be a memory, a sensor, etc. Exemplarily, the I2C device 131 can be an electrically erasable programmable read-only memory (EEPROM), a temperature sensor, etc.

[0069] In some specific examples, the signal configuration end of the logic device 112 can control the same or different level combination order of multiple signal input ends of each I2C device 131 on the same CXL board. For example, when the signal configuration end of the logic device 112 controls the same level combination order of multiple signal input ends of each I2C device 131 on the same CXL board, the device addresses fixed inside each I2C device 131 on the same CXL board are different, thereby making the addresses of each I2C device 131 on the same CXL board different. When the signal configuration end of the logic device 112 controls the same CXL board with different level combination orders of multiple signal input ends of each I2C device 131, the device addresses fixed inside each I2C device 131 on the same CXL board can be the same or different.

[0070] It can be understood that the signal configuration end of the logic device 112 needs to control the level combination order of multiple signal input ends of the corresponding I2C devices 131 on different CXL boards differently. For example, the computing device 100 includes a first CXL board and a second CXL board, and the first CXL board is provided with a first memory bar and a second memory bar, and a first I2C device corresponding to the first memory bar, and a second I2C device corresponding to the second memory bar. The second CXL board is provided with a third memory bar and a third memory bar, and a third I2C device corresponding to the third memory bar, and a fourth I2C device corresponding to the fourth memory bar. Among them, the first memory bar is the same as the third memory bar, the first I2C device is the same as the third I2C device, the second memory bar is the same as the fourth memory bar, and the second I2C device is the same as the fourth I2C device. Then the signal configuration end of the logic device 112 needs to at least control the level combination sequence of the multiple signal input ends corresponding to the first I2C device to be different from the level combination sequence of the multiple signal input ends corresponding to the third I2C device, and the level combination sequence of the multiple signal input ends corresponding to the second I2C device to be different from the level combination sequence of the multiple signal input ends corresponding to the fourth I2C device, so that the address of the first I2C device is different from the address of the third I2C device, and the address of the second I2C device is different from the address of the fourth I2C device.

[0071] In some embodiments, the logic device 112 may control the level combination sequence of multiple signal input terminals of the I2C device 131 on the single board 130 according to the received external command.

[0072] Among them, the external instruction can be sent from the controller 111 to the logic device 112. For example, the controller 111 can generate a write instruction based on the connection information between the multiple signal input terminals of the I2C device 131 on each single board 130 and the logic device 112, and send the write instruction to the logic device 112. The logic device 112 is also used to receive the write instruction, and the logic device 112 controls the level combination sequence of the multiple signal input terminals of the I2C device 131 according to the write instruction. The controller 111 can send a write instruction to the logic device 112 every time it is powered on or in a preset cycle to realize dynamic configuration of the level combination sequence of the multiple signal input terminals of the I2C device 131. Of course, in the present application, the logic device 112 can also set the level of each signal configuration terminal according to the connection relationship between the logic device 112 and the multiple signal input terminals of each I2C device 131 during design, so that the level combination sequence of the multiple signal input terminals of each I2C device 131 is different.

[0073] It can be understood that the connection information between the multiple signal input terminals of each I2C device 131 and the logic device 112 can be pre-stored in the controller 111 .

[0074] In a specific example, the logic device 112 is a complex programmable logic device CPLD, and the controller 111 is a baseboard management controller BMC. The CPLD and the BMC can be connected via an IO bus, and the signal configuration end of the CPLD is a GPIO pin, which can be connected to at least one signal input end of an I2C device 131 on at least one single board 130. The BMC can read and write the value of the internal register of the CPLD through the IO bus. When the BMC sends a write instruction to the CPLD through the IO bus, the CPLD modifies the value of its internal register according to the write instruction, thereby changing the level signal of the GPIO pin connected to the signal input end, realizing the level configuration of the signal input end of the I2C device 131 on the single board 130, and thereby making the level combination sequence of the multiple signal input ends of each I2C device 131 different.

[0075] It can be understood that the write instruction is generated by the BMC according to the connection information between the CPLD and the signal input terminal. Therefore, the CPLD can modify the value corresponding to the GPIO pin in its internal register according to the write instruction, and this value controls the level of the GPIO pin. The value of the internal register of the CPLD is generally binary coded or hexadecimal coded, and the values ​​of different digits of binary or hexadecimal coding can be used to represent the levels of each GPIO pin of the CPLD. For example, if the value of the digit corresponding to a GPIO pin is "1", then the GPIO pin is at a high level. Otherwise, the GPIO pin is at a low level.

[0076] The specific embodiment of the computing device 100 of the present application is described in detail below with reference to the accompanying drawings.

[0077] Embodiment 1: The computing device 100 includes two boards 130. The address configuration circuit 132 includes two signal input terminals and two resistors, one resistor is connected to each signal input terminal. A signal configuration terminal of the logic device 112 is connected to a resistor of an I2C device 131 on one of the boards 130 and a connection node of the corresponding signal input terminal.

[0078] like Figure 2 As shown, the two boards 130 are respectively a first board 130a and a second board 130b, the two signal input terminals are respectively a first signal input terminal P1 and a second signal input terminal P2, and the two resistors are respectively a first resistor R1 and a second resistor R2.

[0079] The circuit structures of the address configuration circuit 132 of the I2C device 131 on the first single board 130a and the second single board 130b are the same, that is, the first ends of the first resistor R1 and the second resistor R2 are connected to the power supply VCC, the second end of the first resistor R1 is connected to the first signal input terminal P1 of the I2C device 131, and the second end of the second resistor R2 is connected to the second signal input terminal P2 of the I2C device 131. A signal configuration terminal of the logic device 112 is connected to the second end of the first resistor R1 on the first single board 130a (that is, the first signal input terminal P1 of the I2C device 131), and the second ends of the first resistor R1 and the second resistor R2 on the second single board 130b are not electrically connected to the signal configuration terminal of the logic device 112. If the logic device 112 is not connected to the signal input terminals (P1, P2) of the I2C device 131, the signal input terminals (P1, P2) of the I2C devices 131 on the two boards (130a, 130b) are pulled up by the resistors (R1, R2) and are both "high level 1", so that the level combination sequence of the signal input terminals (P1, P2) of the I2C devices 131 on the two boards (130a, 130b) is both (1, 1), that is, the level combination sequence of the I2C devices 131 on the two boards (130a, 130b) is the same, and the addresses of the I2C devices 131 on the two boards (130a, 130b) are the same.

[0080] The logic device 112 configures the level signal outputted by the signal configuration end connected to the first signal input end P1 of the I2C device 131 of the first single board 130a to "low level 0", so that the level combination sequence of the first signal input end P1 and the second signal input end P2 of the I2C device 131 of the first single board 130a is (0, 1). The level combination sequence of the first signal input end P1 and the second signal input end P2 of the second single board 130b is still (1, 1). As a result, the level combination sequence of the signal input ends (P1, P2) of the I2C devices 131 on the two single boards (130a, 130b) is different, and thus the addresses of the I2C devices 131 on the two single boards (130a, 130b) are different.

[0081] Of course, in the embodiment of the present application, the address configuration circuit 132 can also be configured as follows: the first end of the first resistor R1 and the second resistor R2 are grounded GND, the second end of the first resistor R1 is connected to the first signal input terminal P1 of the I2C device 131, and the second end of the second resistor R2 is connected to the second signal input terminal P2 of the I2C device 131. At this time, the logic device 112 configures the level signal output by the signal configuration end of the first signal input terminal P1 of the I2C device 131 of the first single board 130a to "high level 1", so that the level combination sequence of the first signal input terminal P1 and the second signal input terminal P2 of the I2C device 131 on the first single board 130a is (1, 0). The level combination sequence of the first signal input terminal P1 and the second signal input terminal P2 of the second single board 130b is (0, 0).

[0082] Of course, the logic device 112 can also be provided with two signal configuration terminals, and the two signal configuration terminals are respectively connected to the two signal input terminals of the I2C device 131 on the first single board 130a or the two signal input terminals of the I2C device 131 on the second single board 130b. At this time, the logic device 112 can configure the level signals output by the two signal configuration terminals as "high level 1" and "low level 0" respectively, or configure the level signals output by the two signal configuration terminals as "high level 1", or configure the level signals output by the two signal configuration terminals as "low level 0". The embodiment of the present application does not limit how the logic device 112 specifically configures the level signal output by the signal configuration terminal, as long as the level combination order of the multiple signal input terminals of each I2C device 131 can be controlled to be different.

[0083] In some specific examples, the logic device 112 may be provided with two signal configuration terminals (not shown), one of which may be connected to a signal input terminal of the I2C device 131 on the first board 130a, and the other may be connected to a signal input terminal of the I2C device 131 on the second board. For example, one signal configuration terminal is connected to the first signal input terminal P1 of the I2C device 131 on the first board 130a, and the other signal configuration terminal is connected to the first signal input terminal P1 of the I2C device 131 on the second board. The logic device 112 may configure the level signals output by the two signal configuration terminals to "high level 1" and "low level 0" respectively. Of course, one signal configuration terminal may be connected to the first signal input terminal P1 of the I2C device 131 on the first board 130a, and the other signal configuration terminal may be connected to the second signal input terminal P2 of the I2C device 131 on the second board, or vice versa.

[0084] In the embodiment of the present application, the controller 111 can generate a write instruction based on the connection information between the resistor and the logic device in the address configuration circuit 132 of each I2C device 131, and then the logic device 112 configures the level signal output by the signal configuration terminal connected to the resistor according to the write instruction.

[0085] Embodiment 2: The address configuration circuit 132 includes three signal input terminals and three resistors, and the three resistors are respectively connected to the three signal input terminals of the I2C device 131. The computing device 100 includes four boards 130, and the three signal configuration terminals of the logic device 112 are respectively connected to the connection nodes of the three resistors and the three signal input terminals.

[0086] like Figure 3 As shown, the four single boards 130 are respectively a first single board 130a, a second single board 130b, a third single board 130c and a fourth single board 130d, the three signal input terminals are respectively a first signal input terminal P1, a second signal input terminal P2 and a third signal input terminal P3, the three resistors are respectively a first resistor R1, a second resistor R2 and a third resistor R3, and the three signal configuration terminals are respectively a first configuration terminal G1, a second configuration terminal G2 and a third configuration terminal G3.

[0087] The first ends of the first resistor R1, the second resistor R2 and the third resistor R3 are all connected to the power supply VCC, the second end of the first resistor R1 is connected to the first signal input terminal P1 of the I2C device 131, the second end of the second resistor R2 is connected to the second signal input terminal P2 of the I2C device 131, and the second end of the third resistor R3 is connected to the third signal input terminal P3 of the I2C device 131. If the signal configuration end of the logic device 112 is not connected to the connection node between the resistor and the signal input end, the level combination sequence of the three signal input ends of the I2C device 131 on the four boards (130a, 130b, 130c and 130d) is "111", and the level combination sequence of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) is the same.

[0088] In this embodiment, the second end of the first resistor R1 on the first board 130a (that is, the first signal input terminal P1 of the I2C device 131 on the first board 130a) is electrically connected to the first configuration terminal G1 of the logic device 112. The second end of the second resistor R2 on the second board 130b (that is, the second signal input terminal P2 of the I2C device 131 on the second board 130b) is electrically connected to the second configuration terminal G2 of the logic device 112. The second end of the third resistor R3 on the third board 130c (that is, the third signal input terminal P3 of the I2C device 131 on the third board 130c) is electrically connected to the third configuration terminal G3 of the logic device 112. The first resistor R1, the second resistor R2, and the third resistor R3 on the fourth board 130d are not electrically connected to the signal configuration terminal of the logic device 112.

[0089] The logic device 112 configures the level signals outputted by the first configuration terminal G1, the second configuration terminal G2 and the third configuration terminal G3 to be "low level 0". As a result, the level combination sequence of the three signal input terminals of the I2C device 131 on the first single board 130a is "011", the level combination sequence of the three signal input terminals of the I2C device 131 on the second single board 130b is "101", the level combination sequence of the three signal input terminals of the I2C device 131 on the third single board 130c is "110", and the level combination sequence of the three signal input terminals of the I2C device 131 on the fourth single board 130d is "111", thereby making the level combination sequence of the I2C devices 131 on the four single boards (130a, 130b, 130c and 130d) different.

[0090] Similar to the first embodiment, the address configuration circuit 132 can also be configured as follows: the first ends of the first resistor R1, the second resistor R2, and the third resistor R3 are all grounded GND. At this time, the logic device 112 configures the level signals output by the first configuration terminal G1, the second configuration terminal G2, and the third configuration terminal G3 to be "high level 1".

[0091] Of course, since the logic device 112 configures the level signals output by the first configuration terminal G1, the second configuration terminal G2 and the third configuration terminal G3 to be the same level signals, the logic device 112 can also be connected to the three signal input terminals of the three I2C devices 131 at the same time by only one signal configuration terminal, so that the logic device 112 needs to occupy fewer ports for address configuration of the I2C device 131, which can save the port resources of the logic device 112.

[0092] In this embodiment, the logic device 112 configures the level signal of the signal configuration terminal connected to the signal input terminal to be the same signal, and the I2C device 131 on each single board 130 has only one signal input terminal connected to the signal configuration terminal, and the order of the signal input terminals connected to the signal configuration terminals is different, so as to achieve different level combination sequences of the signal input terminals of each I2C device 131. It can be understood that in this embodiment, since the address configuration circuit 132 of the I2C device 131 is only provided with three signal input terminals, the logic device 112 can support address configuration for four single boards 130 at most.

[0093] However, the number of the single boards 130 of the computing device 100 of the present application is not limited to two or four, and can also be set to three, five, seven, etc. The number of signal input terminals set in the address configuration circuit 132 of the I2C device 131 of the embodiment of the present application is also not limited to one or three, and can also be set to two, four, seven, etc. The logic device 112 can be connected to the signal input terminal according to the circuit structure of the address configuration circuit 132 in actual application, the number of single boards, and the number of signal input terminals. Specifically, the number of I2C devices 131 set in each single board 130 of the computing device 100 is N, N is a positive integer greater than or equal to 2, the I2C device 131 is provided with M signal input terminals, and the number of resistors in each address configuration circuit 132 is also M, M is a positive integer greater than or equal to 2. The signal configuration terminal of the logic device 112 is electrically connected to the second end of a resistor in the address configuration circuit 132 on N-1 single boards 130, and the address configuration circuit 132 of the remaining single board 130 is not connected to the logic device 112. At this time, the logic device 112 can be used to configure the level signals of the signal configuration terminals connected to the resistors to be all the same. (For specific examples, please refer to the aforementioned embodiment 2) Embodiment three: The address configuration circuit 132 includes three signal input terminals and three resistors, and the three resistors are respectively connected to the three signal input terminals of the I2C device 131. The computing device 100 includes four boards 130, and several signal configuration terminals of the logic device 112 are respectively connected to the connection nodes of each resistor and each signal input terminal.

[0094] like Figure 4 As shown, the four single boards 130 are respectively a first single board 130a, a second single board 130b, a third single board 130c and a fourth single board 130d, the three signal input terminals are respectively a first signal input terminal P1, a second signal input terminal P2 and a third signal input terminal P3, and the three resistors are respectively a first resistor R1, a second resistor R2 and a third resistor R3.

[0095] The connection relationship between the resistor and the signal input terminal in this embodiment is the same as that in the second embodiment, and will not be repeated here.

[0096] The second ends of the resistors corresponding to the signal input ends of the I2C devices 131 on the four boards ( 130 a , 130 b , 130 c and 130 d ) are electrically connected to a number of signal configuration ends of the logic device 112 in a one-to-one correspondence.

[0097] Specifically, the logic device 112 configures the level signals outputted by the three signal configuration terminals connected to the second ends of the first resistor R1, the second resistor R2 and the third resistor R3 of the I2C device 131 on the first board 130a (i.e., the first signal input terminal P1, the second signal input terminal P2 and the third signal input terminal P3 of the I2C device 131 on the first board 130a) to be "low level 0". As a result, the level combination sequence of the signal input terminals of the I2C device 131 on the first board 130a is "000".

[0098] The logic device 112 configures the level signals outputted from the two signal configuration terminals connected to the second ends of the first resistor R1 and the second resistor R2 on the second board 130b (i.e., the first signal input terminal P1 and the second signal input terminal P2 of the I2C device 131 on the second board 130b) to "low level 0", and configures the level signal outputted from the signal configuration terminal connected to the second end of the third resistor R3 on the second board 130b (i.e., the third signal input terminal P3 of the I2C device 131 on the second board 130b) to "high level 1". Thus, the level combination sequence of the signal input terminals of the I2C device 131 on the second board 130b is "001".

[0099] The logic device 112 configures the level signals outputted from the two signal configuration terminals connected to the second ends of the first resistor R1 and the third resistor R3 on the third board 130c (i.e., the first signal input terminal P1 and the third signal input terminal P3 of the I2C device 131 on the third board 130c) to "low level 0", and configures the level signal outputted from the signal configuration terminal connected to the second end of the second resistor R2 on the second board 130b (i.e., the second signal input terminal P2 of the I2C device 131 on the second board 130b) to "high level 1". Thus, the level combination sequence of the signal input terminal of the I2C device 131 on the second board 130b is "010".

[0100] The logic device 112 configures the level signals outputted from the two signal configuration terminals connected to the second ends of the first resistor R1 and the second resistor R2 on the fourth board 130d (i.e., the first signal input terminal P1 and the second signal input terminal P2 of the I2C device 131 on the fourth board 130d) to "high level 1", and configures the level signal outputted from the signal configuration terminal connected to the second end of the third resistor R3 on the fourth board 130d (i.e., the third signal input terminal P3 of the I2C device 131 on the fourth board 130d) to "low level 0". Thus, the level combination sequence of the signal input terminals of the I2C device 131 on the fourth board 130d is "110".

[0101] In this example, the level combination sequences of the signal input terminals of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) are respectively "000", "001", "010" and "110", so that the addresses of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) are different.

[0102] Similar to the first and second embodiments, the address configuration circuit 132 may also be configured such that the first ends of the first resistor R1 , the second resistor R2 , and the third resistor R3 are all grounded GND.

[0103] It can be understood that when the three signal input terminals of the I2C devices 131 on the multiple boards 130 are electrically connected to the signal configuration terminals of the logic device 112 in a one-to-one correspondence, the logic device 112 can be implemented as the I2C devices 131 on eight boards 130 at most for address configuration. When the logic device 112 performs address configuration for the I2C devices 131 on the eight boards 130, the level combination sequence of the signal input terminals of the I2C devices 131 on each board 130 is "000", "001", "010", "011", "100", "101", "110" and "111" respectively. Among them, only the signal input terminals of the I2C devices 131 on seven boards 130 can be connected to the signal configuration terminals of the logic device 112, and the signal input terminal of the I2C device 131 on the remaining board 130 is not connected to the signal configuration terminal of the logic device 112, or the signal input terminals of the I2C devices 131 on the eight boards 130 can all be connected to the signal configuration terminals of the logic device 112.

[0104] Of course, in this embodiment, the number of the boards 130 in the computing device 100 is not limited to four or eight, and can be set according to actual needs, for example, can be set to two, five, and so on.

[0105] In the present application, the connection method between the signal configuration terminal of the logic device 112 and the signal input terminal of the I2C device 131 on each single board 130 is not as follows: Figures 1 to 3 The embodiments shown are limited to the above, and can be set according to actual applications. For example, it can also be set as follows: the I2C devices 131 on some boards 130 have only one signal input terminal connected to the signal configuration terminal of the logic device 112, the I2C devices 131 on some boards 130 have two signal input terminals connected to the signal configuration terminal of the logic device 112, and the I2C devices 131 on the remaining boards 130 have three signal input terminals connected to the signal configuration terminal of the logic device 112.

[0106] It is understandable that the I2C device 131 in the present application is not limited to setting two or three signal input terminals, and the number can be determined according to the signal input terminals designed for the actual I2C device 131, for example, it can also be set to five signal input terminals, seven signal input terminals, etc. Correspondingly, the address configuration circuit 132 can also set the number of resistors according to the number of signal input terminals.

[0107] Embodiment 4: The computing device 100 includes two boards 130, and the address configuration circuit 132 includes two signal input terminals, two resistors and two control switches, one resistor is connected to each signal input terminal. A signal configuration terminal of the logic device 112 is connected to the control terminal of the control switch of the I2C device 131 on one of the boards 130.

[0108] like Figure 5 As shown, the two boards 130 are respectively the first board 130a and the second board 130b, the two signal input terminals are respectively the first signal input terminal P1 and the second signal input terminal P2, the two resistors are respectively the first resistor R1 and the second resistor R2, and the two control switches are respectively the first switch Q1 and the second switch Q2.

[0109] The circuit structures of the address configuration circuit 132 of the I2C device 131 on the first single board 130a and the second single board 130b are the same, that is, the first end of the first resistor R1 and the second resistor R2 are connected to the power supply VCC, the second end of the first resistor R1 is correspondingly connected to the first signal input terminal P1, the first end of the first switch Q1 is connected to the second end of the first resistor R1, and the second end of the first switch Q1 is grounded to GND. The second end of the second resistor R2 is correspondingly connected to the second signal input terminal P2, the first end of the second switch Q2 is connected to the second end of the second resistor R2, and the second end of the second switch Q2 is grounded to GND.

[0110] A signal configuration end of the logic device 112 is connected to the control end of the first switch Q1 on the first board 130a, and the control ends of the first switch Q1 and the second switch Q2 on the second board 130b are not electrically connected to the signal configuration end of the logic device 112. If the logic device 112 is not connected to the control ends of the first switch Q1 and the second switch Q2, the first switch Q1 and the second switch Q2 are disconnected by default, and the signal input ends (P1, P2) of the I2C device 131 on the two boards (130a, 130b) are pulled up by the resistors (R1, R2), and are both "high level 1", so that the level combination sequence of the signal input ends (P1, P2) of the I2C device 131 on the two boards (130a, 130b) is (1, 1), that is, the level combination sequence of the I2C devices 131 on the two boards (130a, 130b) is the same, and the addresses of the I2C devices 131 on the two boards (130a, 130b) are the same.

[0111] In this embodiment, the logic device 112 configures the level signal outputted from the signal configuration end of the control end of the first switch Q1 corresponding to the I2C device 131 of the first board 130a as the conduction signal of the first switch Q1. The first switch Q1 corresponding to the I2C device 131 on the first board 130a is turned on, and the first signal input end P1 of the I2C device 131 on the first board 130a is pulled down to "low level 0", so that the level combination sequence of the first signal input end P1 and the second signal input end P2 of the I2C device 131 of the first board 130a is (0, 1). While the first switch Q1 and the second switch Q2 corresponding to the I2C device 131 on the second board 130b remain disconnected, the level combination sequence of the first signal input end P1 and the second signal input end P2 of the I2C device 131 on the second board 130b is still (1, 1). The level combination sequence of the signal input terminals (P1, P2) of the I2C devices 131 on the two boards (130a, 130b) is different, so that the addresses of the I2C devices 131 on the two boards (130a, 130b) are different.

[0112] If the logic device 112 is not connected to the control end of the control switch (Q1, Q2), the control switch (Q1, Q2) is turned on by default. The signal input ends (P1, P2) of the I2C device 131 on the two boards (130a, 130b) are both "low level 0" by default. Then the logic device 112 can configure the level signal output by the signal configuration end connected to the control end of the first switch Q1 corresponding to the I2C device 131 on the first board 130a as a disconnection signal of the first switch Q1, so that the first switch Q1 corresponding to the I2C device 131 on the first board 130a is disconnected, and then the level of the first signal input end P1 of the I2C device 131 on the first board 130a is pulled up to "high level 1", so that the level combination sequence of the first signal input end P1 and the second signal input end P2 of the I2C device 131 of the first board 130a is (1, 0). The control switch on the second board 130b remains in the on state, and the level combination sequence of the first signal input terminal P1 and the second signal input terminal P2 of the I2C device 131 on the second board 130b is (0, 0), thereby making the level combination sequence of the I2C devices 131 on the two boards (130a, 130b) different.

[0113] It can be understood that when the logic device 112 is not connected to the control end of the control switch (Q1, Q2), the control switch (Q1, Q2) is turned on by default, and the control end of the control switch can also be connected to other control circuits. When the control switch (Q1, Q2) is turned on at a high level (for example, the control switch is an NMOS tube, an NPN transistor, etc.), the control end of the control switch (Q1, Q2) can be connected to the power supply VCC through a resistor, and the disconnection signal of the control switch is a low-level signal. When the control switch (Q1, Q2) is turned on at a low level (for example, the control switch is a PMOS tube, a PNP transistor, etc.), the control end of the control switch (Q1, Q2) can be grounded through a resistor, and the disconnection signal of the control switch (Q1, Q2) is a high-level signal. In this embodiment, the logic device 112 can determine how to configure the level signal output by the signal configuration end according to the actual connection circuit of the control end of the control switch (Q1, Q2) and the on-off performance of the control switch (Q1, Q2).

[0114] For example, the address configuration circuit 132 can also be configured as follows: the first ends of the first resistor R1 and the second resistor R2 are both grounded, the second end of the first resistor R1 is connected to the first signal input terminal P1 of the I2C device 131 and the first end of the first switch Q1, the second end of the first switch Q1 is connected to the power supply VCC, and the first switch Q1 is disconnected by default. The second end of the second resistor R2 is correspondingly connected to the second signal input terminal P2 and the first end of the second switch Q2, the second end of the second switch Q2 is connected to the power supply VCC, and the second switch Q2 is disconnected by default. The level combination sequence of the signal input ports (P1, P2) of the I2C device 131 on the first board 130a and the second board 130b is (0, 0). At this time, the logic device 112 can configure the level signal output by the signal configuration end connected to the control end of the first switch Q1 as the conduction signal of the first switch Q1, then the first switch Q1 turned on on the first single board 130a pulls up the first signal input end P1 of the I2C device 131 to "high level 1", and the level combination sequence of the signal input port (P1, P2) of the I2C device 131 on the first single board 130a is (1, 0), which is different from the level combination sequence of the signal input port (P1, P2) of the I2C device 131 of the second single board 130b.

[0115] It can be understood that the logic device 112 can be provided with two signal configuration terminals respectively connected to the control terminal of one of the control switches (Q1 or Q2) of the two single boards (130a, 130b). In this case, the logic device 112 can respectively configure the two signal configuration terminals as the on signal and the off signal of the control switch (Q1 or Q2).

[0116] In this embodiment, the control switch may include but is not limited to controllable switches such as a triode, a field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), an optocoupler, and a relay.

[0117] In the embodiment of the present application, the controller 111 can generate a write instruction based on the connection information between the control switch in the address configuration circuit 132 of each I2C device 131 and the logic device 112, and then the logic device 112 configures the level signal output by the signal configuration end connected to the control end of the control switch according to the write instruction.

[0118] Embodiment five: The computing device 100 includes four boards 130, and the I2C device 131 is provided with three signal input terminals connected to the address configuration circuit 132. The address configuration circuit 132 includes three resistors and three control switches, the three resistors are respectively connected to the three signal input terminals P, and the three signal configuration terminals of the logic device 112 are respectively connected to the control terminals of the three control switches.

[0119] like Figure 6 As shown, the four single boards 130 are respectively a first single board 130a, a second single board 130b, a third single board 130c and a fourth single board 130d, the three signal input terminals are respectively a first signal input terminal P1, a second signal input terminal P2 and a third signal input terminal P3, the three resistors R are respectively a first resistor R1, a second resistor R2 and a third resistor R3, the three control switches are respectively a first switch Q1, a second switch Q2 and a third switch Q3, and the three signal configuration terminals are respectively a first configuration terminal G1, a second configuration terminal G2 and a third configuration terminal G3.

[0120] The structures of the address configuration circuits 132 of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) are the same, namely: the first ends of the first resistor R1, the second resistor R2 and the third resistor R3 are all connected to the power supply VCC, the second end of the first resistor R1 is connected to the first signal input terminal P1 of the I2C device 131, the second end of the second resistor R2 is connected to the second signal input terminal P2 of the I2C device 131, and the second end of the third resistor R3 is connected to the third signal input terminal P3 of the I2C device 131. The first end of the first switch Q1 is connected to the second end of the first resistor R1, the second end of the second switch Q2 is connected to the second end of the second resistor R2, the second end of the third switch Q3 is connected to the second end of the third resistor R3, and the second ends of the first switch Q1, the second switch Q2 and the third switch Q3 are all grounded GND.

[0121] Among them, the control end of the first switch Q1 on the first single board 130a is electrically connected to the first configuration end G1 of the logic device 112, the control end of the second switch Q2 on the second single board 130b is electrically connected to the second configuration end G2 of the logic device 112, the control end of the third switch Q3 on the third single board 130c is electrically connected to the third configuration end G3 of the logic device 112, and the control ends of the first switch Q1, the second switch Q2 and the third switch Q3 on the fourth single board 130d are not electrically connected to the signal configuration end of the logic device 112. If the logic device 112 is not connected to the control ends of the first switch Q1, the second switch Q2 and the third switch Q3, the first switch Q1, the second switch Q2 and the third switch Q3 are disconnected by default, and the level combination sequence of the signal input ends of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) is all "111" by default, so that the addresses of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) are the same.

[0122] In this embodiment, the logic device 112 configures the level signals output by the first configuration terminal G1, the second configuration terminal G2, and the third configuration terminal G3 as turn-on signals of the first switch Q1, the second switch Q2, and the third switch Q3. The first switch Q1 on the first board 130a is turned on, and the first signal input terminal P1 of the I2C device 131 on the first board 130a is pulled down to "low level 0". The second switch Q2 on the second board 130b is turned on, and the second signal input terminal P2 of the I2C device 131 on the second board 130b is pulled down to "low level 0". The third switch Q3 on the third board 130c is turned on, and the third signal input terminal P3 of the I2C device 131 on the third board 130c is pulled down to "low level 0". Thus, the level combination sequence of the three signal input terminals of the I2C device 131 on the first board 130a is "011", the level combination sequence of the three signal input terminals of the I2C device 131 on the second board 130b is "101", the level combination sequence of the three signal input terminals of the I2C device 131 on the third board 130c is "110", and the level combination sequence of the three signal input terminals of the I2C device 131 on the fourth board 130d is "111", so that the level combination sequence of the signal input terminals of the I2C devices 131 on the four boards (130a, 130b, 130c and 130d) is different.

[0123] Similar to the fourth embodiment, the first switch Q1, the second switch Q2 and the third switch Q3 may also be turned on by default. At this time, the level combination sequence of the signal input end of the I2C device 131 on the four boards (130a, 130b, 130c and 130d) is all defaulted to "000", and the logic device 112 configures the level signal output by the signal configuration end connected to the control end of the first switch Q1, the second switch Q2 and the third switch Q3 as the disconnection signal of the first switch Q1, the second switch Q2 and the third switch Q3. Thus, the level combination sequence of the signal input end of the I2C device 131 on the first board 130a is "100", the level combination sequence of the signal input end of the I2C device 131 on the second board 130b is "010", the level combination sequence of the signal input end of the I2C device 131 on the third board 130c is "001", and the level combination sequence of the signal input end of the I2C device 131 on the fourth board 130d is "000".

[0124] It can be understood that, since the circuit structures of the address configuration circuits 132 on the four boards (130a, 130b, 130c and 130d) are the same, the specific models of the first switch Q1, the second switch Q2 and the third switch Q3 are the same, that is, the turn-on signals or turn-off signals of the first switch Q1, the second switch Q2 and the third switch Q3 on the four boards (130a, 130b, 130c and 130d) are the same, then the control ends of the first switch Q1 on the first board 130a, the second switch Q2 on the second board 130b and the third switch Q3 on the third board 130c can be connected to the same signal configuration end of the logic device 112, so that the logic device 112 needs to occupy fewer ports for address configuration of the I2C device 131, thereby saving port resources of the logic device 112.

[0125] In this embodiment, the connection relationship between the control switches on the four boards 130 and the signal configuration end of the logic device 112 is not limited to the above situation. For example, the control ends of the first switch Q1, the second switch Q2, and the third switch Q3 on the four boards 130 may be electrically connected to a plurality of signal configuration ends of the logic device 112 in a one-to-one correspondence. Among them, one signal configuration end of the logic device 112 is only electrically connected to the control end of one control switch. In this case, the logic device 112 can be implemented as an I2C device 131 on at most eight boards 130 for address configuration. Of course, it can also be that only the control end of one control switch on some boards 130 is connected to the signal configuration end of the logic device 112, the control ends of two control switches on some boards 130 are connected to the signal configuration end of the logic device 112, and the control ends of the three control switches on the remaining boards 130 are all connected to the signal configuration end of the logic device 112. The connection relationship between the control switches on the four boards 130 and the signal configuration end of the logic device 112 can be set according to actual application requirements, and the embodiment of the present application does not limit this.

[0126] Of course, the I2C device 131 in this embodiment is not limited to setting three signal input terminals, and the number can be determined according to the signal input terminals designed for the actual I2C device 131, for example, it can also be set to five signal input terminals, seven signal input terminals, etc. Correspondingly, the address configuration circuit 132 also sets the number of resistors and control switches according to the number of signal input terminals.

[0127] In some embodiments, two or more I2C devices 131 may be disposed on a single board 130. Each I2C device 131 on the same single board 130 may be communicatively connected to the controller 111 via the same I2C bus 120 or via different I2C buses 120.

[0128] It can be understood that, since part of the device address is fixed inside the I2C device 131, the address information of the I2C device 131 is determined according to the fixed device address and the level combination sequence of the signal input terminal. The device addresses of different I2C devices 131 on the same single board 130 can be the same or different. When the device addresses of different I2C devices 131 on the same single board 130 are the same, the signal configuration end of the logic device 112 can also control the level combination sequence of multiple signal input terminals of different I2C devices 131 on the same single board 130 to be different.

[0129] Embodiment 6 like Figure 7 As shown, the server provided in this embodiment includes a management board and at least two CXL boards.

[0130] The management board includes a baseboard management controller BMC and a complex programmable logic device CPLD. The baseboard management controller BMC is connected to communicate with the I2C devices on at least two CXL boards through the I2C bus based on the address of the I2C device.

[0131] Each CXL board includes at least one I2C device and at least one memory stick. The I2C device has an address configuration circuit, and the address configuration circuit includes multiple signal input terminals and multiple resistors. The level combination sequence of the multiple signal input terminals determines the address of the corresponding I2C device. Among them, the first end of the resistor is connected to the power supply, and the second end of a resistor is correspondingly connected to a signal input terminal and a GPIO pin of a complex programmable logic device CPLD. A memory stick on the CXL board corresponds to an I2C device setting, and the I2C device is used to obtain information such as the capacity, temperature or power consumption of the corresponding memory stick.

[0132] The complex programmable logic device CPLD is used to configure the level signal output by the GPIO pin connected to the second end of the resistor and the signal input end to adjust the level of the corresponding connected signal input end so that the level combination sequence of the multiple signal input ends of each I2C device is different.

[0133] It can be understood that when the baseboard management controller BMC communicates with the I2C device on the CXL board through the I2C bus, the signal transmitted by the I2C bus carries the address of the corresponding I2C device, and the level combinations of the multiple signal input ports corresponding to the I2C device controlled by the complex programmable logic device CPLD are different, so that when the baseboard management controller BMC accesses the I2C device through the I2C bus, it can identify and distinguish the I2C device. The baseboard management controller BMC can access the I2C device on the CXL board through the I2C bus, obtain the capacity, temperature or power consumption of the memory bar corresponding to the I2C device, and manage the memory bars on each CXL board according to the obtained memory bar information.

[0134] Specifically, the I2C device may be an EEPROM, in which the capacity and / or power consumption of the corresponding memory bar is stored. The baseboard management controller BMC may access the capacity information and / or power consumption information of the corresponding memory bar stored in the EEPROM through the I2C bus. Alternatively, the I2C device may be a temperature sensor, which is used to obtain the temperature information of the corresponding memory bar, and the baseboard management controller BMC may access the temperature information obtained by the temperature sensor through the I2C bus.

[0135] Among them, when multiple memory sticks are set on the same CXL board, multiple I2C devices are set on the CXL board corresponding to the multiple memory sticks. The baseboard management controller BMC can communicate with each I2C device on the same CXL board through the same I2C bus. If the address configuration circuits of each I2C device on the same CXL board are the same, resulting in the same address of the I2C device, the baseboard management controller BMC will not be able to identify which memory stick the information obtained is from. Therefore, the complex programmable logic device CPLD can also control the level combination sequence of multiple signal input ports corresponding to the I2C device on the same CXL board to be different, so that the addresses of the I2C devices on the same CXL board are also different, so that the baseboard management controller BMC can also identify the I2C devices on the same CXL board.

[0136] The connection relationship between the complex programmable logic device CPLD and the address configuration circuit on each CXL board of the computing device provided in this embodiment can refer to the computing device 100 shown in the above embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0137] It should be noted that those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the embodiments of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computing device, characterized in that include: A plurality of single boards, a logic device and a controller, wherein the logic device is connected to the plurality of single boards respectively, the controller is connected to at least one of the single boards respectively, and the controller is connected to the logic device; The logic device is used to configure the address of the target device on at least one of the single boards, wherein the addresses of the target devices on the multiple single boards are different; The controller communicates with the target device on the corresponding board based on different addresses.

2. The computing device of claim 1, wherein: Each of the target devices has an address configuration circuit, and the address configuration circuit has a plurality of signal input terminals; the level combination sequence of the plurality of signal input terminals determines the address of the corresponding target device; The logic device has a signal configuration terminal, and the signal configuration terminal is used to control the level of the signal input terminal of at least one of the target devices, so that the level combination sequence of the signal input terminals of the target devices is different.

3. The computing device according to claim 1 or 2, characterized in that The target device is any one of a fan, a sensor or a memory.

4. The computing device of claim 2, wherein: The address configuration circuit also includes a plurality of resistors; A first end of the resistor is connected to a power supply, and a second end of the resistor is correspondingly connected to one of the signal input ends; or The first end of the resistor is grounded, and the second end of the resistor is correspondingly connected to the signal input end; Among them, the signal configuration end of the logic device is electrically connected to the second end of the resistor in the address configuration circuit of at least one of the target devices, and the signal configuration end is used to output a level signal to the second end of the resistor so that the level combination sequence of the multiple signal input ends of the target devices on the multiple boards is different.

5. The computing device of claim 4, wherein: The number of target devices on the plurality of boards is N, each of the target devices is provided with M signal input terminals, and the number of the plurality of resistors in each of the address configuration circuits is M; The signal configuration end of the logic device is electrically connected to the second end of one of the resistors in the address configuration circuits of N-1 of the target devices, and the address configuration circuits of the remaining target devices are not connected to the logic device; The logic device is used to configure the level signals of the signal configuration terminals to be all the same.

6. The computing device of claim 4, wherein: The plurality of signal configuration terminals of the logic device are respectively electrically connected to the second terminal of each resistor in the address configuration circuit of each target device; Wherein, the logic device is used to configure the level signals of the plurality of signal configuration terminals.

7. The computing device of claim 4, wherein: The controller is used to generate a write instruction according to the connection information between the resistor in the address configuration circuit of each target device and the logic device; the logic device is used to configure the level signal output by the signal configuration terminal connected to the resistor according to the write instruction.

8. The computing device of claim 2, wherein: The address configuration circuit also includes a plurality of resistors and a plurality of control switches; The first end of the resistor is connected to the power supply, and the second end of the resistor is correspondingly connected to the signal input end; the first end of the control switch is correspondingly connected to the second end of the resistor, and the second end of the control switch is grounded. The control end of at least one of the control switches is connected to the signal configuration end, and the control switch is used to be turned on or off according to the level signal to change the level of the corresponding signal input end; or The first end of the resistor is grounded, and the second end of the resistor is correspondingly connected to the signal input end; the first end of the control switch is correspondingly connected to the second end of the resistor, and the second end of the control switch is connected to the power supply. The control end of at least one of the control switches is connected to the signal configuration end, and the control switch is used to be turned on or off according to the level signal to change the level corresponding to the signal input end.

9. The computing device of claim 8, wherein: The controller is used to generate a write instruction according to the connection information between the control switch in the address configuration circuit of each target device and the logic device; the logic device is used to configure the level signal output by the signal configuration terminal connected to the control switch according to the write instruction.

10. The computing device of claim 1, wherein: The single board is a CXL single board, and at least one memory bar is arranged on the CXL single board. One of the memory bars on the CXL single board is correspondingly arranged with one of the target devices.

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