Chip attenuator and preparation method thereof

Abstract

The invention provides a chip attenuator and a preparation method thereof, and belongs to the technical field of attenuators. The resistance layer comprises a first resistor, a third resistor and a second resistor which are sequentially connected in series, a fourth resistor and a sixth resistor which are connected in parallel between the joint of the first resistor and the second resistor and the ground, and a fifth resistor and a seventh resistor which are connected in parallel between the joint of the second resistor and the third resistor and the ground, and the resistance value of the first resistor is equal to that of the second resistor; the resistance value of the third resistor is the sum of the resistance value of the first resistor and the resistance value of the second resistor, and the resistance values of the fourth resistor, the fifth resistor and the seventh resistor are equal. The chip attenuator manufactured by the invention can meet the requirements of miniaturization, high attenuation and wide frequency band.

Description

Technical Field

[0001] The invention belongs to the technical field of attenuators, and in particular relates to a chip attenuator and a preparation method thereof. Background Art

[0002] An attenuator is an electronic component that provides attenuation and is widely used in electronic equipment. Its main uses are: (1) adjusting the size of the signal in the circuit; (2) in the comparison method measurement circuit, it can be used to directly read the attenuation value of the measured network; (3) improving impedance matching. If some circuits require a relatively stable load impedance, an attenuator can be inserted between this circuit and the actual load impedance to buffer the impedance changes.

[0003] However, with the advent of the 5G era, miniaturization and broadband have become the new trend of microwave components, and the existing attenuators cannot meet the usage requirements. Summary of the invention

[0004] The purpose of the present invention is to provide a chip attenuator and a preparation method thereof, wherein the manufactured chip attenuator can meet the requirements of miniaturization, high attenuation and wide bandwidth.

[0005] The present invention is achieved through the following technical solutions: A chip attenuator includes a resistance layer, which includes a first resistor, a third resistor, and a second resistor connected in series in sequence, a fourth resistor and a sixth resistor connected in parallel between the connection point of the first resistor and the third resistor and ground, and a fifth resistor and a seventh resistor connected in parallel between the connection point of the second resistor and the third resistor and ground. The resistance value of the first resistor is equal to the resistance value of the second resistor, the resistance value of the third resistor is the sum of the resistance value of the first resistor and the resistance value of the second resistor, and the resistance values ​​of the fourth resistor, the fifth resistor, the fifth resistor, and the seventh resistor are equal.

[0006] Furthermore, it also includes a ceramic substrate, an electrode layer and a welding layer. The electrode layer and the resistor layer are arranged on the upper end surface of the ceramic substrate, and the welding layer is arranged on the lower end surface of the ceramic substrate. The electrode layer is composed of a connecting electrode and two ground electrodes. The first resistor, the second resistor and the third resistor are connected in series through the connecting electrode, the fourth resistor and the fifth resistor are connected between the connecting electrode and one of the ground electrodes, and the sixth resistor and the seventh resistor are connected between the connecting electrode and the other ground electrode.

[0007] Furthermore, the electrode layer is formed by a Ti layer, a Pt layer and an Au layer arranged in sequence from top to bottom.

[0008] Furthermore, the electrode layer, the resistance layer and the welding layer are all disposed on the ceramic substrate by sputtering.

[0009] The present invention is also achieved through the following technical solutions: A method for preparing a chip attenuator comprises the following steps: Step S1, sputtering a Ta layer on a ceramic substrate, preparing a TaN layer by reaction of Ta in the Ta layer with nitrogen, and forming a resistance layer through etching the TaN layer; Step S2, sputtering a Ti layer, a Pt layer and an Au layer in sequence on a ceramic substrate as film layers, and removing unnecessary Au, Pt, Ti and TaN by etching to obtain a resistor layer and an electrode layer; Step S3, heat-treating the product processed in step S2 to adjust the square resistance of the product to a target value.

[0010] Furthermore, in step S1, the parameters for preparing the TaN layer include: the pre-sputtering time is set to 180 s, the sputtering power is set to 200 W, the sputtering time is set to 800 s, the nitrogen flow rate is set to 50 sccm, the argon flow rate is set to 50 sccm, the ceramic substrate heating temperature is set to 280 ° C, the sample stage speed is set to 2-4 rpm, and the vacuum degree is set to 8.0x10 -4 -3.0x10 - 4 Pa.

[0011] Furthermore, in step S2, the parameters for preparing the film layer include: the ceramic and urination heating temperatures are set to 280°C, the sample stage speed is set to 2-4 rpm, and the vacuum degree is set to 8.0x10 -4 -3.0x10 -4 Pa, when sputtering the Ti layer, the pre-sputtering time was set to 180s, the sputtering power was set to 400W, the sputtering time was set to 900s, and the argon flow rate was set to 50sccm; when sputtering the Pt layer, the pre-sputtering time was set to 600s, the sputtering power was set to 500W, the sputtering time was set to 900s, and the argon flow rate was set to 50sccm; when sputtering the Au layer, the pre-sputtering time was set to 60s, the sputtering power was set to 500W, the sputtering time was set to 2100s, and the argon flow rate was set to 50sccm.

[0012] Furthermore, in step S2, a coating is applied on the surface of the film layer formed by sputtering. After the coating is applied, the film layer and the resistor layer are etched using a mask and an etching solution to remove unnecessary Au, Pt, Ti, and TaN to obtain a resistor layer and an electrode layer.

[0013] The present invention has the following beneficial effects: 1. The resistance layer of the present invention includes a first resistor, a third resistor and a second resistor connected in series, a fourth resistor and a sixth resistor connected in parallel between the connection point of the first resistor and the third resistor and the ground, and a fifth resistor and a seventh resistor connected in parallel between the connection point of the second resistor and the third resistor and the ground, that is, a same-resistance T-type structure is adopted, and a symmetrical transfer structure and functional resistors are connected in series to optimize the high-frequency performance, high attenuation and miniaturization characteristics of the product, and a two-stage cascade method is adopted to reduce the influence of the temperature drift and coupling of the resistor itself on the product. In the process of the two-stage cascade, the series resistors are combined to reduce the difficulty of the manufacturing process and further improve the miniaturization capability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is further described in detail below with reference to the accompanying drawings.

[0015] Figure 1 Schematic diagram of the resistance layer of the present invention.

[0016] Figure 2 This is a physical picture of the attenuator of the present invention.

[0017] Figure 3 Schematic diagram of the dimensions of the attenuator of the present invention.

[0018] Figure 4 This is a mask sheet corresponding to the resistance layer of the present invention.

[0019] Figure 5 This is a mask sheet corresponding to the electrode layer of the present invention.

[0020] Figure 6 This is a product measurement diagram of the attenuator of the present invention.

[0021] Among them, 1, ceramic substrate; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; 31, connecting electrode; 32, ground electrode. DETAILED DESCRIPTION

[0022] like Figures 1 to 3As shown, the chip attenuator includes a ceramic substrate 1, an electrode layer, a resistor layer and a welding layer, and the ceramic substrate 1 is specifically an alumina ceramic substrate 1. The electrode layer and the resistor layer are arranged on the upper end surface of the ceramic substrate 1, and the welding layer is arranged on the lower end surface of the ceramic substrate 1. The resistor layer includes a first resistor R1, a third resistor R3 and a second resistor R2 connected in series in sequence, a fourth resistor R4 and a sixth resistor R6 connected in parallel between the connection point of the first resistor R1 and the third resistor and the ground, and a fifth resistor R5 and a seventh resistor R7 connected in parallel between the connection point of the second resistor R2 and the third resistor R3 and the ground, the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2, the resistance value of the third resistor R3 is the sum of the resistance value of the first resistor R1 and the resistance value of the second resistor R2, and the resistance values ​​of the fourth resistor R4, the fifth resistor R5, the fifth resistor R5 and the seventh resistor R7 are equal. The electrode layer is composed of a connecting electrode 31 and two ground electrodes 32. The first resistor R1, the second resistor R2 and the third resistor R3 are connected in series through the connecting electrode 31. The fourth resistor R4 and the fifth resistor R5 are connected between the connecting electrode 31 and one of the ground electrodes 32. The sixth resistor R6 and the seventh resistor R7 are connected between the connecting electrode 31 and the other ground electrode 32.

[0023] In this embodiment, the attenuation of the designed attenuator is 10dB. The resistance of the resistance layer can be regarded as a second-order equal-resistance attenuator obtained by connecting two 5dB T-type attenuator circuits in series and performing symmetrical optimization equivalent formation. The first resistor R1 = the second resistor = 14 ohms, and the third resistor is equal to 28 ohms. From the structural point of view, the number of resistors is optimized by series connection, and the third resistor R3 is obtained by merging two resistors in series after cascading two T-type attenuators. From the simulation optimization results, it can be seen that this can not only achieve the same effect but also obtain better performance and smaller size. The fourth resistor R4 = the fifth resistor R5 = the sixth resistor R6 = the seventh resistor R7 satisfies the symmetrical structure, and its parallel equivalent resistance is 164.4 ohms.

[0024] The present invention can achieve a small size of 0.737mm*0.686mm while having good attenuation accuracy and flatness, and can achieve high attenuation within the range of DC~40GHz while having good impedance matching.

[0025] A method for preparing a chip attenuator comprises the following steps: Step S1, sputtering a Ta layer on a ceramic substrate 1, preparing a TaN layer by reaction of Ta in the Ta layer with nitrogen, and forming a resistance layer through etching the TaN layer; The sputtering parameters for preparing the TaN layer are shown in Table 1: Table 1 Step S2, sputtering a Ti layer, a Pt layer and an Au layer in sequence as a film layer on the ceramic substrate 1, performing photoresist coating on the surface of the film layer formed by sputtering, and after the photoresist coating is completed, etching the film layer and the resistor layer using a mask and an etching solution to etch away unnecessary Au, Pt, Ti and TaN to obtain a resistor layer and an electrode layer.

[0026] The sputtering parameters for preparing the film layer are shown in Table 2: Table 2 The coating parameters are shown in Table 3: Table 3 After the product is coated by the coating machine, different masks are used to complete the etching according to different film layers. The mask sheet corresponding to the resistor layer is as follows: Figure 4 As shown, the mask sheet corresponding to the electrode layer is as follows Figure 5 shown.

[0027] Step S3, using a hot furnace to heat treat the product after the treatment in step S2 to adjust the square resistance of the product to a target value; The heat treatment parameters are shown in Table 4: Table 4 like Figure 6 This is the actual measured product diagram of the attenuator of this embodiment. The S11 parameter is in the range of DC~40Ghz, the attenuation curve S21 fluctuates within ±0.6dB, and the standing wave curves are all less than 1.3, achieving good attenuation accuracy and standing wave performance, meeting the design requirements.

[0028] The above description is only a preferred embodiment of the present invention, and therefore cannot be used to limit the scope of implementation of the present invention. That is, equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the specification should still fall within the scope covered by the patent of the present invention.

Claims

1. A chip attenuator, characterized in that: The invention comprises a resistance layer, which comprises a first resistor, a third resistor and a second resistor connected in series in sequence, a fourth resistor and a sixth resistor connected in parallel between the connection point between the first resistor and the third resistor and the ground, and a fifth resistor and a seventh resistor connected in parallel between the connection point between the second resistor and the third resistor and the ground. The resistance value of the first resistor is equal to the resistance value of the second resistor, the resistance value of the third resistor is the sum of the resistance value of the first resistor and the resistance value of the second resistor, and the resistance values ​​of the fourth resistor, the fifth resistor, the sixth resistor and the seventh resistor are equal.

2. A chip attenuator according to claim 1, characterized in that: It also includes a ceramic substrate, an electrode layer and a welding layer. The electrode layer and the resistor layer are arranged on the upper end surface of the ceramic substrate, and the welding layer is arranged on the lower end surface of the ceramic substrate. The electrode layer is composed of a connecting electrode and two ground electrodes. The first resistor, the second resistor and the third resistor are connected in series through the connecting electrode. The fourth resistor and the fifth resistor are connected between the connecting electrode and one of the ground electrodes. The sixth resistor and the seventh resistor are connected between the connecting electrode and the other ground electrode.

3. A chip attenuator according to claim 2, characterized in that: The electrode layer is formed of a Ti layer, a Pt layer and an Au layer which are sequentially arranged from top to bottom.

4. A chip attenuator according to claim 2 or 3, characterized in that: The electrode layer, the resistance layer and the welding layer are all arranged on the ceramic substrate by sputtering.

5. A method for preparing a chip attenuator, characterized in that: The steps include: Step S1, sputtering a Ta layer on a ceramic substrate, preparing a TaN layer by reaction of Ta in the Ta layer with nitrogen, and forming a resistance layer through etching the TaN layer; Step S2, sputtering a Ti layer, a Pt layer and an Au layer in sequence on a ceramic substrate as film layers, and removing unnecessary Au, Pt, Ti and TaN by etching to obtain a resistor layer and an electrode layer; Step S3, heat-treating the product processed in step S2 to adjust the square resistance of the product to a target value.

6. The method for preparing a chip attenuator according to claim 5, characterized in that: The process comprises the following steps: in step S1, the parameters for preparing the TaN layer include: the pre-sputtering time is set to 180s, the sputtering power is set to 200W, the sputtering time is set to 800s, the nitrogen flow rate is set to 50sccm, the argon flow rate is set to 50sccm, the ceramic substrate heating temperature is set to 280°C, the sample stage speed is set to 2-4rpm, and the vacuum degree is set to 8.0x10 -4 -3.0x10 -4 Pa.

7. The method for preparing a chip attenuator according to claim 5, characterized in that: The following steps are included: In step S2, the parameters for preparing the film layer include: the ceramic and urination heating temperature is set to 280°C, the sample stage speed is set to 2-4rpm, and the vacuum degree is set to 8.0x10 -4 -3.0x10 -4 Pa, when sputtering the Ti layer, the pre-sputtering time was set to 180s, the sputtering power was set to 400W, the sputtering time was set to 900s, and the argon flow rate was set to 50sccm; when sputtering the Pt layer, the pre-sputtering time was set to 600s, the sputtering power was set to 500W, the sputtering time was set to 900s, and the argon flow rate was set to 50sccm; when sputtering the Au layer, the pre-sputtering time was set to 60s, the sputtering power was set to 500W, the sputtering time was set to 2100s, and the argon flow rate was set to 50sccm.

8. The method for preparing a chip attenuator according to claim 5, 6 or 7, characterized in that: The method comprises the following steps: in step S2, a film layer surface formed by sputtering is coated, and after the coating is completed, the film layer and the resistor layer are etched using a mask and an etching solution to remove unnecessary Au, Pt, Ti, and TaN to obtain a resistor layer and an electrode layer.

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