High-voltage level shift circuit and layout structure thereof

Abstract

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology and power integrated circuits, and in particular to a high-voltage level shift circuit and its layout structure. Background Art

[0002] HVIC (High Voltage Integrated Circuit) is usually used to drive semiconductor power devices connected in half-bridge, and is often used to drive motors to control automotive electronics, electric motors, etc. The input end of HVIC receives control signals from MCU (Microcontroller Unit) and other devices, and outputs signals for driving high-side power devices and low-side power devices in half-bridge circuits. The high-voltage level shift circuit is a key part of HVIC, which is used to realize the conversion of low-voltage domain signals to high-voltage domain signals, and then realize the driving of high-side power devices in the half-bridge topology. The dynamic power consumption and transmission delay of HVIC mainly come from the high-voltage level shift circuit.

[0003] High-voltage level shift circuits usually use dual narrow pulse level shift circuits to transmit high-side power device drive signals to reduce power consumption. LDMOS (Lateral Double-diffused MOSFET) devices in high-voltage level shift circuits generally have large parasitic capacitance. Therefore, when the high-side power device is turned on, the potential of VS (high-voltage domain floating ground) and VB (high-voltage domain floating power supply) rises rapidly, which will generate displacement current flowing through the load resistor R to charge the parasitic capacitor C. The voltage drop caused by the displacement current flowing through the load resistor may cause the RS trigger to be falsely triggered, which is generally called dV / dt noise (voltage transient noise).

[0004] In the prior art, RC filter circuits are often used to filter out dV / dt noise. However, this noise filtering method has certain disadvantages. On the one hand, the filter width of the RC filter circuit is generally set to tens of nanoseconds, resulting in a large HVIC transmission delay, which cannot meet the requirements of low-latency applications. On the other hand, due to the existence of the RC filter circuit, in order to ensure that the width of the narrow pulse signal after filtering can trigger the RS trigger, the width of the narrow pulse signal transmitted in the high-voltage level shift circuit is generally set to more than 200 nanoseconds. Whenever the input signal level switches, the LDMOS is turned on for a long time, and the main source of dynamic power consumption of the high-voltage level shift circuit is the large current flowing through the LDMOS after it is turned on, which makes it impossible to meet the requirements of low-power applications.

[0005] Based on this, how to provide a high-voltage level shift circuit that can meet the application requirements of low latency and low power consumption has become an urgent problem to be solved. Summary of the invention

[0006] In order to solve at least one problem existing in the prior art, the purpose of the present application is to provide a high-voltage level shifting circuit and its layout structure, which can not only enhance the common-mode noise filtering capability and anti-VS negative bias capability of the voltage transient noise filtering module without increasing the transmission delay, effectively reducing the chip transmission delay, but also ensure that the narrow pulse signal width is not lost during the transmission process, effectively reducing the narrow pulse signal width, thereby reducing dynamic power consumption.

[0007] To achieve the above object, the present application provides a high voltage level shift circuit, comprising: The pulse generating module is configured to receive an input signal, generate a dual-path low-voltage domain narrow pulse signal corresponding to the rising edge and the falling edge of the input signal, and send the signals to the level shifting module; The level shift module is configured to convert the received dual-channel low-voltage domain narrow pulse signal into a corresponding dual-channel high-voltage domain narrow pulse signal, and send it to the voltage transient noise filtering module; A voltage transient noise detection module is configured to detect voltage transient noise of the high-voltage level shift circuit, generate a transient noise intensity signal, and send it to the voltage transient noise filtering module; A voltage transient noise filtering module is configured to perform voltage transient noise filtering on the dual-channel high-voltage domain narrow pulse signal based on the received transient noise intensity signal, generate a dual-channel high-voltage domain filtered signal, and send it to the RS trigger; The RS trigger is configured to convert the received dual-path high-voltage domain filter signal into a high-side power device drive signal.

[0008] Optionally, the level shift module includes: a first resistor, a second resistor, a third resistor, and a fourth resistor; a first diode, wherein the positive electrode is connected to the high-voltage domain floating ground, and the negative electrode is connected to the high-voltage domain floating power supply through the first resistor; a second diode, with an anode connected to the high-voltage domain floating ground and a cathode connected to the high-voltage domain floating power supply through the second resistor; A third diode, whose anode is connected to the cathode of the first diode and connected to the first high-voltage domain narrow pulse signal output terminal of the level shift module, and whose cathode is connected to the high-voltage domain floating power supply; a fourth diode, wherein the anode is connected to the cathode of the second diode and is connected to the second high-voltage domain narrow pulse signal output terminal of the level shift module, and the cathode is connected to the high-voltage domain floating power supply; A first LDMOS tube, whose gate is used to input a first low-voltage domain narrow pulse signal, whose drain is connected to the first high-voltage domain narrow pulse signal output terminal through the third resistor, and whose source is grounded; The second LDMOS tube has a gate for inputting a second low-voltage domain narrow pulse signal, a drain connected to the second high-voltage domain narrow pulse signal output terminal through the fourth resistor, and a source grounded.

[0009] Optionally, the voltage transient noise detection module includes: a fifth resistor and a sixth resistor; a fifth diode, connected in parallel with the fifth resistor, with a cathode connected to the high-voltage domain floating power supply and a positive electrode connected to the transient noise intensity signal output terminal; a sixth diode, an anode of which is connected to the floating ground of the high-voltage domain, and a cathode of which is connected to the anode of the fifth diode; The gate and source of the third LDMOS tube are grounded, and the drain is connected to the anode of the fifth diode through the sixth resistor.

[0010] Further optionally, the high-voltage level shift circuit satisfies at least one of the following conditions: The resistance values ​​of the first resistor, the second resistor and the fifth resistor are equal; The resistance values ​​of the third resistor, the fourth resistor and the sixth resistor are equal; The first diode, the second diode and the sixth diode have the same size; The third diode, the fourth diode and the fifth diode have the same size; The first LDMOS transistor, the second LDMOS transistor and the third LDMOS transistor have the same size.

[0011] Optionally, the voltage transient noise filtering module includes: A first current mirror structure includes a first PMOS tube and a second PMOS tube, wherein the source electrodes of the first PMOS tube and the gate electrodes of the second PMOS tube are connected to the high-voltage domain floating power supply, and the gate electrodes of the first PMOS tube and the drain electrodes of the second PMOS tube are connected to the high-voltage domain floating power supply. A second current mirror structure includes the first PMOS tube and a third PMOS tube, wherein a source of the third PMOS tube is connected to the high-voltage domain floating power supply; A first NMOS tube, sharing a drain with the first PMOS tube; a source of the first NMOS tube connected to the anode of the third diode, and a gate connected to the anode of the fourth diode; A third current mirror structure includes a fourth PMOS tube and a fifth PMOS tube, wherein the source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected to the high-voltage domain floating power supply, and the gate electrodes are connected to the drain electrode of the fourth PMOS tube; a fourth current mirror structure, comprising the fourth PMOS tube and a sixth PMOS tube, wherein a source of the sixth PMOS tube is connected to the high-voltage domain floating power supply; A second NMOS tube shares a drain with the first PMOS tube; a source of the second NMOS tube is connected to the anode of the third diode, and a gate is connected to the source of the first NMOS tube; A fifth current mirror structure comprises a third NMOS tube and a fourth NMOS tube, wherein the sources of the third NMOS tube and the fourth NMOS tube are connected to the floating ground of the high voltage domain, and the gates are connected to the drain of the third NMOS tube; the third NMOS tube and the second PMOS tube share a drain; and the fourth NMOS tube and the sixth PMOS tube share a drain; The sixth current mirror structure includes a fifth NMOS tube and a sixth NMOS tube, the sources of which are connected to the floating ground of the high-voltage domain, and the gates are connected to the drain of the fifth NMOS tube; the fifth NMOS tube and the fifth PMOS tube share a drain; the sixth NMOS tube and the third PMOS tube share a drain.

[0012] Further optionally, the voltage transient noise filtering module further includes: The seventh PMOS tube and the eighth PMOS tube share a common gate and source, the source is connected to the high-voltage domain floating power supply, and the gate is connected to the anode of the fifth diode; the drain of the seventh PMOS tube is connected to the gate of the first NMOS tube; the drain of the eighth PMOS tube is connected to the gate of the second NMOS tube.

[0013] Optionally, the voltage transient noise filtering module further includes: a ninth PMOS tube, wherein the source electrode is connected to the high-voltage domain floating power supply, and the gate electrode is connected to the anode of the fifth diode; a seventh current mirror structure, comprising a seventh NMOS tube and an eighth NMOS tube, wherein the sources of the seventh NMOS tube and the eighth NMOS tube are connected to the floating ground of the high voltage domain, and the gates are connected to the drain of the seventh NMOS tube; the seventh NMOS tube and the ninth PMOS tube share a drain; and the eighth NMOS tube and the second PMOS tube share a drain; The ninth NMOS tube shares a drain with the fifth NMOS tube, shares a gate with the seventh NMOS tube, and has a source connected to the high-voltage domain floating ground.

[0014] Optionally, the high-voltage level shift circuit further includes: a seventh resistor, connected between the high-voltage domain floating power supply and the drain of the sixth NMOS tube; An eighth resistor is connected between the high-voltage domain floating power supply and the drain of the fourth NMOS tube.

[0015] Optionally, the high voltage level shift circuit is configured as: receiving an input signal; In response to the input signal becoming a high level, a first low-voltage domain narrow pulse signal corresponding to the rising edge of the input signal is generated to generate a first high-voltage domain narrow pulse signal and pull it down to the high-voltage domain floating ground potential interval; and a first high-voltage domain filter signal is generated and pulled down to the high-voltage domain floating ground potential, so that a high-side power device drive signal is output to drive the corresponding half-bridge high-side power device to turn on; Wherein, in response to the input signal being at a high level and positive transient noise being detected, a transient noise intensity signal is generated and pulled down to the high-voltage domain floating ground VS potential interval; in response to detecting the end of the positive transient noise, the transient noise intensity signal rises, and the first high-voltage domain filter signal drops to the high-voltage domain floating ground potential until the duration of the first low-voltage domain narrow pulse signal ends; In response to the input signal becoming a low level, a second low-voltage domain narrow pulse signal corresponding to the falling edge of the input signal is generated to generate a second high-voltage domain narrow pulse signal and is pulled down to the high-voltage domain floating ground potential interval; and a second high-voltage domain filter signal is generated and is pulled down to the high-voltage domain floating ground potential, so that the high-side power device drive signal becomes the high-voltage domain floating ground potential, so as to drive the half-bridge high-side power device to turn off; In which, in response to the input signal becoming a low level and detecting negative transient noise, the potential of the second high-voltage domain filter signal rises from the high-voltage domain floating ground potential; in response to detecting the end of the negative transient noise, the potential of the second high-voltage domain filter signal is pulled down to the high-voltage domain floating ground potential until the duration of the second low-voltage domain narrow pulse signal ends.

[0016] To achieve the above-mentioned purpose, the present application also provides a layout structure of a high-voltage level shift circuit, including the high-voltage level shift circuit as described above; The high-voltage level shift circuit includes a high-voltage domain and a low-voltage domain, wherein a high-voltage isolation structure is provided on the periphery of the high-voltage domain to isolate and define the high-voltage domain; at least one of the first LDMOS tube, the second LDMOS tube and the third LDMOS tube is configured to be located in the high-voltage isolation structure.

[0017] According to the high-voltage level shifting circuit of the embodiment of the present application, an input signal is received through a pulse generating module, and a dual-path low-voltage domain narrow pulse signal corresponding to the rising edge and the falling edge of the input signal is generated, and sent to the level shifting module; and the dual-path low-voltage domain narrow pulse signal is received through the level shifting module, converted into a corresponding dual-path high-voltage domain narrow pulse signal, and sent to the voltage transient noise filtering module; and the voltage transient noise of the high-voltage level shifting circuit is detected through the voltage transient noise detection module, and a transient noise intensity signal is generated, which is sent to the voltage transient noise filtering module; and the voltage transient noise filtering module performs voltage transient noise filtering on the dual-path high-voltage domain narrow pulse signal based on the received transient noise intensity signal, generates a dual-path high-voltage domain filtered signal, and sends it to the RS trigger.

[0018] Therefore, on the one hand, the voltage transient noise detection module is used to convert the noise voltage signal into a current compensation signal, and the auxiliary voltage transient noise filtering module is used to achieve dV / dt noise filtering, which can enhance the common mode noise filtering capability and the ability to resist VS negative bias of the voltage transient noise filtering module without increasing the transmission delay, and effectively reduce the chip transmission delay. On the other hand, the voltage transient noise detection module and the voltage transient noise filtering module are used to replace the RC filter circuit in the related technology, and the narrow pulse signal width is basically not lost during the transmission process while ensuring the noise filtering effect. Therefore, the narrow pulse signal width can be reduced while ensuring the chip's ability to resist dV / dt noise, and the LDMOS device turn-on time can be reduced, thereby effectively reducing the chip power consumption.

[0019] According to the layout structure of the high-voltage level shift circuit in the embodiment of the present application, by configuring at least one of the first LDMOS tube, the second LDMOS tube and the third LDMOS tube to be located in the high-voltage isolation structure, the noise filtering circuit does not require a filter capacitor, which can effectively reduce the layout area and facilitate production and manufacturing.

[0020] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings: Figure 1 It is a structural schematic diagram of a high voltage level shift circuit in the related art; Figure 2 is a schematic structural diagram of a high-voltage level shift circuit according to an embodiment of the present application; Figure 3 is a structural schematic diagram of a high-voltage level shift circuit according to another embodiment of the present application; Figure 4 for Figure 3 Working waveform of medium and high voltage level shift circuit; Figure 5 is a structural schematic diagram of a high-voltage level shift circuit according to yet another embodiment of the present application; Figure 6 for Figure 5 Working waveform of medium and high voltage level shift circuit; Figure 7 Schematic diagram of the layout structure of a high-voltage level shift circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

[0023] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0024] It should be noted that the concepts such as "first" and "second" mentioned in this application are only used to distinguish different modules, devices or structures, and are not used to limit the order, interdependence or relative importance of the functions performed by these modules, devices or structures.

[0025] It should be noted that the modifications of "one" and "plurality" mentioned in this application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

[0026] It should be noted that the relationship between structures should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. In the description of the present invention, it should be noted that the terms "inside" and "outside" etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0027] First of all, it should be noted that high-voltage level shift circuits usually use dual narrow pulse level shift circuits to transmit high-side power device drive signals to reduce power consumption. Dual narrow pulse level shift circuits refer to a level shift circuit structure that transmits the rising and falling edge information of the high-side power device drive signal in the form of narrow pulse signals through two level shift circuits from the low voltage area to the high voltage area.

[0028] In related technologies, such as Figure 1 As shown, the high voltage level shift circuit 100 includes a narrow pulse generating circuit 110 , a dual narrow pulse level shift circuit 120 , an RC filtering circuit 130 and an RS trigger 140 .

[0029] Its working principle is as follows: when the rising edge of the input signal VIN arrives, the pulse generating circuit 110 generates a first narrow pulse signal VINS at the rising edge of the input signal VIN, and the signal is transmitted to the corresponding first high-voltage domain narrow pulse signal VDS in the high-voltage domain through the dual-path narrow pulse level shift circuit 120. The VDS signal is filtered by the RC filter circuit 130 and becomes the first high-voltage domain filter signal VOS, and the RS trigger 140 is set, so that the output of the RS trigger 140 becomes high, driving the corresponding high-side power device to turn on; when the falling edge of the input signal VIN arrives, the pulse generating circuit 110 generates a second narrow pulse signal VINR at the falling edge of the input signal VIN, and the signal is transmitted to the corresponding second high-voltage domain narrow pulse signal VDR in the high-voltage domain through the dual-path narrow pulse level shift circuit 120. The VDR signal is filtered by the RC filter circuit 130 and becomes the second high-voltage domain filter signal VOR, and the RS trigger 140 is reset, and the RS trigger output 140 becomes low, driving the high-side power device to turn off.

[0030] use Figure 1 When the high-voltage level shift circuit 100 is used, the filter width of the RC filter circuit 130 is generally set to tens of nanoseconds, resulting in a large HVIC transmission delay, which cannot meet the low-delay application requirements. In addition, due to the existence of the RC filter circuit 130, in order to ensure that the width of the narrow pulse signal after filtering can trigger the RS trigger 140, the width of the narrow pulse signal transmitted in the high-voltage level shift circuit 100 is generally set to more than 200 nanoseconds. Whenever the input signal level switches, the LDMOS is turned on for a long time, which cannot meet the low-power application requirements.

[0031] Based on this, the present application provides a high-voltage level shifting circuit and its layout structure, which can not only enhance the common-mode noise filtering capability and anti-VS negative bias capability of the voltage transient noise filtering module without increasing the transmission delay, effectively reducing the chip transmission delay, but also make the narrow pulse signal width lossless during the transmission process, effectively reducing the narrow pulse signal width, thereby reducing dynamic power consumption.

[0032] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0033] Figure 2 The schematic diagram of the high voltage level shift circuit according to the embodiment of the present application is shown below. Figure 2 , the high voltage level shift circuit of the present application is described in detail.

[0034] The high voltage level shift circuit 200 includes: a pulse generating module 210 , a level shifting module 220 , a voltage transient noise detecting module 230 , a voltage transient noise filtering module 240 and an RS trigger 250 .

[0035] Among them, the pulse generating module 210 is configured to receive the input signal VIN, generate a dual-path low-voltage domain narrow pulse signal, namely a first low-voltage domain narrow pulse signal VINS corresponding to the rising edge of the input signal VIN, and a second low-voltage domain narrow pulse signal VINR corresponding to the falling edge of the input signal VIN, and send the dual-path low-voltage domain narrow pulse signal to the level shifting module 220.

[0036] The level shift module 220 is configured to receive the dual-channel low-voltage domain narrow pulse signal VINS / VINR, convert it into a corresponding dual-channel high-voltage domain narrow pulse signal VDS / VDR, and send it to the voltage transient noise filtering module 240 .

[0037] The voltage transient noise detection module 230 is configured to detect the voltage transient noise dV / dt of the high-voltage level shift circuit 200 , generate a transient noise intensity signal VDN, and send it to the voltage transient noise filtering module 240 .

[0038] The voltage transient noise filtering module 240 is configured to perform voltage transient noise filtering on the dual-channel high-voltage domain narrow pulse signals VDS / VDR based on the received transient noise intensity signal VDN, generate dual-channel high-voltage domain filtered signals VOS / VOR, and send them to the RS trigger 250.

[0039] The RS flip-flop 250 is configured to convert the received dual-path high-voltage domain filter signal VOR / VOS into a high-side power device driving signal VOUT.

[0040] The working principle of the high-voltage level shift circuit provided in the present application is as follows: the pulse generating module 210 generates a first low-voltage domain narrow pulse signal VINS at the rising edge of the input signal VIN, and generates a second low-voltage domain narrow pulse signal VINR at the falling edge of the input signal VIN; the level shifting circuit 220 converts the VINS signal and the VINR signal in the low-voltage domain into a first high-voltage domain narrow pulse signal VDS and a second high-voltage domain narrow pulse signal VDR in the high-voltage domain, respectively; the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR are filtered out of dV / dt noise (voltage transient noise) by the voltage transient noise filtering module 240, and outputs a first high-voltage domain filter signal VOS and a second high-voltage domain filter signal VOR; the RS trigger 250 restores the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR to a high-side power device drive signal VOUT; the voltage transient noise detection module 230 is used to detect the dV / dt intensity, convert the noise voltage signal into a current compensation signal, and assist the voltage transient noise filtering module 240 to achieve dV / dt noise filtering.

[0041] Therefore, on the one hand, the voltage transient noise detection module is used to convert the noise voltage signal into a current compensation signal, and the auxiliary voltage transient noise filtering module is used to achieve dV / dt noise filtering, which can enhance the common mode noise filtering capability and the ability to resist VS negative bias of the voltage transient noise filtering module, without increasing the transmission delay, and can effectively reduce the chip transmission delay. On the other hand, the voltage transient noise detection module and the voltage transient noise filtering module are used to replace the RC filter circuit in the related technology, while ensuring the noise filtering effect, the narrow pulse signal width is basically not lost during the transmission process, so the narrow pulse signal width can be reduced while ensuring the chip's ability to resist dV / dt noise, and the LDMOS device turn-on time can be reduced, thereby effectively reducing the chip power consumption.

[0042] In addition, the working principle of the RS trigger is: when the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR are both high voltage, the output high-side power device drive signal VOUT remains unchanged; when the second high-voltage domain filter signal VOR is high voltage, the first high-voltage domain filter signal VOS jumps from high voltage to low voltage, and the output high-side power device drive signal VOUT becomes high voltage; when the first high-voltage domain filter signal VOS is high voltage, the second high-voltage domain filter signal VOR jumps from high voltage to low voltage, and the output high-side power device drive signal VOUT becomes low voltage.

[0043] In the present application embodiment, Figure 2As shown, the level shift module 220 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first LDMOS transistor M1 and a second LDMOS transistor M2.

[0044] The first diode D1 has an anode connected to the high-voltage domain floating ground VS, and a cathode connected to the high-voltage domain floating power supply VB through the first resistor R1.

[0045] The second diode D2 has an anode connected to the high-voltage domain floating ground VS, and a cathode connected to the high-voltage domain floating power supply VB through a second resistor R2.

[0046] The third diode D3 has an anode connected to the cathode of the first diode D1 and connected to the first high-voltage domain narrow pulse signal VDS output terminal of the level shift module 220 , and a cathode connected to the high-voltage domain floating power supply VB.

[0047] The fourth diode D4 has an anode connected to the cathode of the second diode D2 and connected to the second high-voltage domain narrow pulse signal VDR output terminal of the level shift module 220 , and a cathode connected to the high-voltage domain floating power supply VB.

[0048] The first LDMOS tube M1 has a gate for inputting the first low-voltage domain narrow pulse signal VINS, a drain connected to the output end of the first high-voltage domain narrow pulse signal VDS via the third resistor R3, and a source grounded.

[0049] The second LDMOS tube M2 has a gate for inputting the second low-voltage domain narrow pulse signal VINR; a drain connected to the output end of the second high-voltage domain narrow pulse signal VDR via a fourth resistor R4, and a source grounded.

[0050] Furthermore, if Figure 3 and Figure 5 As shown, the level shift module 220 may further include: a first parasitic capacitor C1 and a second parasitic capacitor C2.

[0051] The first parasitic capacitor C1 has two ends connected to the drain and the source of the first LDMOS transistor M1 in a one-to-one correspondence.

[0052] The second parasitic capacitor C2 has two ends connected to the drain and the source of the second LDMOS transistor M2 in a one-to-one correspondence.

[0053] The working principle of the level shift module 220 is as follows: when the first low-voltage domain narrow pulse signal VINS is at a high level, the first LDMOS tube M1 is turned on, and a current flows from the high-voltage domain floating power supply VB through the first resistor R1 and the third resistor R3, and flows into the drain end of the first LDMOS tube M1. The output end of the first high-voltage domain narrow pulse signal VDS is pulled down to the high-voltage domain floating ground VS potential interval. The VS potential interval is the potential near the VS potential. At this time, the second low-voltage domain narrow pulse signal VINR is at a low level, and the second LDMOS tube M2 is turned off, so the output end of the second high-voltage domain narrow pulse signal VDR is pulled up to the high-voltage domain floating power supply VB potential.

[0054] When the second low-voltage domain narrow pulse signal VINR is at a high level, the second LDMOS tube M2 is turned on, and a current flows from the high-voltage domain floating power supply VB through the second resistor R2 and the fourth resistor R4, and flows into the drain end of the second LDMOS tube M2. The output end of the second high-voltage domain narrow pulse signal VDR is pulled down to the high-voltage domain floating ground VS interval, that is, the potential near the VS potential. At this time, the first low-voltage domain narrow pulse signal VINS is at a low level, and the first LDMOS tube M1 is turned off, so the output end of the first high-voltage domain narrow pulse signal VDS is pulled up to the high-voltage domain floating power supply VB potential.

[0055] Among them, the functions of the third resistor R3 and the fourth resistor R4 are: when the positive transient noise +dV / dt comes, the impedance on the path from the high-voltage domain floating power supply VB to the first parasitic capacitor C1 and the second parasitic capacitor C2 is increased to reduce the voltage transient noise stress at both ends of the parasitic capacitor, and reduce the displacement current flowing through the first resistor R1 and the second resistor R2, thereby reducing the dV / dt noise at the output end of the level shift module 220.

[0056] In the present application embodiment, Figure 3 and Figure 5 As shown, the voltage transient noise detection module 230 includes: a fifth resistor R5, a sixth resistor R6, a fifth diode D5, a sixth diode D6, a third LDMOS tube M3 and a third parasitic capacitor C3.

[0057] The fifth diode D5 is connected in parallel with the fifth resistor R5, and its cathode is connected to the high-voltage domain floating power supply VB, and its anode is connected to the output end of the transient noise intensity signal VDN.

[0058] The sixth diode D6 has an anode connected to the high-voltage domain floating ground VS, and a cathode connected to the anode of the fifth diode D5.

[0059] The gate and source of the third LDMOS tube M3 are grounded, and the drain is connected to the anode of the fifth diode D5 through the sixth resistor R6.

[0060] The third parasitic capacitor C3 has two ends connected to the drain and the source of the third LDMOS transistor M3 in a one-to-one correspondence.

[0061] The working principle of the voltage transient noise detection module 230 is as follows: when the positive transient noise +dV / dt comes, the potential of the high-voltage domain floating ground VS and the high-voltage domain floating power supply VB rises rapidly, and a displacement current flows through the fifth resistor R5 and the sixth resistor R6, and charges the third parasitic capacitor C3 of the third LDMOS tube M3. The voltage drop generated by the displacement current on the fifth resistor R5 is VB-VDN (where VDN is the potential between the fifth resistor R5 and the sixth resistor R6), and the voltage drop VB-VDN increases with the increase of the dV / dt noise intensity. When there is no voltage transient noise dV / dt, no current flows through the voltage transient noise detection module 230, and the transient noise intensity signal VDN is pulled up to the VB potential. At this time, the voltage transient noise detection module 230 has no effect on the operation of the voltage transient noise filtering module 240.

[0062] Optionally, the high voltage level shift circuit satisfies at least one of the following conditions: The resistance values ​​of the first resistor R1, the second resistor R2 and the fifth resistor R5 are equal; The resistance values ​​of the third resistor R3, the fourth resistor R4 and the sixth resistor R6 are equal; The first diode D1, the second diode D2 and the sixth diode D6 have the same size; The third diode D3, the fourth diode D4 and the fifth diode D5 have the same size; The first LDMOS transistor M1 , the second LDMOS transistor M2 , and the third LDMOS transistor M3 have the same size.

[0063] Preferably, the high-voltage level shift circuit meets all the above conditions to achieve better technical effects.

[0064] In the present application embodiment, Figure 3 and Figure 5 As shown, the voltage transient noise filtering module 240 includes: a first current mirror structure, a second current mirror structure, a first NMOS transistor MN1, a third current mirror structure, a fourth current mirror structure, a second NMOS transistor MN2, a fifth current mirror structure and a sixth current mirror structure.

[0065] The first current mirror structure includes a first PMOS transistor MP1 and a second PMOS transistor MP2, the sources of which are connected to a high-voltage domain floating power supply VB, and the gates of which are connected to the drain of the first PMOS transistor MP1.

[0066] The second current mirror structure includes a first PMOS tube MP1 and a third PMOS tube MP3, and a source of the third PMOS tube MP3 is connected to a high-voltage domain floating power supply VB.

[0067] The first NMOS tube MN1 shares a drain with the first PMOS tube MP1; the source of the first NMOS tube MN1 is connected to the anode of the third diode D3, i.e., the output end of the first high-voltage domain narrow pulse signal VDS, and the gate is connected to the anode of the fourth diode D4, i.e., the output end of the second high-voltage domain narrow pulse signal VDR.

[0068] The third current mirror structure includes a fourth PMOS tube MP4 and a fifth PMOS tube MP5, the sources of which are connected to the high-voltage domain floating power supply VB, and the gates of which are connected to the drain of the fourth PMOS tube MP4.

[0069] The fourth current mirror structure includes a fourth PMOS tube MP4 and a sixth PMOS tube MP6, and a source of the sixth PMOS tube MP6 is connected to the high-voltage domain floating power supply VB.

[0070] The second NMOS transistor MN2 shares a drain with the first PMOS transistor MP1 ; the source of the second NMOS transistor MN2 is connected to the anode of the third diode D3 , and the gate is connected to the source of the first NMOS transistor MN1 .

[0071] The fifth current mirror structure includes a third NMOS tube MN3 and a fourth NMOS tube MN4, the sources of which are connected to the high-voltage domain floating ground VS, and the gates are connected to the drain of the third NMOS tube MN3; the third NMOS tube MN3 and the second PMOS tube MP2 share a drain; the fourth NMOS tube MN4 and the sixth PMOS tube MP6 share a drain.

[0072] The sixth current mirror structure includes a fifth NMOS tube MN5 and a sixth NMOS tube MN6, the sources of which are connected to the high-voltage domain floating ground VS, and the gates are connected to the drain of the fifth NMOS tube MN5; the fifth NMOS tube MN5 and the fifth PMOS tube MP5 share a drain; the sixth NMOS tube MN6 and the third PMOS tube MP3 share a drain.

[0073] As an example, Figure 3 As shown, the voltage transient noise filtering module 240 further includes: a seventh PMOS tube MP7 and an eighth PMOS tube MP8. The seventh PMOS tube MP7 and the eighth PMOS tube MP8 share a common gate and a common source. The source of the two is connected to the high-voltage domain floating power supply VB, and the gate is connected to the positive electrode of the fifth diode D5, that is, the transient noise intensity signal VDV output end. The drain of the seventh PMOS tube MP7 is connected to the gate of the first NMOS tube MN1; the drain of the eighth PMOS tube MP8 is connected to the gate of the second NMOS tube MN2.

[0074] In this example, the high-voltage level shift circuit further includes: a seventh resistor R7 and an eighth resistor R8. The seventh resistor R7 is connected between the high-voltage domain floating power supply VB and the drain of the sixth NMOS transistor MN6, that is, connected between the high-voltage domain floating power supply VB and the output terminal of the first high-voltage domain filter signal VOS. The eighth resistor R8 is connected between the high-voltage domain floating power supply VB and the drain of the fourth NMOS transistor MN4, that is, connected between the high-voltage domain floating power supply VB and the output terminal of the second high-voltage domain filter signal VOR.

[0075] The working principle of the voltage transient noise filtering module 240 in this example is as follows: when there is no voltage transient noise dV / dt, within the duration of the first low-voltage domain narrow pulse signal VINS corresponding to the rising edge of the input signal VIN, the first LDMOS tube M1 is turned on, and the potential of the first high-voltage domain narrow pulse signal VDS is pulled down to near the potential of the high-voltage domain floating ground VS, while at this time the second high-voltage domain narrow pulse signal VDR is maintained at the potential of the high-voltage domain floating power supply VB, the first NMOS tube MN1 is turned on, the second NMOS tube MN2 is turned off, and current flows through the branch formed by the first PMOS tube MP1 and the first NMOS tube MN1. Since the first PMOS tube MP1 and the second PMOS tube MP2 form a first current mirror structure, current flows through the branch formed by the second PMOS tube MP2 and the third NMOS tube MN3. The third NMOS tube MN3 and the fourth NMOS tube MN4 form a current mirror structure. The fourth NMOS tube MN4 is turned on. Since the sixth PMOS tube MP6 is turned off, the potential of the first high-voltage domain filter signal VOS is pulled down to the high-voltage domain floating ground VS potential; the first PMOS tube MP1 and the third PMOS tube MP3 form a current mirror structure. The third PMOS tube MP3 is turned on. Since the sixth NMOS tube MN6 is turned off, the potential of the first high-voltage domain filter signal VOS is pulled up to the high-voltage domain floating power supply VB potential.

[0076] During the duration of the second low-voltage domain narrow pulse signal VINR corresponding to the falling edge of the input signal VIN, based on the symmetrical circuit structure, the second high-voltage domain filter signal VOR is pulled down to the high-voltage domain floating ground VS potential, and the first high-voltage domain filter signal VOS is pulled up to the high-voltage domain floating power supply VB potential.

[0077] When a positive transient noise +dV / dt of a certain intensity comes, the potentials of the first high-voltage domain narrow pulse signal VDS, the second high-voltage domain narrow pulse signal VDR, and the transient noise intensity signal VDN are simultaneously reduced to near the high-voltage domain floating ground VS potential.

[0078] The seventh PMOS tube MP7 and the eighth PMOS tube MP8 are turned on to reduce the amplitude of the dV / dt noise signal at VDS and VDR. Since the two branches of the level shift module 220 are exactly the same, VDS and VDR are basically at the same potential at this time. This means that the gate and source of the first NMOS tube MN1 are basically at the same potential as the gate and source of the second NMOS tube MN2. The first NMOS tube MN1 and the second NMOS tube MN2 are turned off, there is no current in the voltage transient noise filtering module 240, the third PMOS tube MP3, the fourth NMOS tube MN4, the sixth PMOS tube MP6, and the sixth NMOS tube MN6 are all turned off, and the VOS and VOR potentials are pulled up to the high-voltage domain floating power supply VB by the seventh resistor R7 and the eighth resistor R8 to achieve the purpose of filtering out dV / dt noise.

[0079] Figure 4 for Figure 5 The waveform diagram corresponding to the medium and high voltage level shift circuit example. The working process of the high voltage level shift circuit in this example will be explained below in combination with the waveform diagram.

[0080] When the input signal VIN becomes a high level, the first low-voltage domain narrow pulse signal VINS corresponding to the rising edge becomes a high level, the first high-voltage domain narrow pulse signal VDS output by the level shift module 220 is pulled down to the vicinity of the high-voltage domain floating ground VS potential, the first NMOS tube MN1 is turned on, and the first high-voltage domain filter signal VOS output by the voltage transient noise filtering module 240 is pulled down from the high-voltage domain floating power supply VB potential to the high-voltage domain floating ground VS potential through the current mirror structure composed of the first PMOS tube MP1 and the second PMOS tube MP2 and the current mirror structure composed of the third NMOS tube MN3 and the fourth NMOS tube MN4. The RS trigger is set by the first high-voltage domain filter signal VOS and the output changes from the high-voltage domain floating ground VS potential to the high-voltage domain floating power supply VB potential. This signal drives the external half-bridge high-side power device of the chip to turn on, and the high-voltage domain floating power supply VB and the high-voltage domain floating ground VS potential rise rapidly. +dV / dt comes and continues until the high-voltage domain floating ground VS potential rises to the chip external half-bridge bus voltage.

[0081] When negative transient noise +dV / dt comes, the displacement current flows through the first resistor R1, the second resistor R2, and the fifth resistor R5 to charge the first parasitic capacitor C1, the second parasitic capacitor C2, and the third parasitic capacitor C3 respectively, and the potential of the first high-voltage domain narrow pulse signal VDS, the second high-voltage domain narrow pulse signal VDR, and the transient noise intensity signal VDN drops below the potential of the high-voltage domain floating ground VS. The seventh PMOS tube MP7 and the eighth PMOS tube MP8 are turned on to provide a path for the displacement current charging the first parasitic capacitor C1 and the second parasitic capacitor C2, thereby reducing the dV / dt noise signal amplitude at the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR. Since the two branches of the level shift module 220 are exactly the same, the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR are basically at the same potential at this time. This means that the gate and source of the first NMOS transistor MN1 and the gate and source of the second NMOS transistor MN2 are basically at the same potential, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off, there is no current in the voltage transient noise filtering module 240, the third PMOS transistor MP3, the fourth NMOS transistor MN4, the sixth PMOS transistor MP6, and the sixth NMOS transistor MN6 are all turned off, and the potential of the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR are pulled up to the high-voltage domain floating power supply VB by the seventh resistor R7 and the eighth resistor R8 until the +dV / dt ends.

[0082] After the positive transient noise +dV / dt ends, the second high-voltage domain narrow pulse signal VDR and the transient noise intensity signal VDN rise to the high-voltage domain floating power supply VB, the seventh PMOS tube MP7 and the eighth PMOS tube MP8 are turned off, the first high-voltage domain narrow pulse signal VDS remains unchanged, and the first high-voltage domain filter signal VOS drops to the high-voltage domain floating ground VS until the duration of the first low-voltage domain narrow pulse signal VINS ends. When the input signal VIN changes from a high level to a low level, the second low-voltage domain narrow pulse signal VINR corresponding to the falling edge changes to a high level, the second high-voltage domain narrow pulse signal VDR output by the level shift module 220 is pulled down to near the high-voltage domain floating ground VS potential, the second NMOS tube MN2 is turned on, and the second high-voltage domain filter signal VOR output by the voltage transient noise filtering module 240 is pulled down from the high-voltage domain floating power supply VB potential to the high-voltage domain floating ground VS potential through the current mirror structure composed of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 and the third current mirror structure composed of the fifth NMOS tube MN5 and the sixth NMOS tube MN6. The RS trigger is reset by the second high-voltage domain filter signal VOR and the output changes from the high-voltage domain floating power supply VB potential to the high-voltage domain floating ground VS potential. This signal drives the external half-bridge high-side power device of the chip to turn off, and the high-voltage domain floating power supply VB and the high-voltage domain floating ground VS potential drop rapidly. -dV / dt comes and continues until the high-voltage domain floating ground VS potential drops to the ground potential.

[0083] When negative transient noise -dV / dt comes, the first parasitic capacitor C1, the second parasitic capacitor C2, and the third parasitic capacitor C3 generate displacement currents that flow through the first resistor R1, the second resistor R2, and the fifth resistor R5 to discharge to the high-voltage domain floating power supply VB. The potential of the first high-voltage domain narrow pulse signal VDS and the potential of the transient noise intensity signal VDN will be clamped to below the high-voltage domain floating power supply VB+0.7V until -dV / dt ends, the potential of the second high-voltage domain narrow pulse signal VDR rises, the branch current where the second NMOS tube MN2 is located decreases, the on-resistance of the sixth NMOS tube MN6 increases slightly, and the potential of the second high-voltage domain filter signal VOR also rises slightly until -dV / dt ends.

[0084] As another example, Figure 5 As shown, the voltage transient noise filtering module 240 may include: a ninth PMOS transistor MP9, a seventh current mirror structure and a ninth NMOS transistor MN9.

[0085] The ninth PMOS transistor MP9 has a source connected to the high-voltage domain floating power supply VB, and a gate connected to the anode of the fifth diode D5, that is, the gate is connected to the output end of the transient noise intensity signal VDN.

[0086] The seventh current mirror structure includes a seventh NMOS tube MN7 and an eighth NMOS tube MN8. The sources of the two are connected to the high-voltage domain floating ground VS, and the gates are connected to the drain of the seventh NMOS tube MN7. The seventh NMOS tube MN7 and the ninth PMOS tube MP9 share a drain; the eighth NMOS tube MN8 and the second PMOS tube MP2 share a drain; The ninth NMOS transistor MN9 shares a drain with the fifth NMOS transistor MN5 and a gate with the seventh NMOS transistor MN7 , and a source thereof is connected to the high-voltage domain floating ground VS.

[0087] In this example, the high-voltage level shift circuit further includes: a seventh resistor R7 and an eighth resistor R8. The seventh resistor R7 is connected between the high-voltage domain floating power supply VB and the drain of the sixth NMOS transistor MN6. The eighth resistor R8 is connected between the high-voltage domain floating power supply VB and the drain of the fourth NMOS transistor MN4.

[0088] The working principle of the voltage transient noise filtering module 240 in this example is as follows: when there is no dV / dt noise, during the duration of the first low-voltage domain narrow pulse signal VINS corresponding to the rising edge of the input signal VIN, the first LDMOS tube M1 is turned on, and the first high-voltage domain narrow pulse signal VDS potential is pulled down to the vicinity of the high-voltage domain floating ground VS potential, while the second high-voltage domain narrow pulse signal VDR is maintained at the high-voltage domain floating power supply VB potential. The first NMOS tube MN1 is turned on, the second NMOS tube MN2 is turned off, and a current flows through the branch formed by the first PMOS tube MP1 and the first NMOS tube MN1. The first PMOS tube MP1 and the second PMOS tube MP2 form a current mirror structure, so a current flows through the branch formed by the second PMOS tube MP2 and the third NMOS tube MN3. The third NMOS tube MN3 and the fourth NMOS tube MN4 form a current mirror structure. The fourth NMOS tube MN4 is turned on. Since the PMOS tube and the sixth PMOS tube MP6 are turned off, the potential of the first high-voltage domain filter signal VOS is pulled down to the high-voltage domain floating ground VS potential; the first PMOS tube MP1 and the third PMOS tube MP3 form a current mirror structure. The third PMOS tube MP3 is turned on. Since the sixth NMOS tube MN6 is turned off, the potential of the second high-voltage domain filter signal VOR is pulled up to the high-voltage domain floating power supply VB potential.

[0089] During the duration of the second low-voltage domain narrow pulse signal VINR corresponding to the falling edge of the input signal VIN, based on the symmetrical circuit structure, the second high-voltage domain filter signal VOR is pulled down to the high-voltage domain floating ground VS potential, and the first high-voltage domain filter signal VOS is pulled up to the high-voltage domain floating power supply VB potential.

[0090] When a certain strength of positive transient noise +dV / dt comes, the transient noise intensity signal VDN, the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR are reduced at the same time. Since the two branches of the level shift module 220 are exactly the same, the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR are basically at the same potential at this time. This means that the gate and source of the first NMOS tube MN1 are at the same potential as the gate and source of the second NMOS tube MN2, the first NMOS tube MN1 and the second NMOS tube MN2 are turned off, there is no current in the voltage transient noise filtering module 240, the third PMOS tube MP3, the fourth NMOS tube MN4, the sixth PMOS tube MP6, and the sixth NMOS tube MN6 are all turned off; the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR are pulled up to the high-voltage domain floating power supply VB by the seventh resistor R7 and the eighth resistor R8 to achieve the purpose of filtering dV / dt noise.

[0091] Figure 6 for Figure 5 The waveform diagram corresponding to the medium and high voltage level shift circuit example. The working process of the high voltage level shift circuit in this example will be explained below in combination with the waveform diagram.

[0092] When the input signal VIN becomes high level, the first low voltage domain narrow pulse signal VINS corresponding to the rising edge becomes high level, and the level shift module 220 outputs the first high voltage domain narrow pulse signal VDS which is pulled down to the vicinity of the high voltage domain floating ground VS potential. The first NMOS tube MN1 is turned on, and the first high voltage domain filter signal VOS output by the voltage transient noise filtering module 240 is pulled down from the high voltage domain floating power supply VB potential to the high voltage domain floating ground VS potential through the first current mirror structure composed of the first PMOS tube MP1 and the second PMOS tube MP2 and the second current mirror structure composed of the third NMOS tube MN3 and the fourth NMOS tube MN4. The RS trigger is set by the first high voltage domain filter signal VOS and the output changes from the high voltage domain floating ground VS potential to the high voltage domain floating power supply VB potential. This signal drives the high side power device of the external half-bridge of the chip to turn on, and the high voltage domain floating power supply VB potential and the high voltage domain floating ground VS potential rise rapidly, and +dV / dt comes, which lasts until the high voltage domain floating ground VS potential rises to the chip external half-bridge bus voltage.

[0093] When the positive transient noise +dV / dt comes, the displacement current flows through the first resistor R1, the second resistor R2, and the fifth resistor R5 to charge the first parasitic capacitor C1, the second parasitic capacitor C2, and the third parasitic capacitor C3 respectively, and the potential of the first high-voltage domain narrow pulse signal VDS, the second high-voltage domain narrow pulse signal VDR, and the transient noise intensity signal VDN drops below the potential of the high-voltage domain floating ground VS. Since the two branches of the level shift module 220 are exactly the same, the first high-voltage domain narrow pulse signal VDS and the second high-voltage domain narrow pulse signal VDR are basically at the same potential at this time. This means that the gate and source of the first NMOS tube MN1 and the gate and source of the second NMOS tube MN2 are basically at the same potential. The first NMOS tube MN1 and the second NMOS tube MN2 are turned off, there is no current in the voltage transient noise filtering module 240, the third PMOS tube MP3, the fourth NMOS tube MN4, the sixth PMOS tube MP6, and the sixth NMOS tube MN6 are all turned off, and the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR are pulled up to the high-voltage domain floating power supply VB by the seventh resistor R7 and the eighth resistor R8. At the same time, because the seventh PMOS tube MP7 is turned on, the gate potentials of the fourth NMOS tube MN4 and the sixth NMOS tube MN6 are pulled down to the high-voltage domain floating ground VS through the current mirror structure formed by the seventh NMOS tube MN7, the eighth NMOS tube MN8, and the ninth NMOS tube MN9, ensuring that the first high-voltage domain filter signal VOS and the second high-voltage domain filter signal VOR will not be pulled down until the +dV / dt ends; After the positive transient noise +dV / dt ends, the potential of the second high-voltage domain narrow pulse signal VDR and the transient noise intensity signal VDN rises to the potential of the high-voltage domain floating power supply VB, the eighth NMOS tube MN8 and the ninth NMOS tube MN9 are turned off, the potential of the first high-voltage domain narrow pulse signal VDS remains unchanged, and the potential of the first high-voltage domain filter signal VOS drops to the potential of the high-voltage domain floating ground VS until the duration of the first low-voltage domain narrow pulse signal VINS ends. When the input signal VIN changes from a high level to a low level, the corresponding second low-voltage domain narrow pulse signal VINR at the falling edge changes to a high level, and the second high-voltage domain narrow pulse signal VDR output by the level shift module 220 is pulled down to near the potential of the high-voltage domain floating ground VS. The second NMOS tube MN2 is turned on, and the second high-voltage domain filter signal VOR output by the voltage transient noise filtering module 240 is pulled down from the high-voltage domain floating power supply VB potential to the high-voltage domain floating ground VS potential through the third current mirror structure composed of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 and the fourth current mirror structure composed of the fifth NMOS tube MN5 and the sixth NMOS tube MN6. The RS trigger is reset by the second high-voltage domain filter signal VOR and the output is changed from the high-voltage domain floating power supply VB potential to the high-voltage domain floating ground VS potential. The signal drives the external half-bridge high-side power device of the chip to turn off, and the high-voltage domain floating power supply VB and the high-voltage domain floating ground VS potential drop rapidly. -dV / dt arrives and continues until the high-voltage domain floating ground VS potential drops to the ground potential.

[0094] When negative transient noise -dV / dt comes, the first parasitic capacitor C1, the second parasitic capacitor C2, and the third parasitic capacitor C3 generate displacement current flowing through the first resistor R1, the second resistor R2, and the fifth resistor R5 to discharge to the high-voltage domain floating power supply VB, and the potential of the first high-voltage domain narrow pulse signal VDS and the transient noise intensity signal VDN will be clamped to below the high-voltage domain floating power supply VB+0.7V until -dV / dt ends, the potential of the second high-voltage domain narrow pulse signal VDR rises, the branch current where the second NMOS tube MN2 is located decreases, the on-resistance of the sixth NMOS tube MN6 increases slightly, and the potential of the second high-voltage domain filter signal VOR also rises slightly until -dV / dt ends.

[0095] In the embodiment of the present application, the high voltage level shift circuit 200 may be configured as follows: Receive input signal VIN. In response to the input signal VIN becoming a high level, generate a first low-voltage domain narrow pulse signal VINS corresponding to the rising edge of the input signal VIN, so as to generate a first high-voltage domain narrow pulse signal VDS and pull it down to the high-voltage domain floating ground VS potential interval; and generate a first high-voltage domain filter signal VOS and pull it down to the high-voltage domain floating ground VS potential, so as to output a high-side power device drive signal VOUT to drive the corresponding half-bridge high-side power device to turn on.

[0096] Among them, in response to the input signal VIN being at a high level and the positive transient noise +dV / dt being detected, a transient noise intensity signal VDN is generated and pulled down to the high-voltage domain floating ground VS potential interval; in response to detecting the end of the positive transient noise +dV / dt, the transient noise intensity signal VDN rises, and the first high-voltage domain filter signal VOS drops to the high-voltage domain floating ground VS potential until the duration of the first low-voltage domain narrow pulse signal VINS ends.

[0097] Furthermore, in response to the input signal VIN becoming a low level, a second low-voltage domain narrow pulse signal VINR is generated corresponding to the falling edge of the input signal VIN to generate a second high-voltage domain narrow pulse signal VDR and is pulled down to the high-voltage domain floating ground VS potential interval; and a second high-voltage domain filter signal VOR is generated and pulled down to the high-voltage domain floating ground VS potential, so that the high-side power device drive signal VOUT becomes the high-voltage domain floating ground VS potential to drive the half-bridge high-side power device to turn off.

[0098] Among them, in response to the input signal VIN becoming a low level and detecting a negative transient noise -dV / dt, the potential of the second high-voltage domain filter signal VOR rises from the high-voltage domain floating ground VS potential; in response to detecting the end of the negative transient noise -dV / dt, the potential of the second high-voltage domain filter signal VOR is pulled down to the high-voltage domain floating ground VS potential until the duration of the second low-voltage domain narrow pulse signal VINR ends.

[0099] Figure 7 FIG. 1 is a schematic diagram of a layout structure of a high voltage level shift circuit according to an embodiment of the present application. Figure 7 As shown, the layout structure of the high-voltage level shift circuit includes the high-voltage level shift circuit 300 in the above embodiment.

[0100] The high-voltage level shift circuit 300 includes a high-voltage domain 310 and a low-voltage domain 320 , wherein a high-voltage isolation structure 330 is provided around the high-voltage domain 310 to isolate and define the high-voltage domain 310 ; at least one of the first LDMOS transistor M1 , the second LDMOS transistor M2 and the third LDMOS transistor M3 is configured to be located in the high-voltage isolation structure 330 .

[0101] That is to say, any one, two or all of the first LDMOS tube M1, the second LDMOS tube M2 and the third LDMOS tube M3 can be arranged in the high-voltage isolation structure 330, and the present application does not impose specific restrictions on this. Preferably, the third LDMOS tube M3 in the voltage transient noise detection module 230 and the first LDMOS tube M1 and the second LDMOS tube M2 in the level shift module 220 are all located in the high-voltage isolation structure 330 in the layout, and the other devices in the voltage transient noise detection module 230 occupy a very small layout area compared to the third LDMOS tube M3, so the voltage transient noise detection module 230 proposed in the present invention hardly occupies additional layout area. Therefore, compared with the traditional RC filter circuit, the noise filtering circuit proposed in the present invention does not require a filter capacitor, can effectively reduce the layout area, and is easy to produce and manufacture.

[0102] In summary, according to the high-voltage level shifting circuit of the embodiment of the present application, an input signal is received through a pulse generating module, and a dual-path low-voltage domain narrow pulse signal corresponding to the rising edge and the falling edge of the input signal is generated, and sent to the level shifting module; and the dual-path low-voltage domain narrow pulse signal is received through the level shifting module, converted into a corresponding dual-path high-voltage domain narrow pulse signal, and sent to the voltage transient noise filtering module; and the voltage transient noise of the high-voltage level shifting circuit is detected through the voltage transient noise detection module, and a transient noise intensity signal VDN is generated, which is sent to the voltage transient noise filtering module; and the voltage transient noise filtering module performs voltage transient noise filtering on the dual-path high-voltage domain narrow pulse signal based on the received transient noise intensity signal VDN, generates a dual-path high-voltage domain filtered signal, and sends it to the RS trigger. Therefore, on the one hand, the voltage transient noise detection module is used to convert the noise voltage signal into a current compensation signal, and the auxiliary voltage transient noise filtering module is used to achieve dV / dt noise filtering, which can enhance the common mode noise filtering capability and the ability to resist VS negative bias of the voltage transient noise filtering module without increasing the transmission delay, and effectively reduce the chip transmission delay. On the other hand, the voltage transient noise detection module and the voltage transient noise filtering module are used to replace the RC filter circuit in the related technology, and the narrow pulse signal width is basically not lost during the transmission process while ensuring the noise filtering effect. Therefore, the narrow pulse signal width can be reduced while ensuring the chip's ability to resist dV / dt noise, and the LDMOS device turn-on time can be reduced, thereby effectively reducing the chip power consumption.

[0103] It should be noted that in the drawings, the sizes of layers, regions, components and their relative sizes may be exaggerated for clarity. The same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions.

[0104] Those skilled in the art can understand that the above are only preferred embodiments of the present application and are not intended to limit the present application. Although the present application is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A high voltage level shift circuit, characterized in that: include: The pulse generating module is configured to receive an input signal, generate a dual-path low-voltage domain narrow pulse signal corresponding to the rising edge and the falling edge of the input signal, and send the signals to the level shifting module; The level shift module is configured to convert the received dual-channel low-voltage domain narrow pulse signal into a corresponding dual-channel high-voltage domain narrow pulse signal, and send it to the voltage transient noise filtering module; A voltage transient noise detection module is configured to detect voltage transient noise of the high-voltage level shift circuit, generate a transient noise intensity signal, and send it to the voltage transient noise filtering module; A voltage transient noise filtering module is configured to perform voltage transient noise filtering on the dual-channel high-voltage domain narrow pulse signal based on the received transient noise intensity signal, generate a dual-channel high-voltage domain filtered signal, and send it to the RS trigger; The RS trigger is configured to convert the received dual-path high-voltage domain filter signal into a high-side power device drive signal.

2. The high voltage level shift circuit according to claim 1, characterized in that: The level shift module comprises: a first resistor, a second resistor, a third resistor, and a fourth resistor; a first diode, wherein the positive electrode is connected to the high-voltage domain floating ground, and the negative electrode is connected to the high-voltage domain floating power supply through the first resistor; a second diode, with an anode connected to the high-voltage domain floating ground and a cathode connected to the high-voltage domain floating power supply through the second resistor; A third diode, whose anode is connected to the cathode of the first diode and connected to the first high-voltage domain narrow pulse signal output terminal of the level shift module, and whose cathode is connected to the high-voltage domain floating power supply; a fourth diode, wherein the anode is connected to the cathode of the second diode and is connected to the second high-voltage domain narrow pulse signal output terminal of the level shift module, and the cathode is connected to the high-voltage domain floating power supply; A first LDMOS tube, whose gate is used to input a first low-voltage domain narrow pulse signal, whose drain is connected to the first high-voltage domain narrow pulse signal output terminal through the third resistor, and whose source is grounded; The second LDMOS tube has a gate for inputting a second low-voltage domain narrow pulse signal, a drain connected to the second high-voltage domain narrow pulse signal output terminal through the fourth resistor, and a source grounded.

3. The high voltage level shift circuit according to claim 2, characterized in that: The voltage transient noise detection module comprises: a fifth resistor and a sixth resistor; a fifth diode, connected in parallel with the fifth resistor, with a cathode connected to the high-voltage domain floating power supply and a positive electrode connected to the transient noise intensity signal output terminal; a sixth diode, an anode of which is connected to the floating ground of the high-voltage domain, and a cathode of which is connected to the anode of the fifth diode; The gate and source of the third LDMOS tube are grounded, and the drain is connected to the anode of the fifth diode through the sixth resistor.

4. The high voltage level shift circuit according to claim 3, characterized in that: The high voltage level shift circuit satisfies at least one of the following conditions: The resistance values ​​of the first resistor, the second resistor and the fifth resistor are equal; The resistance values ​​of the third resistor, the fourth resistor and the sixth resistor are equal; The first diode, the second diode and the sixth diode have the same size; The third diode, the fourth diode and the fifth diode have the same size; The first LDMOS transistor, the second LDMOS transistor and the third LDMOS transistor have the same size.

5. The high voltage level shift circuit according to claim 3, characterized in that: The voltage transient noise filtering module comprises: A first current mirror structure includes a first PMOS tube and a second PMOS tube, wherein the source electrodes of the first PMOS tube and the gate electrodes of the second PMOS tube are connected to the high-voltage domain floating power supply, and the gate electrodes of the first PMOS tube and the drain electrodes of the second PMOS tube are connected to the high-voltage domain floating power supply. A second current mirror structure includes the first PMOS tube and a third PMOS tube, wherein a source of the third PMOS tube is connected to the high-voltage domain floating power supply; A first NMOS tube, sharing a drain with the first PMOS tube; a source of the first NMOS tube connected to the anode of the third diode, and a gate connected to the anode of the fourth diode; A third current mirror structure includes a fourth PMOS tube and a fifth PMOS tube, wherein the source electrodes of the fourth PMOS tube and the fifth PMOS tube are connected to the high-voltage domain floating power supply, and the gate electrodes are connected to the drain electrode of the fourth PMOS tube; a fourth current mirror structure, comprising the fourth PMOS tube and a sixth PMOS tube, wherein a source of the sixth PMOS tube is connected to the high-voltage domain floating power supply; A second NMOS tube shares a drain with the first PMOS tube; a source of the second NMOS tube is connected to the anode of the third diode, and a gate is connected to the source of the first NMOS tube; A fifth current mirror structure comprises a third NMOS tube and a fourth NMOS tube, wherein the sources of the third NMOS tube and the fourth NMOS tube are connected to the floating ground of the high voltage domain, and the gates are connected to the drain of the third NMOS tube; the third NMOS tube and the second PMOS tube share a drain; and the fourth NMOS tube and the sixth PMOS tube share a drain; The sixth current mirror structure includes a fifth NMOS tube and a sixth NMOS tube, the sources of which are connected to the floating ground of the high-voltage domain, and the gates are connected to the drain of the fifth NMOS tube; the fifth NMOS tube and the fifth PMOS tube share a drain; the sixth NMOS tube and the third PMOS tube share a drain.

6. The high voltage level shift circuit according to claim 5, characterized in that: The voltage transient noise filtering module also includes: The seventh PMOS tube and the eighth PMOS tube share a common gate and source, the source is connected to the high-voltage domain floating power supply, and the gate is connected to the anode of the fifth diode; the drain of the seventh PMOS tube is connected to the gate of the first NMOS tube; the drain of the eighth PMOS tube is connected to the gate of the second NMOS tube.

7. The high voltage level shift circuit according to claim 5, characterized in that: The voltage transient noise filtering module also includes: a ninth PMOS tube, wherein the source electrode is connected to the high-voltage domain floating power supply, and the gate electrode is connected to the anode of the fifth diode; a seventh current mirror structure, comprising a seventh NMOS tube and an eighth NMOS tube, wherein the sources of the seventh NMOS tube and the eighth NMOS tube are connected to the floating ground of the high voltage domain, and the gates are connected to the drain of the seventh NMOS tube; the seventh NMOS tube and the ninth PMOS tube share a drain; and the eighth NMOS tube and the second PMOS tube share a drain; The ninth NMOS tube shares a drain with the fifth NMOS tube, shares a gate with the seventh NMOS tube, and has a source connected to the high-voltage domain floating ground.

8. The high voltage level shift circuit according to claim 5, characterized in that: The high voltage level shift circuit further comprises: a seventh resistor, connected between the high-voltage domain floating power supply and the drain of the sixth NMOS tube; An eighth resistor is connected between the high-voltage domain floating power supply and the drain of the fourth NMOS tube.

9. The high voltage level shift circuit according to any one of claims 1 to 8, characterized in that: The high voltage level shift circuit is configured as: receiving an input signal; In response to the input signal becoming a high level, a first low-voltage domain narrow pulse signal corresponding to the rising edge of the input signal is generated to generate a first high-voltage domain narrow pulse signal and pull it down to the high-voltage domain floating ground potential interval; and a first high-voltage domain filter signal is generated and pulled down to the high-voltage domain floating ground potential, so that a high-side power device drive signal is output to drive the corresponding half-bridge high-side power device to turn on; Wherein, in response to the input signal being at a high level and positive transient noise being detected, a transient noise intensity signal is generated and pulled down to the high-voltage domain floating ground VS potential interval; in response to detecting the end of the positive transient noise, the transient noise intensity signal rises, and the first high-voltage domain filter signal drops to the high-voltage domain floating ground potential until the duration of the first low-voltage domain narrow pulse signal ends; In response to the input signal becoming a low level, a second low-voltage domain narrow pulse signal corresponding to the falling edge of the input signal is generated to generate a second high-voltage domain narrow pulse signal and is pulled down to the high-voltage domain floating ground potential interval; and a second high-voltage domain filter signal is generated and is pulled down to the high-voltage domain floating ground potential, so that the high-side power device drive signal becomes the high-voltage domain floating ground potential, so as to drive the half-bridge high-side power device to turn off; In which, in response to the input signal becoming a low level and detecting negative transient noise, the potential of the second high-voltage domain filter signal rises from the high-voltage domain floating ground potential; in response to detecting the end of the negative transient noise, the potential of the second high-voltage domain filter signal is pulled down to the high-voltage domain floating ground potential until the duration of the second low-voltage domain narrow pulse signal ends.

10. A layout structure of a high voltage level shift circuit, characterized in that: A high voltage level shift circuit comprising any one of claims 4 to 8; The high-voltage level shift circuit includes a high-voltage domain and a low-voltage domain, wherein a high-voltage isolation structure is provided on the periphery of the high-voltage domain to isolate and define the high-voltage domain; at least one of the first LDMOS tube, the second LDMOS tube and the third LDMOS tube is configured to be located in the high-voltage isolation structure.

Images