Storage unit, memory, data reading method, data erasing method and electronic equipment
By using vertical structure transistors and erasing units in the DRAM memory cell, the problems of complex signal line structure and floating body effect in the prior art are solved, and a simpler process flow and higher storage density are achieved.
Patent Information
- Application Number
- CN202411535076.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-14
AI Technical Summary
The DRAM composed of the existing 2T0C memory cells has a complex signal line structure and process flow, and there is a floating body effect that causes transistor failure.
A new memory cell architecture is designed, using a vertical structure of write transistors and read transistors, and an erasing unit is provided on the side wall of the write channel structure, located on the side of the write gate structure near the second source and drain region.
The signal line structure and process flow are simplified, the data erasing speed is improved, the floating body effect is reduced, and the overall performance and storage density of the device are improved.
Smart Images
Figure CN119446232A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a storage unit, a memory, a data reading method, an erasing method, and an electronic device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory used in computers and other electronic devices to store data that needs to be accessed quickly. Compared with static random access memory, it has the advantages of simple structure, low manufacturing cost and high storage density, and is an important component of modern computing systems.
[0003] At present, the storage unit of common DRAM memory is a structure of one transistor connected to one capacitor, namely, a 1T1C (1Transistor 1Capacitor) storage unit structure. This structure requires constant refreshing of the charge in the capacitor to ensure that data is not lost. It consumes a lot of power, and the manufacturing process of the capacitor occupies a large area, which limits the miniaturization of the device size.
[0004] In order to overcome the drawbacks of 1T0C memory cells, the two-transistor capacitorless dynamic random access memory (2Transistor0Capacitor, 2T0C) uses two transistors as the memory cell structure, in which the source and drain of the write transistor are connected to the gate of the read transistor, and the gate is used to store charge to change the transistor transconductance to store information. In the existing DRAM composed of 2T0C memory cells, the word line of the write transistor is extended vertically, and the projections of the word line and bit line of the read transistor on the substrate intersect. The step structure in two directions is designed to lead out the word line and bit line of the write transistor and the word line and bit line of the read transistor at different layers, and the process flow is relatively complicated. In addition, the existing DRAM composed of 2T0C memory cells also has a floating body effect, which may cause transistor failure.
[0005] Therefore, it is necessary to design a DRAM with a new 2T0C storage cell architecture, design a signal line structure and a signal line lead-out structure with a simpler manufacturing process, and at the same time improve or reduce the floating body effect.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In view of this, a storage unit, a memory, a data reading method, an erasing method, and an electronic device are provided. The storage unit is provided with an erasing unit, which can increase the data erasing speed of the device, reduce the floating body effect, and thus improve the overall performance of the device.
[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.
[0009] According to one aspect of the present disclosure, there is provided a memory cell formed above a substrate, the memory cell comprising:
[0010] A write transistor and a read transistor, wherein both the write transistor and the read transistor are vertical structure transistors, and the write transistor is located above the read transistor;
[0011] The write transistor includes a write channel structure, a write gate structure surrounding a portion of the sidewall of the write channel structure, and a write gate dielectric structure located between the write gate structure and the write channel structure, wherein the write channel structure extends along a first direction and includes a first source and drain region, a write channel region, and a second source and drain region; the first direction is perpendicular to the plane of the substrate;
[0012] The read transistor includes a read gate structure extending along the first direction, a read channel structure surrounding a sidewall and an end of the read gate structure, and a read gate dielectric structure located between the read gate structure and the read channel structure, wherein the read channel structure includes a third source and drain region, a read channel region, and a fourth source and drain region;
[0013] The second source and drain region is conductively connected to the read gate structure, and a projection of the write channel structure on the substrate overlaps with a projection of the read gate structure on the substrate;
[0014] An erasing unit is coated on a portion of the sidewall of the write channel structure, and the erasing unit is located on a side of the write gate structure close to the second source and drain region.
[0015] In an exemplary embodiment of the present disclosure, the write gate dielectric structure conformally covers the surface of the write gate structure.
[0016] In an exemplary embodiment of the present disclosure, the write channel structure includes a sleeve and a filling body, the sleeve conformally covers the sidewalls and lower end surface of the filling body, and the upper surface of the sleeve is not lower than the upper surface of the filling body; the sleeve is in contact with the write gate dielectric structure.
[0017] In an exemplary embodiment of the present disclosure, the material of the sleeve includes indium gallium zinc oxide, and the material of the filler includes indium zinc oxide.
[0018] In an exemplary embodiment of the present disclosure, the material of the read gate structure includes indium zinc oxide, and the material of the read channel structure is indium gallium zinc oxide.
[0019] In an exemplary embodiment of the present disclosure, the second source and drain region are conductively connected to the read gate structure through a first conductive block, the lower end surface of the first conductive block is in contact with the upper end surface of the read gate structure, and the upper end surface of the first conductive block is in contact with the second source and drain region; the first conductive block is insulated from the read channel structure.
[0020] According to another aspect of the present disclosure, a memory is provided, formed on a substrate, the memory comprising:
[0021] A plurality of the above-mentioned storage units, wherein the plurality of the storage units form an array structure along a second direction and a third direction, wherein the second direction and the third direction intersect and are both parallel to the substrate;
[0022] a plurality of write word lines extending along the second direction and arranged at intervals along the third direction, each of the write word lines being in contact and connected with the gate structures of a row of the write transistors arranged at intervals along the second direction;
[0023] a plurality of write bit lines extending along the third direction and arranged at intervals along the second direction, each of the write bit lines being electrically connected to the first source and drain regions of a row of the write transistors arranged at intervals along the third direction;
[0024] a plurality of first read signal lines extending along the second direction and arranged at intervals along the third direction, each of the first read signal lines being in contact and connected with the third source and drain regions of a row of the read transistors arranged at intervals along the second direction;
[0025] a plurality of second read signal lines extending along the second direction and arranged at intervals along the third direction, each of the second read signal lines being in contact and connected with the fourth source and drain regions of a row of the read transistors arranged at intervals along the second direction;
[0026] A plurality of erasing lines extending along the second direction and arranged at intervals along the third direction, each of the erasing lines being formed by connecting a row of the erasing units arranged along the second direction end to end.
[0027] In an exemplary embodiment of the present disclosure, the write word line and the gate structure are made of the same material, and the write word line and the gate structure are integrally formed.
[0028] In an exemplary embodiment of the present disclosure, a second conductive block and a first connecting line are sequentially disposed on each of the first source and drain regions, the first connecting line extends along the first direction, two adjacent first connecting lines are insulated from each other, and two adjacent second conductive blocks are insulated from each other;
[0029] The lower end surface of the second conductive block contacts the first source and drain region, the upper end surface of the second conductive block contacts the lower end surface of the first connecting line, and the upper end surface of the first connecting line contacts the write bit line, thereby realizing electrical connection between the write bit line and the first source and drain region.
[0030] In an exemplary embodiment of the present disclosure, in a direction along the first direction and away from the substrate, the lengths of the second read signal line, the first read signal line, the erase line and the write word line decrease or increase in sequence.
[0031] In an exemplary embodiment of the present disclosure, the second read signal line, the first read signal line, the erase line and the write line all include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the first direction, the main extension portions of any two of the second read signal line, the first read signal line, the erase line and the write line overlap in their orthographic projections on the substrate, and the lead-out end portions of any two of the second read signal line, the first read signal line, the erase line and the write line do not overlap in their orthographic projections on the substrate.
[0032] In an exemplary embodiment of the present disclosure, the memory further includes a plurality of second connection lines, which extend along the first direction and are in contact with and connected to the lead-out end portions.
[0033] According to another aspect of the present disclosure, a method for reading data from a memory is provided, which is applied to the above-mentioned memory, and the reading method includes:
[0034] Determine an access memory cell from which data needs to be read, and a selected write word line, a selected read first signal line, and a selected read second signal line connected to the access memory cell, and determine all non-access memory cells connected to the selected write word line;
[0035] Turning on the write transistor in the non-access memory cell to erase data stored in a storage node in the non-access memory cell;
[0036] All the write transistors in the memory are controlled to remain in a closed state, a read voltage is applied through one of the selected read first signal line and the selected read second signal line, and data stored in a storage node in the access storage unit is read from the other of the selected read first signal line and the selected read second signal line.
[0037] In an exemplary embodiment of the present disclosure, after reading the data stored in the storage node in the access storage unit, the method further includes:
[0038] Turning on the write transistor in the access memory cell to erase the data stored in the storage node in the access memory cell;
[0039] Data are rewritten to a row of the memory cells connected to the selected write word line.
[0040] According to another aspect of the present disclosure, a method for erasing data of a memory is provided, which is applied to the above-mentioned memory, and the erasing method includes:
[0041] Determine a selected block where data needs to be erased, wherein the selected block includes a row of the storage cells arranged at intervals along the second direction, and a selected write word line, a selected erase line, a selected read first signal line, and a selected second signal line connected to the row of the storage cells arranged at intervals along the second direction;
[0042] The data in each storage node in all the storage units in the selected block are erased through the selected erase line.
[0043] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned memory.
[0044] The memory cell provided by the present disclosure includes a read transistor and a write transistor, both of which are vertical structure transistors, wherein the second source and drain region of the write transistor is conductively connected to the gate structure of the read transistor; the memory cell also includes an erase unit, the write-erase unit is coated on a part of the side wall of the write channel structure, and the erase unit is located on a side of the write gate structure close to the second source and drain region, by arranging the erase unit on the side wall of the write channel structure of the write transistor of the memory cell, the data in the storage node in the memory cell can be erased, thereby improving the erasing speed of the data in the storage node in the memory cell; in addition, by arranging the erase unit on one side of the write gate structure, the floating body effect can be reduced, thereby improving the functionality of the device;
[0045] The memory provided by the present disclosure includes a plurality of the above-mentioned memory cells, the gate structures of the write transistors of each memory cell are electrically connected through a write word line, the first source and drain regions of the write transistors of each memory cell are electrically connected through a write bit line, the third source and drain regions of the read transistors of each memory cell are connected through a read first signal line, the fourth source and drain regions of the read transistors of each memory cell are connected through a read second signal line, and the erase units of each memory cell are connected end to end as an erase line. By forming an erase line in the memory, in conjunction with a write bit line, a write word line, a read first signal line and a read second signal line, data of each storage node in a plurality of memory cells in the memory can be erased, thereby improving the data erasing speed and thus improving the overall functionality of the device. In addition, the memory cell structure in the memory is compact, thereby improving the storage density of the device; moreover, the write word line, the read first signal line and the read second signal line are all arranged to extend laterally, so that a step-shaped lead-out structure can be formed in one direction to lead out four signal lines in different layers, thereby simplifying the preparation process flow;
[0046] The data reading method provided by the present disclosure is applied to the above-mentioned memory. After determining the required access storage unit, the data in the non-access storage unit is first erased, and then the data in the access unit is read. This can realize the reading of data in a single storage unit, and improve the data reading speed of a single storage unit.
[0047] The data erasing method provided by the present disclosure is applied to the above-mentioned memory, and can erase the data in each storage node in all storage cells in the selected block through the erase line, thereby improving the data erasing speed and further improving the overall function of the device.
[0048] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0050] Figure 1 It is a schematic diagram of the structure of a storage unit in an exemplary embodiment of the present disclosure.
[0051] Figure 2 It is a cross-sectional view of a memory in an exemplary embodiment of the present disclosure.
[0052] Figure 3 It is a schematic diagram of the three-dimensional structure of a memory in an exemplary embodiment of the present disclosure.
[0053] Figure 4 The figure is a schematic diagram of a circuit structure of a memory in an exemplary embodiment of the present disclosure.
[0054] The reference numerals are described as follows:
[0055] 10. Storage cell; 100. Write transistor; 110. Write gate structure; 120. Write gate dielectric structure; 130. Write channel structure; 131. Sleeve; 132. Filler; 101. First source and drain region; 102. Second source and drain region; 103. Write channel region; 200. Read transistor; 210. Read gate structure; 220. Read gate dielectric structure; 230. Read channel structure; 201. Third source and drain region; 202. Fourth source and drain region; 203. Read channel region; 300. Erase unit; 401. First conductive block; 402. Second conductive block; 501. First connection line; 502. Second connection line; 600. Substrate; 700. Blocking layer; BL, erase line; WWL, write word line; WBL, write bit line; RL1, first signal line; RL2, second signal line; X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION
[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0057] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
[0058] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.
[0059] In the related art, a two-transistor capacitor-free dynamic random access memory (2T0C) uses two transistors as a storage unit structure, wherein a source and drain of one transistor are connected to the gate of another transistor, and the gate of one of the transistors is used to replace the capacitor in the 1T0C structure to store charge. This can change the problem of low device storage density caused by the manufacturing process limitations of the capacitor, and can also change the transistor transconductance to store information.
[0060] A memory with a 2T0C storage cell structure can increase storage density by continuously increasing the number of stacking layers. However, as the number of stacking layers increases, higher requirements are placed on the manufacturing process of the device, and the data reading, writing and erasing speeds in each storage node in each storage cell in 2T0C are also affected.
[0061] Based on this, the present disclosure provides a storage unit formed above a substrate, such as Figure 1 As shown, the memory cell 10 includes: a read transistor 200 , a write transistor 100 and an erase unit 300 .
[0062] Wherein, the write transistor 100 and the read transistor 200 are both vertical structure transistors, and the write transistor 100 is located above the read transistor 200; the write transistor 100 includes a write channel structure 130, a write gate structure 110 surrounding a portion of the sidewall of the write channel structure 130, and a write gate dielectric structure 120 located between the write gate structure 110 and the write channel structure 130, the write channel structure 130 extends along a first direction X, and the write channel structure 130 includes a first source and drain region 101, a write channel region 103 and a second source and drain region 102; the first direction X is perpendicular to the plane of the substrate; the read transistor 200 includes a read gate structure 21 extending along the first direction X 0, a read channel structure 230 that surrounds the sidewall and one end of the read gate structure 210, and a read gate dielectric structure 220 located between the read gate structure 210 and the read channel structure 230, the read channel structure 230 includes a third source and drain region 201, a read channel region 203 and a fourth source and drain region 202; the second source and drain region 102 is conductively connected to the read gate structure 210, and the projection of the write channel structure 130 on the substrate 600 overlaps with the projection of the read gate structure 210 on the substrate 600; the erase unit 300 is coated on a portion of the sidewall of the write channel structure 130, and the erase unit 300 is located on a side of the write gate structure 110 close to the second source and drain region 102.
[0063] The storage cell 10 provided in the present disclosure includes a read transistor 200 and a write transistor 100, both of which are vertical structure transistors, wherein the second source and drain region 102 of the write transistor 100 is conductively connected to the gate structure of the read transistor 200; the storage cell 10 also includes an erase unit 300, the write-erase unit 300 is coated on a portion of the side wall of the write channel structure 130, and the erase unit 300 is located on a side of the write gate structure 110 close to the second source and drain region 102. By arranging the erase unit 300 on the side wall of the write channel structure 130 of the write transistor 100 of the storage cell 10, the data in the storage node in the storage cell 10 can be erased, thereby improving the erasing speed of the data in the storage node in the storage cell 10; in addition, by arranging the erase unit 300 on one side of the write gate structure 110, the floating body effect can also be reduced, thereby improving the functionality of the device.
[0064] The structure of the storage unit provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings:
[0065] In the embodiments provided in the present disclosure, the substrate may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a germanium silicon (Ge Si) substrate, SOI (Silicon On Insulator), SOS (Silicon-on-Sapphire) or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP) or gallium arsenide (GaAs). The embodiments provided in the present disclosure are described by taking the substrate as a silicon (Si) substrate as an example. Of course, for other types of substrates, corresponding deformations or improvements can be made to the embodiments of the present disclosure, all of which are within the protection scope of the present disclosure.
[0066] In the embodiment provided in the present disclosure, the memory cell 10 includes a read transistor 200, which is formed above the substrate 600. The read transistor 200 is used to transfer the data information in the memory cell 10 to the external circuit during the data reading operation. The read transistor 200 is a vertical structure transistor, and the read transistor 200 includes a read gate structure 210, a read channel structure 230, and a read gate dielectric structure 220, wherein the read gate structure 210 extends along a first direction X, the read channel structure 230 surrounds the sidewall and one end of the read gate structure 210, and the read gate dielectric structure 220 is located between the read gate structure 210 and the read channel structure 230. In the present disclosure, the first direction X is perpendicular to the substrate ( Figure 1 The direction of the plane (not shown).
[0067] The read gate structure 210 may be made of polysilicon, metal or metal alloy material, for example, the metal material may be tungsten, copper, etc., and the metal alloy material may be indium zinc oxide (IZO). In the present disclosure, in order to improve the on- and off-capacity of the source and drain of the read transistor 200 in the memory cell 10 and improve the performance of the device, the read gate structure 210 may be made of indium zinc oxide (IZO), which has good electrical and optical properties. Using it as the read gate structure 210 can improve the conductivity of the gate, thereby improving the overall performance of the read transistor 200.
[0068] The read gate structure 210 can be formed by physical vapor deposition (PVD), such as sputtering deposition, evaporation deposition, etc.; or chemical vapor deposition (CVD), such as atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), etc. The specific formation process can be adaptively selected according to the design requirements and structural requirements of the storage unit 10.
[0069] The read channel structure 230 is formed of materials such as silicon, germanium, silicon carbide, gallium nitride, zinc oxide or indium oxide. In the present disclosure, in order to reduce the leakage current in the transistor and reduce power consumption, the read channel structure 230 can be made of indium gallium zinc oxide (IGZO), which has a lower leakage current when the transistor is off, which can reduce the overall power consumption of the device, and it also has a higher electron mobility, which can improve the switching speed of the read transistor 200, thereby improving the response speed of the device.
[0070] The read channel structure 230 can be formed by a PVD method, such as Sputtering, or a CVD method, such as an ALD method, a PECVD method, etc. The specific formation process can be adaptively selected according to the design requirements and structural requirements of the storage unit 10.
[0071] The read channel structure 230 includes a third source and drain region 201, a read channel region 203 and a fourth source and drain region 202 which are arranged in sequence along the first direction X and close to the substrate 600, that is, the third source and drain region 201 and the fourth source and drain region 202 are respectively located at two ends of the read channel region 203, wherein the read channel region 203 is a channel for carriers to flow between the third source and drain region 201 and the fourth source and drain region 202.
[0072] Among them, the appearance of the read gate dielectric structure 220 and the read channel structure 230 can be the same or substantially the same, and the two are sequentially coated on the sidewall and one end of the read gate structure 210. The read gate dielectric structure 220 can be made of a material with electrical isolation, such as silicon dioxide, silicon nitride or aluminum oxide. In the present disclosure, in order to improve the electrical isolation performance of the read gate dielectric structure 220 and ensure its effective control over the read gate structure 210 and the read channel structure 230, the read gate dielectric structure 220 can be made of a high dielectric constant material, such as hafnium oxide, hafnium silicon oxide, zirconium oxide and other materials, which can reduce the operating voltage, increase the operating current, and thereby improve the overall performance of the read transistor 200.
[0073] In the embodiment provided by the present disclosure, the storage unit 10 includes a write transistor 100, and the write transistor 100 is located above the read transistor 200, wherein the above of the read transistor 200 refers to the side thereof away from the substrate 600, and the write transistor 100 is used as a switch to control access to the gate capacitor, allowing data to be read or written. The write transistor 100 is a vertical structure transistor, and the write transistor 100 includes a write gate structure 110, a write channel structure 130, and a write gate dielectric structure 120, wherein the write channel structure 130 extends along a first direction X, the write gate structure 110 surrounds part of the sidewall of the write channel structure 130, the write gate dielectric structure 120 is located between the write gate structure 110 and the write channel structure 130, and the write gate dielectric structure is conformally coated on the surface of the write gate structure 110.
[0074] The write channel structure 130 includes a sleeve 131 and a filling body 132 . The sleeve 131 conformally covers the sidewalls and lower end surface of the filling body 132 . The upper surface of the sleeve 131 is not lower than the upper surface of the filling body 132 . The sleeve 131 contacts the write gate dielectric structure 120 .
[0075] The sidewall of the sleeve 131 extends along the first direction X, and one end of the sleeve 131 close to the substrate 600 is a closed structure, that is, the sleeve 131 is in a U-shape or a quasi-U-shape structure. The sleeve 131 serves as a channel layer in the write transistor 100 and can provide an electron flow channel between the source and the drain of the write transistor 100. The sleeve 131 can be made of IGZO. Since IGZO has high mobility, uniformity and stability, it can improve the switching speed and performance stability of the write transistor 100, reduce the leakage current of the transistor, and improve the information retention time of the storage node.
[0076] The filler 132 can be made of IZO. Since IZO has high transparency and good conductivity, filling IZO in the sleeve 131 is conducive to the transmission of electrons and can provide an effective conduction path for the carriers in the write channel structure 130. In addition, the filler 132 and the sleeve 131 together constitute the write channel structure 130. Due to the high mobility characteristics of IGZO itself and the good conductivity of IZO, the overall mobility of the carriers in the channel can be improved, the uniformity of the electrical performance of the channel structure can be improved, and the performance stability of the transistor can be enhanced. The method of forming the sleeve 131 and the filler 132 is the same or similar to the method of forming the read channel structure 230 of the read transistor 200, and will not be repeated here.
[0077] The write channel structure 130 includes a first source and drain region 101, a write channel region 103, and a second source and drain region 102, which are arranged in sequence along the first direction X and close to the substrate 600, that is, the first source and drain region 101 and the second source and drain region 102 are respectively located at two ends of the write channel region 103, wherein the write channel region 103 is a channel for carriers to flow between the first source and drain region 101 and the second source and drain region 102.
[0078] The write gate structure 110 surrounds part of the sidewall of the write channel structure 130, and the write gate structure 110 extends along the second direction Y, wherein the second direction Y is perpendicular to the first direction X and parallel to the surface of the substrate 600. This arrangement of the write gate structure 110 can improve the density of subsequent devices and increase the degree of integration of the devices. The write gate structure 110 can be made of metal materials, such as tungsten, copper, aluminum, molybdenum or tantalum, etc., and can be formed by PVD methods, such as Sputtering, Evaporation, etc.; or CVD methods, such as ALD, Metal-Organic Chemical Vapor Deposition (Metal-Organic Chemical Vapor Deposition, MOCVD), etc., and an appropriate formation process method can be selected according to the specific material of the write gate structure 110. The write gate structure 110 is formed of metal materials, which can reduce its resistance value and improve its conductivity.
[0079] The write gate dielectric structure 120 is located between the write gate structure 110 and the write channel structure 130, and the write gate dielectric structure 120 surrounds the write gate structure 110. The write gate dielectric structure 120 can be a film layer that conformally surrounds the outer surface of the write gate structure 110. The write gate dielectric structure 120 is used to isolate the write gate structure 110 and the write channel structure 130. The write gate dielectric structure 120 can be made of a material with electrical isolation, such as silicon dioxide, silicon nitride or aluminum oxide. In the present disclosure, in order to improve the electrical isolation performance of the write gate dielectric structure 120 and ensure its effective isolation of the write gate structure 110 and the write channel structure 130, the write gate dielectric structure 120 can use a high dielectric constant material, such as hafnium oxide, hafnium silicon oxide, zirconium oxide, etc., which can reduce the operating voltage, increase the operating current, and thus improve the overall performance of the write transistor 100.
[0080] In the embodiment provided in the present disclosure, within the memory cell 10, the write transistor 100 is electrically connected to the read transistor 200. Specifically, the second source and drain region 102 of the write transistor 100 is conductively connected to the read gate structure 210 of the read transistor 200, and the projection of the write channel structure 130 on the substrate 600 overlaps with the projection of the read gate structure 210 on the substrate 600, so as to improve the miniaturization and structural compactness of the memory cell 10.
[0081] The second source-drain region 102 and the read gate structure 210 are electrically connected through the first conductive block 401, the lower end surface of the first conductive block 401 is in contact with the upper end surface of the read gate structure 210, and the upper end surface of the first conductive block 401 is in contact with the second source-drain region 102. The first conductive block 401 is a conductive bridge connecting the write transistor 100 and the read transistor 200, and can be made of a material with conductive properties. However, since the lower end surface of the first conductive block 401 is in contact with the upper end surface of the read gate structure 210, in order to form a better transition between the first conductive block 401 and the read gate structure 210 and ensure that it does not affect the functionality of the upper end surface of the read gate structure 210, the first conductive block 401 can be made of polysilicon (poly), and the device size is small and the local electrical interconnection with low current density can achieve compatibility of processability and performance.
[0082] The first conductive block 401 is insulated from the read channel structure 230 to prevent the first conductive block 401 from affecting the normal function of the read channel structure 230. The first conductive block 401 and the read channel structure 230 may be insulated by the read gate dielectric structure 220, or an insulating layer may be provided between the first conductive block 401 and the read channel structure 230, such as an insulating layer formed of a material such as silicon oxide, to isolate the first conductive block 401 from the read channel structure 230.
[0083] In the embodiment provided by the present disclosure, the storage unit 10 further includes an erasing unit 300, the erasing unit 300 is coated on a part of the sidewall of the write channel structure 130, the erasing unit 300 is located on the side of the write gate structure 110 close to the second source and drain region 102, the erasing unit 300 extends along the second direction Y, and the erasing unit 300 can be arranged parallel to the write gate structure 110. Among them, the erasing unit 300 can be made of a conductive material, such as a metal material, such as tungsten, copper, aluminum, etc. By arranging the erasing unit 300 in the storage unit 10, on the first hand, when processing data, the electrons in the read transistor 200 or the write transistor 100 can be cleared by the erasing unit 300 to clear the data in the storage unit 10; on the second hand, since the erasing unit 300 is arranged inside the storage unit 10, when erasing data, data can be erased by selecting a specific storage unit 10, thereby improving the data erasing speed; on the third hand, by arranging the erasing unit 300 in the storage unit 10, the floating body effect can be effectively reduced and the performance of the device can be improved.
[0084] The present disclosure provides a memory device formed on a substrate, such as Figure 2 and Figure 3 As shown, combined Figure 1 and Figure 4 The memory includes: a plurality of the above-mentioned storage units 10, a plurality of write word lines WWL, a plurality of write bit lines WBL, a plurality of first signal lines RL1, a plurality of second signal lines RL2 and a plurality of erase lines BL.
[0085] Among them, multiple storage cells 10 are arranged in an array structure along the second direction Y and the third direction Z, the second direction Y and the third direction Z intersect and are parallel to the substrate 600; multiple write word lines WWL, multiple first signal lines RL1, multiple second signal lines RL2 and multiple erase lines BL all extend along the second direction Y and are spaced apart along the third direction Z, and multiple write bit lines WBL extend along the third direction Z and are spaced apart along the second direction Y.
[0086] Each write word line WWL is in contact with and connected to a row of write gate structures 110 arranged at intervals along the second direction Y; each write bit line WBL is electrically connected to a row of first source and drain regions 101 arranged at intervals along the third direction Z; each read first signal line RL1 is in contact with and connected to a row of third source and drain regions 201 arranged at intervals along the second direction Y; each read second signal line RL2 is in contact with and connected to a row of fourth source and drain regions 202 arranged at intervals along the second direction Y; each erase line BL is formed by a row of erase units 300 arranged along the second direction Y connected end to end.
[0087] The memory provided by the present disclosure includes a plurality of the above-mentioned memory cells 10. By forming an erase line BL in the memory, the plurality of memory cells 10 can be divided into blocks through the erase line BL, and the data in each memory cell 10 in the corresponding block can be erased through different erase lines BL, thereby realizing selective erasure of data in the memory; data is erased by applying a voltage to the erase line BL, thereby improving the data erasing speed and thus improving the overall functionality of the device; in addition, the erase line BL is arranged parallel to the write word line WWL, the first read signal line RL1 and the second read signal line RL2, and a stepped lead-out structure can be formed in one direction to realize the lead-out of 4 signal lines in different layers, thereby simplifying the preparation process.
[0088] The structure of the memory provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings:
[0089] In the embodiment provided by the present disclosure, the memory includes a plurality of the above-mentioned memory cells 10 arranged in an array. In the row direction, the number of memory cells 10 in each row is m, m>1; in the column direction, the number of memory cells 10 in each column is n, n>1, that is, a plurality of memory cells 10 can be arranged in an m×n array in the memory. In the row direction, the second direction Y, and the column direction is the third direction Z. Arranging a plurality of memory cells 10 in an array in the memory can achieve the purpose of increasing the density of the memory cells 10 through reasonable arrangement.
[0090] In an embodiment provided by the present disclosure, the memory includes a plurality of write word lines WWL extending along the second direction Y and spaced apart along the third direction Z. In the row direction, each write word line WWL connects m memory cells 10 in series, and the write gate structure 110 of each memory cell 10 is in contact with the write word line WWL, so as to select a specific row through the write word line WWL.
[0091] In order to improve the compactness of the memory structure, each write word line WWL and the write gate structure 110 in the write transistor 100 in the same row are an integrally formed structure. The write word line WWL and the write gate structure 110 are made of the same material, such as tungsten, and are integrally formed. Of course, the write word line WWL can also be formed by connecting the write gate structures 110 in the same row end to end after each write transistor 100 is formed.
[0092] In each memory cell 10, the write gate dielectric structure 120 in the write transistor 100 surrounds the write gate structure 110. In the memory, since the write gate structure 110 and the write word line WWL are integrally formed, the write gate dielectric structure 120 extends and surrounds the outer surface of the write word line WWL, and the write gate dielectric structure 120 conformally covers the write word line WWL.
[0093] In order to prevent metal ions in the write word line WWL from diffusing into the memory cell 10 , a barrier layer 700 , such as titanium nitride, may be provided between the write word line WWL and the write gate dielectric structure 120 . The barrier layer 700 may maintain the structural integrity of the memory cell 10 .
[0094] In the embodiment provided in the present disclosure, the memory includes a plurality of write bit lines WBL extending along a third direction Z and spaced apart along a second direction Y. The projections of the write word lines WWL and the write bit lines WBL on the substrate 600 intersect with each other. In the column direction, each write bit line WBL is connected in series with n memory cells 10, and the first source and drain regions 101 of the write transistor 100 in each memory cell 10 are electrically connected to the write bit line WBL, so as to implement a data write operation on a specific memory cell 10 through the write bit line WBL.
[0095] In order to realize the electrical connection between the write bit line WBL and the first source and drain region 101, a second conductive block 402 and a first connecting wire 501 are sequentially arranged on each first source and drain region 101, the first connecting wire 501 extends along the first direction X, two adjacent first connecting wires 501 are insulated from each other, and two adjacent second conductive blocks 402 are insulated from each other. The lower end surface of the second conductive block 402 contacts the first source and drain region 101, the upper end surface of the second conductive block 402 contacts the lower end surface of the first connecting wire 501, and the upper end surface of the first connecting wire 501 contacts the write bit line WBL, so that the write bit line WBL is electrically connected to the first source and drain region 101.
[0096] The second conductive block 402 may be formed of the same or similar material and method as the first conductive block 401. In addition, the sidewall of the sleeve 131 of the write channel structure 130 in the write transistor 100 may extend to the outer sidewall of the second conductive block 402, and the sleeve 131 may surround a portion of the outer sidewall of the second conductive block 402. The projection of the second conductive block 402 on the substrate 600 overlaps with the projection of the filler 132 in the write channel structure 130 on the substrate 600, so as to ensure the reliability of the electrical connection between the second conductive block 402 and the write gate structure 110.
[0097] The first connecting line 501 can be formed of a metal material with good conductivity, such as tungsten. In addition, in order to prevent the diffusion of metal ions in the first connecting line 501, a barrier layer 700 can be coated on the outer wall of the first connecting line 501. The barrier layer 700 can be formed using the same material and method as the barrier layer 700 coated on the outside of the write line WWL, which will not be described in detail here.
[0098] In the embodiment provided by the present disclosure, the memory includes a plurality of first signal lines RL1 extending along the second direction Y and spaced along the third direction Z, and a plurality of second signal lines RL2 extending along the second direction Y and spaced along the third direction Z, and the first signal lines RL1 and the second signal lines RL2 are parallel to each other in the row direction. In the row direction, each first signal line RL1 is connected in series with m storage units 10, and the third source and drain regions 201 of the read transistor 200 in each storage unit 10 are in contact with the first signal line RL1; each second signal line RL2 is connected in series with m storage units 10, and the fourth source and drain regions 202 of the read transistor 200 in each storage unit 10 are in contact with the second signal line RL2. After the data is transmitted through the write transistor 100 and stored in the read gate structure 210 of the read transistor 200, when the data needs to be read, a read signal can be applied to the read transistor 200 through the first signal line RL1 or the second signal line RL2 to turn on the read transistor 200 and read the data.
[0099] The first signal line RL1 and the second signal line RL2 may be made of metal materials, such as tungsten, copper, aluminum and other materials with low resistivity, or other non-metallic materials with conductivity. Taking the case where the first signal line RL1 and the second signal line RL2 are both made of tungsten as an example, in order to prevent the diffusion of metal ions in the first signal line RL1 and the second signal line RL2, a barrier layer 700 may be provided on the outer surface of each first signal line RL1 and each second signal line RL2 to improve the yield and usability of the device. The barrier layer 700 may be made of the same material as the barrier layer 700 coated on the outside of the write word line WWL.
[0100] In the embodiment provided in the present disclosure, the memory includes a plurality of erase lines BL extending along the second direction Y and spaced apart along the third direction Z, and each erase line BL can be formed by connecting a row of erase units 300 arranged along the second direction Y end to end. In addition, the erase line BL can also be formed by an integral molding method. In the row direction, each erase line BL can connect m storage units 10 in series, and each erase line BL is located on the side of the second source and drain region 102 of the write transistor 100 close to the write gate structure 110, and the erase units 300 in each erase line BL surround part of the side wall of the sleeve 131 in the write channel structure 130. When erasing the data of some storage units 10, the corresponding erase line BL can be turned on to erase the data in this part of the storage unit 10, thereby improving the data erasing speed of the memory. In addition, when the memory is repeatedly read, written and erased, residual charge will remain in the transistor, causing the transistor to fail. The residual charge can be removed by setting the erase line BL to ensure the normal function of the transistor.
[0101] In which, in the memory, along the first direction X and away from the substrate 600, the lengths of the second read signal line RL2, the first read signal line RL1, the erase line BL and the write word line WWL decrease or increase successively, so as to facilitate the subsequent electrical connection of each signal line with other structures in the device.
[0102] Furthermore, the second read signal line RL2, the first read signal line RL1, the erase line BL and the write word line WWL all include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the first direction X, the main extension portions of any two of the second read signal line RL2, the first read signal line RL1, the erase line BL and the write word line WWL have overlapping orthographic projections on the substrate 600, and the lead-out end portions of any two of the second read signal line RL2, the first read signal line RL1, the erase line BL and the write word line WWL do not overlap in their orthographic projections on the substrate 600.
[0103] The memory also includes a plurality of second connection lines 502, which extend along the first direction X and are in contact with the lead-out end. The second connection lines 502 serve as electrical connection bridges connecting various signals, the erase line BL, and the write line WWL with other structures, and can be made of conductive materials, such as metal tungsten, copper, aluminum, etc. Taking the second connection line 502 as tungsten as an example, in order to prevent the second connection line 502 from diffusing during the process, a barrier layer 700 can be coated on the outer surface of the third connection line to prevent the metal from diffusing into the device and reducing the performance of the device. The barrier layer 700 can be made of the same or similar material as the barrier layer 700 coated on the outside of the write line WWL.
[0104] In the present disclosure, multiple memory cells 10 located in the same row share a first signal line RL1, a second signal line RL2 and a write word line WWL, and multiple memory cells 10 located in the same column share a write bit line WBL, which can reduce the complexity of the structural layout in the device, improve the compactness of the device structural layout and the integration of the device, and thus improve the storage density.
[0105] In the embodiment provided in the present disclosure, the circuit structure diagram of the memory is as follows: Figure 4 As shown, combined Figure 3 The memory structure shown in FIG. 1 is a memory structure in which, in each memory cell 10, the second source-drain region 102 of the write transistor 100 is in contact with the read gate structure 210 of the read transistor 200. The specific principle of data reading and writing of a single memory cell 10 is as follows:
[0106] The process of writing "1" is: apply a positive voltage to the write gate structure 110 (write word line WWL), turn on the write transistor 100, apply a positive voltage to the first source and drain region 101 of the write transistor 100, inject charge into the gate structure of the read transistor 200 through the second source and drain region 102 of the write transistor 100, and after the charge injection, remove the voltage of the first source and drain region 101 of the write transistor 100 and the voltage on the write gate structure 110 to save the "1" state.
[0107] The process of reading "1" is as follows: after writing "1" to the storage cell 10, a read voltage is applied to the third source-drain region 201 or the fourth source-drain region 202 of the read transistor 200. Since there is charge in the read gate structure 210, the read transistor 200 is in a lower resistance state and obtains a larger current. After amplification by the amplifier, the reading of "1" is completed.
[0108] The process of writing "0" is: applying a positive voltage to the write gate structure 110 (write word line WWL), turning on the write transistor 100, applying a negative voltage to the first source and drain region 101 of the write transistor 100, extracting the charge in the gate structure of the read transistor 200 through the second source and drain region 102 of the write transistor 100, and after the charge extraction, removing the voltage of the first source and drain region 101 of the write transistor 100 and the voltage on the write gate structure 110 to save the "0" state.
[0109] The process of reading "0" is as follows: after writing "0" to the storage cell 10, a read voltage is applied to the third source-drain region 201 or the fourth source-drain region 202 of the read transistor 200. Since there is no charge in the read gate structure 210, the read transistor 200 is in a higher resistance state and obtains a smaller current. After amplification by the amplifier, the reading of "0" is completed.
[0110] It should be noted that the positive voltage in the above data reading and writing process refers to a voltage greater than the threshold voltage. The amplifier is arranged in the peripheral circuit, and its function is to read and amplify the data in the storage unit 10 to meet the demand for high-speed data processing.
[0111] The present disclosure provides a method for reading data from a memory, using the above memory in combination with Figures 2 to 3 The memory structure shown and Figure 4 The circuit structure of the memory shown in the figure, the method comprises: steps S10 to S30.
[0112] Wherein, step S10: determining the access memory cell 10 that needs to read data, and the selected write word line WWL, the selected read first signal line RL1 and the selected read second signal line RL2 connected to the access memory cell 10, and determining all non-access memory cells 10 connected to the selected write word line WWL;
[0113] Step S20: turning on the write transistor 100 in the non-access memory cell 10 to erase the data stored in the storage node in the non-access memory cell 10;
[0114] Step S30: Control all write transistors 100 in the memory to remain in a closed state, apply a read voltage by selecting one of the first read signal line RL1 and the second read signal line RL2, and read the data stored in the storage node in the access memory cell 10 from the other of the first read signal line RL1 and the second read signal line RL2.
[0115] In the embodiment provided by the present disclosure, before performing a data read operation on a storage unit 10, it is necessary to first determine the access storage unit 10 for which the data is to be read. For the access storage unit 10, by activating the write word line WWL of the access unit and opening the storage unit 10 in the row where the access storage unit 10 is located, the data read operation can be performed on the access storage unit 10; for the non-access storage unit 10, the corresponding write word line WWL can be in an inactive state, and the storage unit 10 in the row where the storage unit 10 is located can be closed, and the data cannot be read at this time. After determining the required access storage unit 10 and the non-access storage unit 10 in the memory, the write word line WWL of the access storage unit 10, the read first signal line RL1, and the read second signal line RL2 are selected.
[0116] Before performing a read operation on the data in the access memory cell 10, the data in the non-access memory cell 10 needs to be erased to read the data in the access memory cell 10. Specifically, a positive voltage is applied to the write word line WWL of the non-access memory cell 10 to turn on the write transistor 100 of the non-access memory cell 10, and a positive voltage is applied to the erase line BL to extract the charge in the non-access memory cell 10, thereby erasing the data stored in the storage node in the non-access memory cell 10.
[0117] After erasing the data in the non-access memory cell 10, all write transistors 100 in the memory are controlled to remain in a closed state, and a read voltage is applied by selecting the first read signal line RL1 or the second read signal line RL2 to read the data stored in the storage node in the access memory cell 10 from the selected read second signal line RL2 or the selected read second signal line RL3. The data reading method is as described above and will not be repeated here.
[0118] After reading the data from the access memory cell 10, the method further includes: turning on the write transistor 100 of the access memory cell 10, erasing the data stored in the storage node in the access memory cell 10; and rewriting the data to a row of memory cells 10 connected to the selected write word line WWL. The data in the access memory cell can be erased by applying a positive voltage to the write word line WWL of the access memory cell 10 to turn on the write transistor 100 of the access memory cell 10, and by applying a high voltage to the erase line BL to extract the charge in the access memory cell 10 through the tunnel effect, thereby erasing the data stored in the storage node in the access memory cell 10. After erasing the data in the access memory cell 10, the data can be rewritten to the memory cell 10, wherein the data writing method is as described above and will not be repeated here.
[0119] The data reading method of the memory provided in the present disclosure can improve the data reading speed and enhance the functionality of the device by determining the access memory cell 10 and erasing the data in the non-access memory cell 10 through the erase line BL to read the data in its storage node.
[0120] The present disclosure provides a method for erasing data of a memory, using the above-mentioned memory, combined with Figures 2 to 3 The memory structure shown and Figure 4 The circuit structure of the memory shown in the figure, the method comprises: steps S100 to S200.
[0121] Wherein, step S100: determining a selected block whose data needs to be erased, the selected block comprising a row of storage cells 10 arranged at intervals along the second direction Y, and a selected write word line WWL, a selected erase line BL, a selected read first signal line RL1, and a selected read second signal line RL2 connected to the row of storage cells 10 arranged at intervals along the second direction Y;
[0122] Step S200: erasing the data in each storage node in all storage cells 10 in the selected block by selecting the erase line BL.
[0123] In the embodiment provided by the present disclosure, when erasing the data in the storage unit 10, after determining the selected block, a positive voltage may be applied to the write word line WWL of each storage unit 10 in the selected block, and then the write transistor 100 of each storage unit 10 in the selected block may be turned on, and the erase line BL corresponding to the row (row) where the selected block is located may be selected, and a high voltage may be applied to the erase line BL to extract the charge in the storage unit 10 in the selected block through the tunnel effect, and erase the data stored in the storage node in the storage unit 10 in the selected block. Of course, the data in all the storage units 10 in the memory may also be erased through the erase line BL.
[0124] The data erasing method of the memory provided by the present disclosure does not need to erase all the data through the substrate 600 when performing an erasing operation on the data of the storage node in the memory. The data in the storage cell 10 in the selected block can be erased, thereby improving the data erasing speed. In addition, due to the setting of the erase line BL, the floating body effect in the memory can be reduced, thereby improving the functionality of the device.
[0125] The disclosed embodiment provides an electronic device, including the above-mentioned memory. The electronic device can be a computer device such as a computer, a server, or an electronic device such as a mobile phone, a tablet computer, a smart TV, or other types of devices such as a game console, an industrial control computer, etc.
[0126] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A memory cell formed on a substrate, characterized in that: include: A write transistor and a read transistor, wherein both the write transistor and the read transistor are vertical structure transistors, and the write transistor is located above the read transistor; The write transistor includes a write channel structure, a write gate structure surrounding a portion of the sidewall of the write channel structure, and a write gate dielectric structure located between the write gate structure and the write channel structure, wherein the write channel structure extends along a first direction and includes a first source and drain region, a write channel region, and a second source and drain region; the first direction is perpendicular to the plane of the substrate; The read transistor includes a read gate structure extending along the first direction, a read channel structure surrounding a sidewall and an end of the read gate structure, and a read gate dielectric structure located between the read gate structure and the read channel structure, wherein the read channel structure includes a third source and drain region, a read channel region, and a fourth source and drain region; The second source and drain region is conductively connected to the read gate structure, and a projection of the write channel structure on the substrate overlaps with a projection of the read gate structure on the substrate; An erasing unit is coated on a portion of the sidewall of the write channel structure, and the erasing unit is located on a side of the write gate structure close to the second source and drain region.
2. The storage unit according to claim 1, characterized in that The write gate dielectric structure conformally covers the surface of the write gate structure.
3. The storage unit according to claim 1, characterized in that The write channel structure comprises a sleeve and a filling body, wherein the sleeve conformally covers the side wall and the lower end surface of the filling body, and the upper surface of the sleeve is not lower than the upper surface of the filling body; the sleeve contacts the write gate dielectric structure.
4. The storage unit according to claim 3, characterized in that The material of the sleeve includes indium gallium zinc oxide, and the material of the filler includes indium zinc oxide.
5. The storage unit according to claim 1, characterized in that The material of the read gate structure includes indium zinc oxide, and the material of the read channel structure is indium gallium zinc oxide.
6. The storage unit according to claim 1, characterized in that The second source and drain regions are conductively connected to the read gate structure via a first conductive block, the lower end surface of the first conductive block is in contact with the upper end surface of the read gate structure, and the upper end surface of the first conductive block is in contact with the second source and drain regions; the first conductive block is insulated from the read channel structure.
7. A memory, characterized in that: Formed on a substrate, comprising: A plurality of storage units according to any one of claims 1 to 6, wherein the plurality of storage units form an array structure along a second direction and a third direction, wherein the second direction and the third direction intersect and are parallel to the substrate; a plurality of write word lines extending along the second direction and arranged at intervals along the third direction, each of the write word lines being in contact and connected with the gate structures of a row of the write transistors arranged at intervals along the second direction; a plurality of write bit lines extending along the third direction and arranged at intervals along the second direction, each of the write bit lines being electrically connected to the first source and drain regions of a row of the write transistors arranged at intervals along the third direction; a plurality of first read signal lines extending along the second direction and arranged at intervals along the third direction, each of the first read signal lines being in contact and connected with the third source and drain regions of a row of the read transistors arranged at intervals along the second direction; a plurality of second read signal lines extending along the second direction and arranged at intervals along the third direction, each of the second read signal lines being in contact and connected with the fourth source and drain regions of a row of the read transistors arranged at intervals along the second direction; A plurality of erasing lines extending along the second direction and arranged at intervals along the third direction, each of the erasing lines being formed by connecting a row of the erasing units arranged along the second direction end to end.
8. The memory according to claim 7, characterized in that: The write word line and the gate structure are made of the same material, and the write word line and the gate structure are integrally formed.
9. The memory according to claim 7, characterized in that: A second conductive block and a first connecting line are sequentially disposed on each of the first source and drain regions, the first connecting line extends along the first direction, two adjacent first connecting lines are insulated from each other, and two adjacent second conductive blocks are insulated from each other; The lower end surface of the second conductive block contacts the first source and drain region, the upper end surface of the second conductive block contacts the lower end surface of the first connecting line, and the upper end surface of the first connecting line contacts the write bit line, thereby realizing electrical connection between the write bit line and the first source and drain region.
10. The memory according to claim 7, characterized in that: In a direction along the first direction and away from the substrate, the lengths of the second read signal line, the first read signal line, the erase line, and the write word line decrease or increase in sequence.
11. The memory according to claim 10, characterized in that: The second read signal line, the first read signal line, the erase line and the write line all include a main extension portion and a lead-out end portion located at at least one end of the main extension portion; in the first direction, the main extension portions of any two of the second read signal line, the first read signal line, the erase line and the write line overlap in their orthographic projections on the substrate, and the lead-out end portions of any two of the second read signal line, the first read signal line, the erase line and the write line do not overlap in their orthographic projections on the substrate.
12. The memory according to claim 11, characterized in that: The memory further includes a plurality of second connection lines extending along the first direction and contacting and connecting with the lead-out end portions.
13. A method for reading data from a memory, applied to the memory according to any one of claims 7 to 12, characterized in that: include: Determine an access memory cell from which data needs to be read, and a selected write word line, a selected read first signal line, and a selected read second signal line connected to the access memory cell, and determine all non-access memory cells connected to the selected write word line; Turning on the write transistor in the non-access memory cell to erase data stored in a storage node in the non-access memory cell; All the write transistors in the memory are controlled to remain in a closed state, a read voltage is applied through one of the selected read first signal line and the selected read second signal line, and data stored in a storage node in the access storage unit is read from the other of the selected read first signal line and the selected read second signal line.
14. The method for reading data from a memory according to claim 13, wherein: After reading the data stored in the storage node in the access storage unit, the method further includes: Turning on the write transistor in the access memory cell to erase the data stored in the storage node in the access memory cell; Data are rewritten to a row of the memory cells connected to the selected write word line.
15. A method for erasing data in a memory, applied to the memory according to any one of claims 7 to 12, characterized in that: include: Determine a selected block where data needs to be erased, wherein the selected block includes a row of the storage cells arranged at intervals along the second direction, and a selected write word line, a selected erase line, a selected read first signal line, and a selected read second signal line connected to the row of the storage cells arranged at intervals along the second direction; The data in each storage node in all the storage units in the selected block are erased through the selected erase line.
16. An electronic device, characterized in that: Comprising a memory as claimed in any one of claims 7 to 12.