Annealing method of silicon carbide wafer

Abstract

The invention discloses an annealing method of a silicon carbide wafer. According to the method, a gap between a crucible and a wafer is filled with an annealing solvent, the annealing solvent is melted at a high temperature, and then the uniformity of the annealing temperature is improved in a manner of replacing existing gas heat conduction or radiation heat conduction with liquid heat conduction; and meanwhile, the temperature is reduced to 900 DEG C by controlling the cooling rate, so that impurities in and on the surface of the wafer can be uniformly separated out under the cooling process. If the temperature is reduced too fast, the internal structure and uniformity of the wafer can be damaged, and the effect of eliminating the internal defects of the silicon carbide wafer is poor. According to the technical scheme of the invention, qualified wafer products can be obtained, and the stress value of the substrate finished product, the proportion of grinding and cracking in the later pass and the proportion of adverse effects caused by stress in the later pass can be controlled within a better level.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an annealing method for a silicon carbide wafer. Background Art

[0002] As the most technologically mature material among the third-generation semiconductor materials (including II-O, III-N, SiC, diamond, etc.), SiC has the advantages of wide bandgap, high critical breakdown field strength (10 times that of Si), high thermal conductivity (3.3 times that of Si), high carrier saturation mobility (2.5 times that of Si) and high bonding energy. Its excellent performance can meet the new needs of special fields of modern electronic technology, and is particularly suitable for manufacturing high-frequency, high-power, radiation-resistant and corrosion-resistant electronic devices. Therefore, it is regarded as one of the most promising materials in the field of semiconductor materials. At present, silicon carbide single crystal materials used in the manufacture of devices are generally grown by PVT (physical vapor phase) method. Compared with the complex control and high cost of high-temperature chemical deposition method and the major defects of metal contamination and surface roughness of solution method, PVT method is mature in technology and is currently the most widely used method for growing silicon carbide single crystals. In addition, the growth conditions of silicon carbide single crystals grown by PVT method are simple, which is convenient for industrialization. However, due to the temperature non-uniformity during the growth process, large internal stress is likely to appear in the crystal, causing the crystal to crack during processing, reducing the productivity of the silicon carbide wafer. Therefore, annealing treatment is required after the growth of the silicon carbide crystal is completed. The current annealing process mainly uses an induction coil to heat the crystal in the crucible and then cool it to eliminate the internal stress. This method has the disadvantages of uneven heating of the crystal and easy generation of secondary internal stress, resulting in poor annealing effect. The crystal cracks when it is out of the furnace, affecting the yield of the crystal, and the power cannot be set too high in the crystal heating section, resulting in a long crystal heating time and a long overall process time.

[0003] The large number of dislocations (on the order of 104 / cm2) contained in the current substrate is considered to be the main limiting factor affecting the performance of power devices. For example, basal plane dislocations (BPD) require special attention. Such defects will lead to instability in the forward voltage in the prepared bipolar device. Classical theory believes that plastic deformation caused by stress is one of the reasons for the formation of dislocations inside the material. According to the defect analysis theoretical model, the main reason for the generation of dislocations in the crystal is the slip of the slip system caused by the shear stress exceeding the critical shear stress value. For the hexagonal SiC structure, its slip usually occurs on the (0001) plane. Therefore, the shear stress σrz exceeding the critical value in the SiC crystal grown along the c-axis is the root cause of the dislocation defect.

[0004] There are many factors that induce thermal stress in the silicon carbide crystal growth process, such as seed crystal bonding conditions, crystal growth interface shape, wafer cutting, grinding and polishing, etc. In combination with the actual PVT method 4H-SiC single crystal growth process, in order to achieve crystal form and growth rate control, the SiC raw material temperature is usually set higher and the seed crystal temperature is lower, so a considerable axial temperature field gradient is formed inside the SiC crucible, which is prone to thermal stress; and the difference in material thermal expansion coefficient between graphite parts (seed crystal holder, crucible, etc.) and silicon carbide ingots is also prone to mechanical stress.

[0005] In the prior art, a treatment method for reducing crystal thermal stress (CN113073392A) is used to place a silicon carbide crystal in a heating furnace, introduce argon or nitrogen as a protective gas, control the pressure in the furnace to be 0.1-0.2MPa, and heat the furnace at a heating rate of 600-750℃ / h. Heat to 1100-1200℃, keep warm for 10-20h, and perform annealing. After stopping heating, fill the heating furnace with neon gas at a rate of 0.5-2vol% / min for 20-60min. After the temperature of the heating furnace is cooled to room temperature, the silicon carbide crystal is taken out, and the finished silicon carbide crystal is obtained after cutting and polishing. The prior art mainly deals with the reduction and treatment method of thermal stress of silicon carbide crystals. There is less research on silicon carbide wafers, and there is even less description in the patent on how to use a uniform temperature field. The stress of silicon carbide wafers not only comes from silicon carbide crystals, but is also related to subsequent substrate processing, such as wire cutting, grinding and polishing. Reducing the stress of silicon carbide wafers and improving the quality and yield of silicon carbide wafers are issues that the industry continues to solve. Summary of the invention

[0006] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a method for annealing a silicon carbide wafer.

[0007] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0008] A method for annealing a silicon carbide wafer comprises the following steps:

[0009] S1. Vertically support the silicon carbide wafer and place it in a graphite crucible, fill the gap between the graphite crucible and the silicon carbide wafer with annealing solvent, and insert a thermocouple into the wall of the graphite crucible;

[0010] S2, placing the crucible into a high-temperature annealing furnace and evacuating the furnace, and after reaching a preset vacuum degree, filling the high-temperature annealing furnace with an inert gas;

[0011] S3, firstly heating the temperature in the high temperature annealing furnace to a set temperature, keeping the temperature for a set time so that the annealing solvent is completely melted, then heating the temperature to a set temperature, keeping the temperature for a set time to perform annealing;

[0012] S4, cooling the temperature in the high temperature annealing furnace to a set temperature at a set cooling rate, and finally stopping heating to cool the temperature in the high temperature annealing furnace to room temperature to prevent stress from occurring due to too fast cooling;

[0013] S5. Take out the crucible and put it into a water tank. After the annealing solvent is completely dissolved, take out the wafer, and the annealing of the silicon carbide wafer is completed.

[0014] Further, in step S1, the annealing solvent includes K2SO4, NaF, KCl or NaCl.

[0015] Furthermore, in step S1, the particle size of the annealing solvent is 60-100 mesh.

[0016] Furthermore, in step S2, the preset vacuum degree is 1×10^-2 Pa.

[0017] Furthermore, in step S2, an inert gas is charged into the annealing furnace until the pressure inside the annealing furnace is 1 to 1.3 atmospheres.

[0018] Furthermore, in step S2, the inert gas filled into the high temperature annealing furnace is replaced with nitrogen.

[0019] Furthermore, in step S3, the temperature in the high temperature annealing furnace is first heated to 850-950° C., kept at this temperature for 3-5 hours to completely melt the annealing solvent, and then heated to 1600-1800° C., kept at this temperature for 10 hours for annealing.

[0020] Furthermore, in step S3, the heating rate is 5-10°C.

[0021] Furthermore, in step S4, the temperature in the high temperature annealing furnace is cooled to 900° C. at a cooling rate of 5 to 10° C. / min, and finally the heating is stopped and the temperature in the high temperature annealing furnace is cooled to room temperature to prevent stress from occurring due to too fast cooling.

[0022] Furthermore, in step S4, the temperature in the high temperature annealing furnace is first cooled to 1200°C at a cooling rate of 2 to 4°C / min, and then cooled to 900°C at a cooling rate of 5 to 10°C / min, and the temperature is cooled in stages. Finally, the heating is stopped and the temperature in the high temperature annealing furnace is cooled to room temperature to prevent stress from occurring due to too rapid cooling.

[0023] The present invention improves the uniformity of annealing temperature by melting the annealing flux at high temperature and then replacing the existing gas heat conduction or radiation heat conduction with liquid heat conduction, thereby reducing the temperature non-uniformity between wafers and within the wafer itself, and greatly reducing the stress of the wafer; and the liquid phase heat capacity is also much greater than the gas phase, which can reduce the problem of inaccurate temperature control caused by thermal inertia. At the same time, the liquid phase wrapping effect can prevent the surface pits caused by decomposition and sublimation on the wafer surface.

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] 1) The present invention fundamentally improves the uniformity of the temperature of the entire annealing crucible by liquid phase conduction.

[0026] 2) The present invention controls the temperature of the wafer by monitoring the temperature of the liquid phase flux, and can achieve the effect of accurately monitoring the annealing temperature during the entire annealing process.

[0027] 3) The present invention adopts a liquid phase conduction method and can well control the thermal inertia by designing the volume of the crucible, thereby solving the problem of heating and cooling speed.

[0028] 4) The present invention does not require a heat field, only a crucible is needed, which can be directly placed in an atmosphere furnace, thus reducing the loss of equipment and heat field costs.

[0029] 5) The wafer surface will decompose and sublimate in the atmosphere, causing the annealed wafer to be scrapped, and the volatile Si atmosphere will damage the thermal field and the annealing furnace heater. The present invention avoids this problem by liquid phase encapsulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a stress test diagram of the wafer prepared in Example 1 of the present invention;

[0031] Figure 2 is a stress test parameter setting diagram of a wafer prepared in Example 1 of the present invention;

[0032] Figure 3 The present invention is a flowchart of a method for annealing a silicon carbide wafer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following description combines specific illustrations to explain the technical solution so as to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and similar generalized embodiments made by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0034] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms of "a", "the" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0035] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish similar objects and are not necessarily used to describe the order or sequence of features described in one or more embodiments of this specification. In addition, the terms "having" and "including" are similarly expressed to indicate a non-exclusive scope. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to the contents listed in detail, but may include inherent contents related to these steps or modules that are not listed.

[0036] A method for annealing a silicon carbide wafer, such as Figure 3 As shown, the following steps are included:

[0037] Place the wafer in a graphite crucible with a vertical support, fill the gap between the crucible and the wafer with annealing solvent, and insert a thermocouple into the crucible wall;

[0038] The crucible is placed in a high-temperature annealing furnace and then evacuated. After reaching a preset vacuum degree, an inert gas or nitrogen is filled into the annealing furnace;

[0039] First, heat to 850-950°C, keep warm for 3-5 hours to completely melt the annealing solvent, then heat to 1600-1800°C, keep warm for 10 hours for annealing;

[0040] The temperature was lowered to 900°C at a rate of 5-10°C / min, and the heating system was finally turned off and the furnace was cooled to room temperature.

[0041] Take out the crucible and put it into a water tank, and take out the wafer after the annealing solvent is completely dissolved.

[0042] The inventor creatively discovered that the use of an annealing solvent in a liquid phase conduction manner can fundamentally improve the uniformity of the temperature of the entire annealing crucible.

[0043] The inventors have also found that the annealing solvent is mainly selected from K2SO4, NaF, KCl or NaCl, and more preferably K2SO4.

[0044] In some specific embodiments, the particle size of the annealing solvent is 40-60 mesh.

[0045] In some specific implementations, the support frame used for vertical support is a metal tungsten support or a graphite support.

[0046] In some specific embodiments, the preset vacuum degree is 1×10-2 Pa.

[0047] In some specific embodiments, an inert gas or nitrogen is filled into the annealing furnace until the pressure inside the annealing furnace is 1 to 1.3 atmospheres.

[0048] In some specific embodiments, the heating rate in step (3) is 5-10°C / min, which can be 5°C / min, 6°C / min, 7°C / min, 8°C / min, 9°C / min, 10°C / min, etc. At this heating rate, the silicon carbide wafer is gradually heated and continuously reaches a uniform heating state during the gradual heating process.

[0049] In some specific embodiments, the cooling process is to first cool down to 1200°C at 2-4°C / min, and then cool down to 900°C at 5-10°C / min. Under this cooling process, impurities inside and on the surface of the wafer can be uniformly precipitated. If the temperature is cooled too quickly, the internal structure and uniformity of the wafer will be destroyed, and the effect of eliminating internal defects of the silicon carbide wafer will be poor.

[0050] The technical solution of the present invention is further described below through specific embodiments.

[0051] Example 1

[0052] The annealing process of silicon carbide wafers includes:

[0053] (1) Place a 6-inch silicon carbide wafer in a graphite crucible supported vertically by metal tungsten, fill the gap between the crucible and the wafer with 60-80 mesh K2SO4, and insert a thermocouple into the crucible wall;

[0054] (2) placing the crucible into a high-temperature annealing furnace and evacuating the furnace to a vacuum of 1×10-2 Pa, and then filling the annealing furnace with nitrogen until the pressure inside the annealing furnace reaches 1.3 atmospheres;

[0055] (3) First, heat to 800°C at a rate of 5°C / min, keep warm for 3 h to completely melt the annealing solvent, then heat to 1650°C at a rate of 8°C / min, and keep warm for 10 h for annealing;

[0056] (4) First cool down to 1200℃ at 2℃ / min, then cool down to 900℃ at 5℃ / min, and finally turn off the heating system and cool down to room temperature with the furnace.

[0057] (5) Take out the crucible and place it in a water tank. After the annealing solvent is completely dissolved, take out the wafer.

[0058] use Figure 1 and Figure 2 The stress test method shown shows that the stress value of the finished wafer substrate is 5.6. During the subsequent grinding, fewer cracks occur, accounting for 2.5%. The proportion of defective surface shape caused by stress in the subsequent grinding is 8.6%, which can be maintained at a good level.

[0059] In order to better illustrate the annealing process of the present method, the following embodiments 2 to 5 and comparative examples 1 to 2 are set. The basic steps are consistent with those of embodiment 1, and only the parameters in the table are changed to complete the final annealing. According to the technical solution of the present invention, qualified wafer products can be obtained, the stress value of the finished substrate can be controlled within 10 MPa, the proportion of subsequent grinding cracks can be controlled within 6%, and the proportion of defects caused by stress in the subsequent pass can be controlled within 10%.

[0060]

[0061]

[0062] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for annealing a silicon carbide wafer, characterized in that: The following steps are involved: S1. Vertically support the silicon carbide wafer and place it in a graphite crucible, fill the gap between the graphite crucible and the silicon carbide wafer with annealing solvent, and insert a thermocouple into the wall of the graphite crucible; S2, placing the crucible into a high-temperature annealing furnace and evacuating the furnace, and after reaching a preset vacuum degree, filling the high-temperature annealing furnace with an inert gas; S3, firstly heating the temperature in the high temperature annealing furnace to a set temperature, keeping the temperature for a set time so that the annealing solvent is completely melted, then heating the temperature to a set temperature, keeping the temperature for a set time to perform annealing; S4, cooling the temperature in the high temperature annealing furnace to a set temperature at a set cooling rate, and finally stopping heating to cool the temperature in the high temperature annealing furnace to room temperature to prevent stress from occurring due to too fast cooling; S5. Take out the crucible and put it into a water tank. After the annealing solvent is completely dissolved, take out the wafer, and the annealing of the silicon carbide wafer is completed.

2. The annealing method of a silicon carbide wafer according to claim 1, characterized in that: In step S1, the annealing solvent includes K2SO4, NaF, KCl or NaCl.

3. The annealing method of a silicon carbide wafer according to claim 1, characterized in that: In step S1, the particle size of the annealing solvent is 60-100 mesh.

4. The annealing method of a silicon carbide wafer according to claim 1, characterized in that: In step S2, the vacuum degree is preset to 1×10^-2 Pa.

5. The annealing method of a silicon carbide wafer according to claim 1, characterized in that: In step S2, an inert gas is charged into the annealing furnace until the pressure inside the annealing furnace is 1 to 1.3 atmospheres.

6. The method for annealing a silicon carbide wafer according to claim 5, characterized in that: In step S2, the inert gas filled into the high temperature annealing furnace is replaced with nitrogen.

7. The method for annealing a silicon carbide wafer according to claim 1, characterized in that: In step S3, the temperature in the high temperature annealing furnace is first heated to 850-950° C. and kept at this temperature for 3-5 hours to completely melt the annealing solvent, and then heated to 1600-1800° C. and kept at this temperature for 10 hours for annealing.

8. The method for annealing a silicon carbide wafer according to claim 1, characterized in that: In step S3, the heating rate is 5-10°C.

9. The method for annealing a silicon carbide wafer according to claim 1, characterized in that: In step S4, the temperature in the high temperature annealing furnace is cooled to 900° C. at a cooling rate of 5 to 10° C. / min, and finally the heating is stopped and the temperature in the high temperature annealing furnace is cooled to room temperature to prevent stress from occurring due to too fast cooling.

10. The method for annealing a silicon carbide wafer according to claim 1, characterized in that: In step S4, the temperature in the high temperature annealing furnace is first cooled to 1200°C at a cooling rate of 2-4°C / min, and then cooled to 900°C at a cooling rate of 5-10°C / min, and the temperature is cooled in stages. Finally, the heating is stopped and the temperature in the high temperature annealing furnace is cooled to room temperature to prevent stress from occurring due to too fast cooling.

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