Reference voltage source with high-order curvature compensation function

Abstract

The invention discloses a reference voltage source with a high-order curvature compensation function. The reference voltage source comprises a band-gap core circuit, a common-mode feedback circuit and a high-order curvature correction circuit. The band-gap core circuit is used for generating a reference voltage; the common-mode feedback circuit is used for generating common-mode voltage according to the reference voltage and returning the common-mode voltage to the band-gap core circuit through negative feedback so as to improve the stability of the band-gap core circuit; and the high-order curvature correction circuit is used for extracting current from the band-gap core circuit or injecting current into the band-gap core circuit according to the reference voltage so as to eliminate high-order errors generated by temperature in the band-gap core circuit. According to the invention, high-order curvature compensation can be carried out on the temperature through the high-order curvature correction circuit, so that the precision of the output reference voltage can be effectively improved, the temperature coefficient is reduced, and the temperature stability of the reference voltage is improved. Meanwhile, the circuit structure is simple, the occupied chip area is small, and high practicability is achieved.

Description

Technical Field

[0001] The invention belongs to the field of reference voltage sources, and in particular relates to a reference voltage source with a high-order curvature compensation function. Background Art

[0002] The reference voltage source can generate a stable voltage that does not change with temperature. It is usually used in various high-precision digital-analog mixed circuit systems, such as analog-to-digital converters, digital-to-analog converters, LDOs, etc. Its stability directly determines the accuracy of the system. The traditional first-order compensation is to compensate for the negative temperature coefficient of the first-order term of VBE through the positive temperature coefficient voltage generated by △VBE, and its optimal temperature drift can only reach 20-30ppm / ℃. The high-order curvature correction technology further reduces the temperature drift by compensating the quadratic term and the high term of VBE, and can achieve a temperature drift of less than 10ppm / ℃. Therefore, it is necessary to propose a circuit using high-order curvature correction technology to further reduce the temperature drift. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a reference voltage source with a high-order curvature compensation function.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A reference voltage source with high-order curvature compensation function, comprising:

[0006] Bandgap core circuit for generating reference voltage V REF ;

[0007] The common-mode feedback circuit is used to REF generating a common mode voltage, and returning the common mode voltage to the bandgap core circuit through negative feedback to increase the stability of the bandgap core circuit; and

[0008] A high-order curvature correction circuit is used to adjust the curvature according to the reference voltage V REF Current is extracted or injected into the bandgap core circuit to remove higher-order errors caused by temperature in the bandgap core circuit.

[0009] Further, the bandgap core circuit includes an eighth MOS transistor, a second triode, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and N first triodes connected in parallel, wherein N is an integer greater than or equal to 1;

[0010] The source of the eighth MOS transistor is connected to the external power supply voltage, the gate is electrically connected to the output end of the common-mode feedback circuit, and the drain is electrically connected to the first ends of the seventh resistor and the eighth resistor respectively; the second end of the seventh resistor is electrically connected to the inverting input end of the first operational amplifier and the collectors of the N first transistors respectively; the second end of the eighth resistor is electrically connected to the non-inverting input end of the first operational amplifier and the collector of the second transistor respectively; the base of the second transistor and the bases of the N first transistors are both electrically connected to the output end of the first operational amplifier;

[0011] The non-inverting input terminal of the first operational amplifier is electrically connected to the first input terminal of the common-mode feedback circuit, and the inverting input terminal of the first operational amplifier is electrically connected to the second input terminal of the common-mode feedback circuit; the output terminal of the first operational amplifier is used to generate a reference voltage V REF , the output end of the first operational amplifier is electrically connected to the third input end of the common mode feedback circuit and the input end of the high-order curvature correction circuit respectively;

[0012] The emitters of the N first transistors are all electrically connected to the first end of the ninth resistor, and the emitter of the second transistor is electrically connected to the second end of the ninth resistor; the second end of the ninth resistor is grounded through the tenth resistor, and the second end of the ninth resistor is also electrically connected to the correction end of the high-order curvature correction circuit.

[0013] Furthermore, the eighth MOS tube is a PMOS tube; the second transistor and the N first transistors are all NPN transistors.

[0014] Furthermore, the seventh resistor and the eighth resistor are of the same type and size.

[0015] Furthermore, the ratio of the sum of the saturation currents of the N first transistors to the saturation current of the second transistor is N:1.

[0016] Furthermore, the emitter area of ​​each of the first triodes is the same as the emitter area of ​​the second triode.

[0017] Further, the common-mode feedback circuit includes a second operational amplifier, a first input terminal of the second operational amplifier being electrically connected to the non-inverting input terminal of the first operational amplifier as the first input terminal of the common-mode feedback circuit, a second input terminal of the second operational amplifier being electrically connected to the inverting input terminal of the first operational amplifier as the second input terminal of the common-mode feedback circuit, a third input terminal of the second operational amplifier being electrically connected to the output terminal of the first operational amplifier as the third input terminal of the common-mode feedback circuit, and an output terminal of the second operational amplifier being electrically connected to the gate of the eighth MOS tube as the output terminal of the common-mode feedback circuit.

[0018] Further, the high-order curvature correction circuit includes a third operational amplifier, a fourth operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode, a tenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode, a sixteenth triode, a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twenty-third triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;

[0019] The non-inverting input terminal of the third operational amplifier, the non-inverting input terminal of the fourth operational amplifier and the base of the twenty-third triode are all electrically connected to the output terminal of the first operational amplifier, the emitter of the twenty-third triode is grounded through a first resistor, the inverting input terminal of the third operational amplifier is electrically connected to the collector of the twenty-second triode and the collector of the twenty-third triode respectively, the output terminal of the third operational amplifier is electrically connected to the base of the twelfth triode and the base of the twenty-second triode respectively, and the emitter of the twelfth triode and the emitter of the twenty-second triode are both connected to an external power supply voltage;

[0020] The inverting input terminal of the fourth operational amplifier is grounded through a second resistor, and the output terminal of the fourth operational amplifier is electrically connected to the base of the third triode, the base of the fourth triode, and the base of the tenth triode respectively; the emitter of the third triode, the emitter of the fourth triode, and the emitter of the tenth triode are all connected to an external power supply voltage, and the collector of the third triode is electrically connected to the inverting input terminal of the fourth operational amplifier;

[0021] The collector of the fourth triode is electrically connected to the collector of the fifth triode, the base of the fifth triode, the base of the sixth triode and the base of the seventh triode respectively, and the emitter of the fifth triode, the emitter of the sixth triode and the emitter of the seventh triode are all grounded; the collector of the sixth triode is electrically connected to the collector of the seventh triode through a third resistor;

[0022] The collector of the sixth triode is also electrically connected to the drain of the first MOS tube and the base of the thirteenth triode respectively, the gate of the first MOS tube is electrically connected to the gate of the sixth MOS tube, the drain of the sixth MOS tube and the gate of the seventh MOS tube respectively, the source of the first MOS tube is electrically connected to the collector of the eighth triode, the base of the eighth triode is electrically connected to the base of the seventeenth triode, the collector of the seventeenth triode, the base of the eighteenth triode and the base of the twenty-third triode respectively, and the emitter of the eighth triode, the emitter of the seventeenth triode, the emitter of the eighteenth triode and the emitter of the twenty-third triode are all connected to the external power supply voltage;

[0023] The collector of the seventh triode is also electrically connected to the drain of the second MOS tube and the base of the eleventh triode respectively, the gate of the second MOS tube is electrically connected to the gate of the third MOS tube and the drain of the third MOS tube respectively, the source of the second MOS tube is electrically connected to the collector of the ninth triode, the base of the ninth triode is electrically connected to the base of the fifteenth triode, the base of the sixteenth triode and the collector of the sixteenth triode respectively, the emitter of the ninth triode, the emitter of the fifteenth triode and the emitter of the sixteenth triode are all connected to the external power supply voltage, and the source of the third MOS tube is electrically connected to the collector of the fifteenth triode;

[0024] The emitter of the thirteenth triode is grounded, the collector of the thirteenth triode is electrically connected to the collector of the twelfth triode and the base of the nineteenth triode respectively, the emitter of the nineteenth triode is grounded through a fifth resistor, the collector of the nineteenth triode is electrically connected to the gate of the fifth MOS tube and the gate of the sixth MOS tube respectively; the drain of the fifth MOS tube is grounded, the source of the fifth MOS tube is electrically connected to the collector of the seventeenth triode, and the source of the sixth MOS tube is electrically connected to the collector of the eighteenth triode;

[0025] The emitter of the eleventh triode is grounded, the collector of the eleventh triode is electrically connected to the collector of the tenth triode, the base of the fourteenth triode and the base of the twenty-first triode respectively, the emitter of the fourteenth triode is grounded through a fourth resistor, the collector of the fourteenth triode is electrically connected to the gate of the third MOS tube and the gate of the fourth MOS tube respectively; the drain of the fourth MOS tube is grounded, and the source of the fourth MOS tube is electrically connected to the collector of the sixteenth triode;

[0026] The emitter of the twenty-first transistor is grounded through the sixth resistor, the collector of the twenty-first transistor is electrically connected to the drain of the seventh MOS transistor, the drain of the seventh MOS transistor is electrically connected to the second end of the ninth resistor as the correction end of the high-order curvature correction circuit, and the source of the seventh MOS transistor is electrically connected to the collector of the twenty-third transistor.

[0027] Further, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all PMOS tubes;

[0028] The third triode, the fourth triode, the eighth triode, the ninth triode, the tenth triode, the twelfth triode, the fifteenth triode, the sixteenth triode, the seventeenth triode, the eighteenth triode, the twenty-third triode and the twenty-second triode are all PNP triodes;

[0029] The fifth triode, the sixth triode, the seventh triode, the eleventh triode, the thirteenth triode, the fourteenth triode, the nineteenth triode, the twenty-first triode and the twenty-third triode are all NPN triodes.

[0030] Further, the emitter area ratio of the third triode, the fourth triode and the tenth triode is 4:1:1; the emitter area ratio of the fifth triode, the sixth triode and the seventh triode is 2:1:1; the emitter area ratio of the eighth triode, the seventeenth triode, the eighteenth triode and the twenty-third triode is 2:1:1:4; the emitter area ratio of the ninth triode, the fifteenth triode and the sixteenth triode is 2:1:1; the emitter area ratio of the twelfth triode and the twenty-second triode is 1:2; the emitter area ratio of the fourteenth triode and the twenty-first triode is 1:4; the width-to-length ratio of the first MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube is 2:1:1:4; the width-to-length ratio of the second MOS tube, the third MOS tube and the fourth MOS tube is 2:1:1; the resistance values ​​of the fourth resistor and the fifth resistor are both 4 times the resistance value of the sixth resistor.

[0031] In the present invention, the high-order curvature compensation circuit can be used to compensate for the temperature, thereby effectively improving the accuracy of the output reference voltage, reducing the temperature coefficient, and improving the temperature stability of the reference voltage. At the same time, the circuit structure is simple, the chip area occupied is small, and it has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 It is a structural schematic diagram of an embodiment of a reference voltage source with a high-order curvature compensation function of the present invention.

[0034] Figure 2 The circuit diagram of the high-order curvature correction circuit.

[0035] Figure 3 FIG. 4 is a schematic diagram of a reference voltage simulation result of performing high-order curvature compensation using the circuit of this embodiment.

[0036] Figure 4 This is a schematic diagram of the temperature coefficient simulation results of the first-order curvature correction circuit.

[0037] The accompanying drawings in the specification are numeraled as follows:

[0038] Bandgap core circuit: 100, common mode feedback circuit: 200, high-order curvature correction circuit: 300;

[0039] First operational amplifier: A1, second operational amplifier: A2, third operational amplifier: A3, fourth operational amplifier: A4;

[0040] The first MOS tube: M1, the second MOS tube: M2, the third MOS tube: M3, the fourth MOS tube: M4, the fifth MOS tube: M5, the sixth MOS tube: M6, the seventh MOS tube: M7, the eighth MOS tube: M8;

[0041] The first transistor: Q1_1-Q1_8, the second transistor: Q2, the third transistor: Q3, the fourth transistor: Q4, the fifth transistor: Q5, the sixth transistor: Q6, the seventh transistor: Q7, the eighth transistor: Q8, the ninth transistor: Q9, the tenth transistor: Q10, the eleventh transistor: Q11, the twelfth transistor: Q12, the thirteenth transistor: Q13, the fourteenth transistor: Q14, the fifteenth transistor: Q15, the sixteenth transistor: Q16, the seventeenth transistor: Q17, the eighteenth transistor: Q18, the nineteenth transistor: Q19, the twenty-third transistor: Q20, the twenty-first transistor: Q21, the twenty-second transistor: Q22, the twenty-third transistor: Q23;

[0042] The first resistor: R1, the second resistor: R2, the third resistor: R3, the fourth resistor: R4, the fifth resistor: R5, the sixth resistor: R6, the seventh resistor: R7, the eighth resistor: R8, the ninth resistor: R9, and the tenth resistor: R10. DETAILED DESCRIPTION

[0043] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0044] See also Figure 1 , Figure 11 is a schematic diagram of a reference voltage source with a high-order curvature compensation function according to an embodiment of the present invention. The reference voltage source with a high-order curvature compensation function according to this embodiment includes a bandgap core circuit 100, a common-mode feedback circuit 200 and a high-order curvature correction circuit 300. The bandgap core circuit 100 is used to generate a reference voltage V REF The common mode feedback circuit 200 is used to generate a reference voltage V REF Generate a common mode voltage, and return the common mode voltage to the bandgap core circuit 100 through negative feedback to increase the stability of the bandgap core circuit 100; the high-order curvature correction circuit 300 is used to adjust the curvature of the bandgap core circuit 100 according to the reference voltage V REF Current is drawn or injected into the bandgap core circuit 100 to eliminate high-order errors in the bandgap core circuit 100 due to temperature.

[0045] Please continue reading Figure 1 The bandgap core circuit 100 includes an eighth MOS transistor M8, a second transistor Q2, a first operational amplifier A1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and N first transistors connected in parallel. Wherein, N is an integer greater than or equal to 1; the eighth MOS transistor M8 can be a PMOS transistor; the eight first transistors (Q1_1-Q1_8) and the second transistor Q2 can all be NPN transistors. The seventh resistor R7 and the eighth resistor R8 are generally of the same type and size.

[0046] In this embodiment, N=8 is used as an example for explanation, that is, a total of 8 first triodes are provided, namely triode Q1_1, triode Q1_2, triode Q1_3, triode Q1_4, triode Q1_5, triode Q1_6, triode Q1_7, and triode Q1_8, and the ratio of the sum of the saturation currents of the 8 first triodes (Q1_1-Q1_8) to the saturation current of the second triode Q2 is 8: 1. Of course, in other embodiments, N can also be other integers greater than or equal to 1. Alternatively, more than one second triode may be provided. In this case, the number of first triodes needs to be multiplied so that the ratio of the number of first triodes to the second triodes is maintained at N:1; for example, when the bandgap core circuit 100 is provided with two second triodes connected in parallel, 16 first triodes connected in parallel need to be provided to maintain the ratio of 8:1 in the present embodiment, which is substantially the same as providing one second triode and eight first triodes.

[0047] The source of the eighth MOS transistor M8 is connected to the power supply voltage VDD, the gate is electrically connected to the output end of the common-mode feedback circuit 200, and the drain is electrically connected to the first ends of the seventh resistor R7 and the eighth resistor R8 respectively; the second end of the seventh resistor R7 is electrically connected to the inverting input end of the first operational amplifier A1 and the collectors of the eight first transistors (Q1_1-Q1_8) respectively; the second end of the eighth resistor R8 is electrically connected to the non-inverting input end of the first operational amplifier A1 and the collector of the second transistor Q2 respectively; the base of the second transistor Q2 and the bases of the eight first transistors (Q1_1-Q1_8) are both electrically connected to the output end of the first operational amplifier A1.

[0048] The non-inverting input terminal of the first operational amplifier A1 is electrically connected to the first input terminal of the common-mode feedback circuit 200, and the inverting input terminal of the first operational amplifier A1 is electrically connected to the second input terminal of the common-mode feedback circuit 200; the output terminal of the first operational amplifier A1 is used to generate a reference voltage V REF The output terminal of the first operational amplifier A1 is electrically connected to the third input terminal of the common-mode feedback circuit 200 and the input terminal of the high-order curvature correction circuit 300 respectively.

[0049] The emitters of the eight first transistors (Q1_1-Q1_8) are all electrically connected to the first end of the ninth resistor R9, and the emitter of the second transistor Q2 is electrically connected to the second end of the ninth resistor R9; the second end of the ninth resistor R9 is grounded through the tenth resistor R10, and the second end of the ninth resistor R9 is also electrically connected to the correction end of the high-order curvature correction circuit 300.

[0050] Please continue reading Figure 1 The common-mode feedback circuit 200 includes a second operational amplifier A2, a first input terminal of the second operational amplifier A2 being electrically connected to the non-inverting input terminal of the first operational amplifier A1 as the first input terminal of the common-mode feedback circuit 200, a second input terminal of the second operational amplifier A2 being electrically connected to the inverting input terminal of the first operational amplifier A1 as the second input terminal of the common-mode feedback circuit 200, a third input terminal of the second operational amplifier A2 being electrically connected to the output terminal of the first operational amplifier A1 as the third input terminal of the common-mode feedback circuit 200, and an output terminal of the second operational amplifier A2 being electrically connected to the gate of the eighth MOS transistor M8 as the output terminal of the common-mode feedback circuit 200.

[0051] See also Figure 2The high-order curvature correction circuit 300 includes a third operational amplifier A3, a fourth operational amplifier A4, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a third triode Q3, a fourth triode Q4, a fifth triode Q5, a sixth triode Q6, a seventh triode Q7, an eighth triode Q8, a ninth triode Q9, a tenth triode Q10, and an eleventh triode Q11. transistor Q11, the twelfth triode Q12, the thirteenth triode Q13, the fourteenth triode Q14, the fifteenth triode Q15, the sixteenth triode Q16, the seventeenth triode Q17, the eighteenth triode Q18, the nineteenth triode Q19, the twenty-third triode Q20, the twenty-first triode Q21, the twenty-second triode Q22, the twenty-third triode Q23, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6.

[0052] The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 can all be PMOS transistors. The third triode Q3, the fourth triode Q4, the eighth triode Q8, the ninth triode Q9, the tenth triode Q10, the twelfth triode Q12, the fifteenth triode Q15, the sixteenth triode Q16, the seventeenth triode Q17, the eighteenth triode Q18, the twenty-third triode Q20 and the twenty-second triode Q22 can all be PNP triodes. The fifth triode Q5, the sixth triode Q6, the seventh triode Q7, the eleventh triode Q11, the thirteenth triode Q13, the fourteenth triode Q14, the nineteenth triode Q19, the twenty-first triode Q21 and the twenty-third triode Q23 can all be NPN triodes.

[0053] The emitter area ratio of the third transistor Q3, the fourth transistor Q4 and the tenth transistor Q10 is generally 4:1:1; the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is generally 2:1:1; the emitter area ratio of the eighth transistor Q8, the seventeenth transistor Q17, the eighteenth transistor Q18 and the twenty-third transistor Q20 is generally 2:1:1:4; the emitter area ratio of the ninth transistor Q9, the fifteenth transistor Q15 and the sixteenth transistor Q16 is generally 2:1:1; the emitter area ratio of the twelfth transistor Q8, the seventeenth transistor Q17, the eighteenth transistor Q18 and the twenty-third transistor Q20 is generally 2:1:1:4; the emitter area ratio of the ninth transistor Q9, the fifteenth transistor Q15 and the sixteenth transistor Q16 is generally 2:1:1; The emitter area ratio of the transistor Q12 to the twenty-second transistor Q22 is generally 1:2; the emitter area ratio of the fourteenth transistor Q14 to the twenty-first transistor Q21 is generally 1:4; the width-to-length ratio of the first MOS transistor M1, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 is generally 2:1:1:4; the width-to-length ratio of the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 is generally 2:1:1; the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are generally 4 times the resistance value of the sixth resistor R6.

[0054] The non-inverting input terminal of the third operational amplifier A3, the non-inverting input terminal of the fourth operational amplifier A4 and the base of the twenty-third triode Q23 are all electrically connected to the output terminal of the first operational amplifier A1, the emitter of the twenty-third triode Q23 is grounded through the first resistor R1, the inverting input terminal of the third operational amplifier A3 is respectively electrically connected to the collector of the twenty-second triode Q22 and the collector of the twenty-third triode Q23, the output terminal of the third operational amplifier A3 is respectively electrically connected to the base of the twelfth triode Q12 and the base of the twenty-second triode Q22, and the emitter of the twelfth triode Q12 and the emitter of the twenty-second triode Q22 are both connected to the power supply voltage VDD.

[0055] The inverting input terminal of the fourth operational amplifier A4 is grounded through the second resistor R2, and the output terminal of the fourth operational amplifier A4 is electrically connected to the base of the third triode Q3, the base of the fourth triode Q4 and the base of the tenth triode Q10 respectively; the emitter of the third triode Q3, the emitter of the fourth triode Q4 and the emitter of the tenth triode Q10 are all connected to the power supply voltage VDD, and the collector of the third triode Q3 is electrically connected to the inverting input terminal of the fourth operational amplifier A4.

[0056] The collector of the fourth triode Q4 is electrically connected to the collector of the fifth triode Q5, the base of the fifth triode Q5, the base of the sixth triode Q6 and the base of the seventh triode Q7 respectively, and the emitter of the fifth triode Q5, the emitter of the sixth triode Q6 and the emitter of the seventh triode Q7 are all grounded; the collector of the sixth triode Q6 is electrically connected to the collector of the seventh triode Q7 through the third resistor R3.

[0057] The collector of the sixth triode Q6 is also electrically connected to the drain of the first MOS tube M1 and the base of the thirteenth triode Q13 respectively, the gate of the first MOS tube M1 is electrically connected to the gate of the sixth MOS tube M6, the drain of the sixth MOS tube M6 and the gate of the seventh MOS tube M7 respectively, the source of the first MOS tube M1 is electrically connected to the collector of the eighth triode Q8, the base of the eighth triode Q8 is electrically connected to the base of the seventeenth triode Q17, the collector of the seventeenth triode Q17, the base of the eighteenth triode Q18 and the base of the twenty-third triode Q20 respectively, and the emitter of the eighth triode Q8, the emitter of the seventeenth triode Q17, the emitter of the eighteenth triode Q18 and the emitter of the twenty-third triode Q20 are all connected to the power supply voltage VDD.

[0058] The collector of the seventh triode Q7 is also electrically connected to the drain of the second MOS tube M2 and the base of the eleventh triode Q11 respectively, the gate of the second MOS tube M2 is electrically connected to the gate of the third MOS tube M3 and the drain of the third MOS tube M3 respectively, the source of the second MOS tube M2 is electrically connected to the collector of the ninth triode Q9, the base of the ninth triode Q9 is electrically connected to the base of the fifteenth triode Q15, the base of the sixteenth triode Q16 and the collector of the sixteenth triode Q16 respectively, the emitter of the ninth triode Q9, the emitter of the fifteenth triode Q15 and the emitter of the sixteenth triode Q16 are all connected to the power supply voltage VDD, and the source of the third MOS tube M3 is electrically connected to the collector of the fifteenth triode Q15.

[0059] The emitter of the thirteenth triode Q13 is grounded, the collector of the thirteenth triode Q13 is electrically connected to the collector of the twelfth triode Q12 and the base of the nineteenth triode Q19 respectively, the emitter of the nineteenth triode Q19 is grounded through the fifth resistor R5, the collector of the nineteenth triode Q19 is electrically connected to the gate of the fifth MOS tube M5 and the gate of the sixth MOS tube M6 respectively; the drain of the fifth MOS tube M5 is grounded, the source of the fifth MOS tube M5 is electrically connected to the collector of the seventeenth triode Q17, and the source of the sixth MOS tube M6 is electrically connected to the collector of the eighteenth triode Q18.

[0060] The emitter of the eleventh triode Q11 is grounded, the collector of the eleventh triode Q11 is electrically connected to the collector of the tenth triode Q10, the base of the fourteenth triode Q14 and the base of the twenty-first triode Q21 respectively, the emitter of the fourteenth triode Q14 is grounded through the fourth resistor R4, the collector of the fourteenth triode Q14 is electrically connected to the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4 respectively; the drain of the fourth MOS tube M4 is grounded, and the source of the fourth MOS tube M4 is electrically connected to the collector of the sixteenth triode Q16.

[0061] The emitter of the twenty-first transistor Q21 is grounded through the sixth resistor R6, the collector of the twenty-first transistor Q21 is electrically connected to the drain of the seventh MOS transistor M7, the drain of the seventh MOS transistor M7 is electrically connected to the second end of the ninth resistor R9 as the correction end of the high-order curvature correction circuit 300, and the source of the seventh MOS transistor M7 is electrically connected to the collector of the twenty-third transistor Q20.

[0062] The working principle of this embodiment is as follows:

[0063] See also Figure 1 and Figure 2 When the high-order curvature correction circuit 300 injects current into the bandgap core circuit 100, the reference voltage V generated by the bandgap core circuit 100 REF The expression is as follows:

[0064]

[0065] Among them, V BE Represents the voltage between the base and emitter of the second transistor Q2; V T represents thermal voltage; N represents the ratio of the number of the first transistor to the number of the second transistor, that is; I IN represents the current value of the injection current of the high-order curvature correction circuit 300.

[0066] When the high-order curvature correction circuit 300 draws current from the bandgap core circuit 100, the reference voltage V generated by the bandgap core circuit 100 REF The expression is as follows:

[0067]

[0068] Among them, I OUT represents the current value drawn by the high-order curvature correction circuit 300.

[0069] Thermal voltage V T It is the potential difference caused by the temperature difference between two points in a closed circuit, also known as the voltage equivalent of temperature; its calculation formula is as follows:

[0070]

[0071] Among them, k represents the Boltzmann constant; T represents the actual ambient temperature (T is the thermodynamic temperature, the unit is K); q represents the charge of the electron.

[0072] V BE The expression is as follows:

[0073]

[0074] Among them, V g0 Indicates V when the temperature is 0K BE The value of; T0 represents the selected temperature; V BE (T0) indicates the temperature V when T0 BE The value of; η, m are process-related constants that do not change with temperature.

[0075] according to Figure 2 It can be seen that since the in-phase input terminals of the third operational amplifier A3 and the fourth operational amplifier A4 are connected to the reference voltage V output by the bandgap core circuit 100, REF , then the current I flowing through the first resistor R1 PTAT for:

[0076]

[0077] The current I flowing through the second resistor R2 REF for:

[0078]

[0079] Among them, V BE23 It represents the voltage between the base and the emitter of the twenty-third transistor Q23. REF With zero temperature coefficient, V BE has a negative temperature coefficient, so I PTAT Has a positive temperature coefficient, I REF Has zero temperature coefficient.

[0080] Since the emitter area of ​​the 22nd transistor Q22 is twice the emitter area of ​​the 12th transistor Q12, the current flowing through the 12th transistor Q12 and the 13th transistor Q13 is I PTAT / 2, the voltage V at the base point A of the thirteenth transistor Q13 A for:

[0081]

[0082] Among them, I S13represents the current flowing through the thirteenth triode Q13 (i.e., the current of the collector or emitter of the thirteenth triode Q13); since the emitter area ratio of the third triode Q3, the fourth triode Q4 and the tenth triode Q10 is 4:1:1, the current flowing through the fourth triode Q4, the fifth triode Q5, the tenth triode Q10 and the eleventh triode Q11 is I REF / 4, the voltage V at the base voltage point B of the eleventh transistor Q11 B for

[0083]

[0084] Among them, I S11 It represents the current flowing through the eleventh transistor Q11.

[0085] The current flowing through the twenty-third transistor Q20 and the seventh MOS transistor M7 is marked as I1. Since the emitter area ratio of the eighth transistor Q8, the seventeenth transistor Q17, the eighteenth transistor Q18 and the twenty-third transistor Q20 is 2:1:1:4, and the width-to-length ratio of the first MOS transistor M1, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 is 2:1:1:4, the current flowing through the eighteenth transistor Q18, the seventeenth transistor Q17, the fifth MOS transistor M5, the sixth MOS transistor M6, the nineteenth transistor Q19 and the fifth resistor R5 is I1 / 4. Since the resistance of the fifth resistor R5 is 4 times that of the sixth resistor R6, the current flowing through the eighth transistor Q8 and the first MOS transistor M1 is I1 / 2.

[0086] The current flowing through the twenty-first transistor Q21 and the sixth resistor R6 is marked as I2. Since the emitter area ratio of the fourteenth transistor Q14 to the twenty-first transistor Q21 is 1:4, and the resistance ratio of the fourth resistor R4 to the sixth resistor R6 is 4:1, the current flowing through the fourteenth transistor Q14, the fourth resistor R4, the third MOS transistor M3, and the fifteenth transistor Q15 is I2 / 4. Since the emitter area ratio of the ninth transistor Q9, the fifteenth transistor Q15, and the sixteenth transistor Q16 is 2:1:1, and the width-to-length ratio of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 is 2:1:1, the current flowing through the sixteenth transistor Q16 and the fourth MOS transistor M4 is I2 / 4, and the current flowing through the ninth transistor Q9 and the second MOS transistor M2 is I2 / 2.

[0087] If I PTAT / 2<I REF / 4, then the voltage at point B is higher than that at point A, and the current I flowing from point B to point A BA for

[0088]

[0089] Since the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is 2:1:1, the currents flowing through the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are I REF / 4、I REF / 8 and I REF / 8, then

[0090] I REF / 8 ＝ I1 / 2+I BA

[0091] I2 / 2 ＝ I REF / 8+I BA

[0092] Calculated

[0093]

[0094] The current I drawn from the bandgap core circuit 100 OUT for

[0095]

[0096] The reference voltage V output by the bandgap core circuit 100 REF for

[0097]

[0098] Will I PTAT and I REF Substituting in, we get

[0099]

[0100] The second and third terms in the above formula are linear terms of temperature, and the fourth term is a high-order term of temperature. It can be seen that by adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the ninth resistor R9 and the tenth resistor R10, V BE The temperature second-order term in V can be offset by adjusting the resistance values ​​of the third resistor R3 and the tenth resistor R10. BE The temperature higher-order terms in .

[0101] If I PTAT / 2>I REF / 4, then the voltage at point A is higher than that at point B, and the current I flowing from point A to point B is BA for

[0102]

[0103] Since the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is 2:1:1, the currents flowing through the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are I REF / 4、I REF / 8 and I REF / 8, then

[0104] I REF / 8 ＝ I1 / 2-I BA

[0105] I2 / 2 ＝ I REF / 8-I BA

[0106] Calculated

[0107]

[0108] The current I injected into the bandgap core circuit 100 IN for

[0109]

[0110] The reference voltage V output by the bandgap core circuit 100 REF for

[0111]

[0112] Will I PTAT and I REF Substituting in, we get

[0113]

[0114] The second and third terms in the above formula are linear terms of temperature, and the fourth term is a high-order term of temperature. It can be seen that by adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the ninth resistor R9 and the tenth resistor R10, V BE The temperature second-order term in V can be offset by adjusting the resistance values ​​of the third resistor R3 and the tenth resistor R10. BE The temperature higher-order terms in .

[0115] In summary, if I PTAT / 2≠I REF / 4, the circuit structure of this embodiment can be used to achieve high-order curvature compensation correction.

[0116] This embodiment also uses SMIC 0.35um CMOS process to carry out simulation, and the reference voltage after high-order curvature compensation is simulated. The simulation results are as follows: Figure 3As shown in FIG4 , the output voltage deviation is only 401uV in the range of -55°C to 125°C, and the temperature coefficient is 1.84ppm / °C. The simulation results of the first-order curvature correction circuit are shown in FIG4 , and the output voltage deviation is 3.45mV in the range of -55°C to 125°C, and the temperature coefficient is 15.4ppm / °C. This shows that the temperature characteristics of the reference voltage are greatly improved by using the high-order curvature correction circuit 300 proposed in this embodiment.

[0117] In this embodiment, a new high-order curvature correction technology is proposed, which can perform high-order curvature compensation on temperature, thereby effectively improving the accuracy of the output reference voltage, reducing the temperature coefficient, and improving the temperature stability of the reference voltage. At the same time, the circuit structure of this embodiment is simple, the chip area occupied is small, and it has high practicality.

[0118] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A reference voltage source with a high-order curvature compensation function, characterized in that: include Bandgap core circuit for generating reference voltage V REF ; The common-mode feedback circuit is used to REF Generate a common mode voltage, and return the common mode voltage to the bandgap core circuit through negative feedback to increase the stability of the bandgap core circuit; as well as A high-order curvature correction circuit is used to adjust the curvature according to the reference voltage V REF Current is extracted or injected into the bandgap core circuit to remove higher-order errors caused by temperature in the bandgap core circuit.

2. The reference voltage source with high-order curvature compensation function as claimed in claim 1, characterized in that: The bandgap core circuit includes an eighth MOS transistor, a second triode, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and N first triodes connected in parallel, wherein N is an integer greater than or equal to 1; The source of the eighth MOS transistor is connected to the external power supply voltage, the gate is electrically connected to the output end of the common-mode feedback circuit, and the drain is electrically connected to the first ends of the seventh resistor and the eighth resistor respectively; the second end of the seventh resistor is electrically connected to the inverting input end of the first operational amplifier and the collectors of the N first transistors respectively; the second end of the eighth resistor is electrically connected to the non-inverting input end of the first operational amplifier and the collector of the second transistor respectively; the base of the second transistor and the bases of the N first transistors are both electrically connected to the output end of the first operational amplifier; The non-inverting input terminal of the first operational amplifier is electrically connected to the first input terminal of the common-mode feedback circuit, and the inverting input terminal of the first operational amplifier is electrically connected to the second input terminal of the common-mode feedback circuit; the output terminal of the first operational amplifier is used to generate a reference voltage V REF , the output end of the first operational amplifier is electrically connected to the third input end of the common mode feedback circuit and the input end of the high-order curvature correction circuit respectively; The emitters of the N first transistors are all electrically connected to the first end of the ninth resistor, and the emitter of the second transistor is electrically connected to the second end of the ninth resistor; the second end of the ninth resistor is grounded through the tenth resistor, and the second end of the ninth resistor is also electrically connected to the correction end of the high-order curvature correction circuit.

3. The reference voltage source with high-order curvature compensation function as claimed in claim 2, characterized in that: The eighth MOS tube is a PMOS tube; the second transistor and the N first transistors are all NPN transistors.

4. The reference voltage source with high-order curvature compensation function as claimed in claim 2, characterized in that: The seventh resistor and the eighth resistor are of the same type and size.

5. The reference voltage source with high-order curvature compensation function as claimed in claim 2, characterized in that: The ratio of the sum of the saturation currents of the N first triodes to the saturation current of the second triode is N:

1.

6. The reference voltage source with high-order curvature compensation function as claimed in claim 2, characterized in that: The emitter area of ​​each of the first transistors is the same as the emitter area of ​​the second transistors.

7. The reference voltage source with high-order curvature compensation function according to any one of claims 2 to 6, characterized in that: The common-mode feedback circuit includes a second operational amplifier, a first input terminal of the second operational amplifier being electrically connected to the non-inverting input terminal of the first operational amplifier as the first input terminal of the common-mode feedback circuit, a second input terminal of the second operational amplifier being electrically connected to the inverting input terminal of the first operational amplifier as the second input terminal of the common-mode feedback circuit, a third input terminal of the second operational amplifier being electrically connected to the output terminal of the first operational amplifier as the third input terminal of the common-mode feedback circuit, and an output terminal of the second operational amplifier being electrically connected to the gate of the eighth MOS tube as the output terminal of the common-mode feedback circuit.

8. The reference voltage source with high-order curvature compensation function as claimed in claim 7, characterized in that: The high-order curvature correction circuit includes a third operational amplifier, a fourth operational amplifier, a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode, a tenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode, a sixteenth triode, a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twenty-third triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The non-inverting input terminal of the third operational amplifier, the non-inverting input terminal of the fourth operational amplifier and the base of the twenty-third triode are all electrically connected to the output terminal of the first operational amplifier, the emitter of the twenty-third triode is grounded through a first resistor, the inverting input terminal of the third operational amplifier is electrically connected to the collector of the twenty-second triode and the collector of the twenty-third triode respectively, the output terminal of the third operational amplifier is electrically connected to the base of the twelfth triode and the base of the twenty-second triode respectively, and the emitter of the twelfth triode and the emitter of the twenty-second triode are both connected to an external power supply voltage; The inverting input terminal of the fourth operational amplifier is grounded through a second resistor, and the output terminal of the fourth operational amplifier is electrically connected to the base of the third triode, the base of the fourth triode, and the base of the tenth triode respectively; the emitter of the third triode, the emitter of the fourth triode, and the emitter of the tenth triode are all connected to an external power supply voltage, and the collector of the third triode is electrically connected to the inverting input terminal of the fourth operational amplifier; The collector of the fourth triode is electrically connected to the collector of the fifth triode, the base of the fifth triode, the base of the sixth triode and the base of the seventh triode respectively, and the emitter of the fifth triode, the emitter of the sixth triode and the emitter of the seventh triode are all grounded; the collector of the sixth triode is electrically connected to the collector of the seventh triode through a third resistor; The collector of the sixth triode is also electrically connected to the drain of the first MOS tube and the base of the thirteenth triode respectively, the gate of the first MOS tube is electrically connected to the gate of the sixth MOS tube, the drain of the sixth MOS tube and the gate of the seventh MOS tube respectively, the source of the first MOS tube is electrically connected to the collector of the eighth triode, the base of the eighth triode is electrically connected to the base of the seventeenth triode, the collector of the seventeenth triode, the base of the eighteenth triode and the base of the twenty-third triode respectively, and the emitter of the eighth triode, the emitter of the seventeenth triode, the emitter of the eighteenth triode and the emitter of the twenty-third triode are all connected to the external power supply voltage; The collector of the seventh triode is also electrically connected to the drain of the second MOS tube and the base of the eleventh triode respectively, the gate of the second MOS tube is electrically connected to the gate of the third MOS tube and the drain of the third MOS tube respectively, the source of the second MOS tube is electrically connected to the collector of the ninth triode, the base of the ninth triode is electrically connected to the base of the fifteenth triode, the base of the sixteenth triode and the collector of the sixteenth triode respectively, the emitter of the ninth triode, the emitter of the fifteenth triode and the emitter of the sixteenth triode are all connected to the external power supply voltage, and the source of the third MOS tube is electrically connected to the collector of the fifteenth triode; The emitter of the thirteenth triode is grounded, the collector of the thirteenth triode is electrically connected to the collector of the twelfth triode and the base of the nineteenth triode respectively, the emitter of the nineteenth triode is grounded through a fifth resistor, the collector of the nineteenth triode is electrically connected to the gate of the fifth MOS tube and the gate of the sixth MOS tube respectively; the drain of the fifth MOS tube is grounded, the source of the fifth MOS tube is electrically connected to the collector of the seventeenth triode, and the source of the sixth MOS tube is electrically connected to the collector of the eighteenth triode; The emitter of the eleventh triode is grounded, the collector of the eleventh triode is electrically connected to the collector of the tenth triode, the base of the fourteenth triode and the base of the twenty-first triode respectively, the emitter of the fourteenth triode is grounded through a fourth resistor, the collector of the fourteenth triode is electrically connected to the gate of the third MOS tube and the gate of the fourth MOS tube respectively; the drain of the fourth MOS tube is grounded, and the source of the fourth MOS tube is electrically connected to the collector of the sixteenth triode; The emitter of the twenty-first transistor is grounded through the sixth resistor, the collector of the twenty-first transistor is electrically connected to the drain of the seventh MOS transistor, the drain of the seventh MOS transistor is electrically connected to the second end of the ninth resistor as the correction end of the high-order curvature correction circuit, and the source of the seventh MOS transistor is electrically connected to the collector of the twenty-third transistor.

9. The reference voltage source with high-order curvature compensation function as claimed in claim 8, characterized in that: The first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are all PMOS tubes; The third triode, the fourth triode, the eighth triode, the ninth triode, the tenth triode, the twelfth triode, the fifteenth triode, the sixteenth triode, the seventeenth triode, the eighteenth triode, the twenty-third triode and the twenty-second triode are all PNP triodes; The fifth triode, the sixth triode, the seventh triode, the eleventh triode, the thirteenth triode, the fourteenth triode, the nineteenth triode, the twenty-first triode and the twenty-third triode are all NPN triodes.

10. The reference voltage source with high-order curvature compensation function as claimed in claim 8, characterized in that: The emitter area ratio of the third triode, the fourth triode and the tenth triode is 4:1:1; the emitter area ratio of the fifth triode, the sixth triode and the seventh triode is 2:1:1; the emitter area ratio of the eighth triode, the seventeenth triode, the eighteenth triode and the twenty-third triode is 2:1:1:4; the emitter area ratio of the ninth triode, the fifteenth triode and the sixteenth triode is 2:1:1; the emitter area ratio of the twelfth triode and the twenty-second triode is 1:2; the emitter area ratio of the fourteenth triode and the twenty-first triode is 1:4; the width-to-length ratio of the first MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube is 2:1:1:4; the width-to-length ratio of the second MOS tube, the third MOS tube and the fourth MOS tube is 2:1:1; the resistance values ​​of the fourth resistor and the fifth resistor are both 4 times the resistance value of the sixth resistor.

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