Storage device

Abstract

In a storage device capable of improving I / O performance while reducing data retention cost by improving data reduction rate, a processor receives first updated write data of a part of a first logical address region with respect to first compressed data of the first logical address region compressed by basic compression units; in order to compress the first update write data, the accelerator instruction is compressed in a size smaller than the basic compression unit. Merging the non-updated data of the first logical address region decompressed by the accelerator and the first updated write data to generate uncompressed data of the basic compression unit; the accelerator is instructed to compress the uncompressed data in a basic compression unit.

Description

Technical Field

[0001] The present invention relates to a storage device that reduces the amount of stored data by compression. Background Art

[0002] In recent years, technologies such as IoT (Internet of Things) and AI (Artificial Intelligence) that analyze large amounts of data to generate new value are becoming more and more popular. Storage devices that store large amounts of data require lower data retention costs (price per unit capacity) and higher I / O (Input / Output) performance.

[0003] The data retention cost is calculated by multiplying the low bit cost (price per unit capacity) by the amount of data to be stored. Compression is a technique for reducing the data retention cost by reducing the amount of data to be stored. Compression reduces the amount of data by replacing the bit sequence of data with a shorter bit sequence through coding.

[0004] Patent Document 1 discloses a storage system that uses a larger compression unit to compress data to be written by a host together in order to improve the effect of reducing the amount of data.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: U.S. Patent Publication No. 2022 / 0121402 Summary of the invention

[0008] Problems to be solved by the invention

[0009] The reversible compression algorithm used in the storage device is generally a sliding dictionary method. In this method, the larger the compression unit, the larger the dictionary exploration space becomes. The probability of finding consistent data from a larger dictionary exploration space increases, and the data reduction effect becomes higher. For example, when there is a data column ABABABCD, if the compression unit is a length of 4, it is divided into data column ABAB and data column ABCD for compression. At this time, the data column ABAB can be encoded as two repetitions of the dictionary data AB. However, the data column ABCD cannot be encoded. On the other hand, if the compression unit is a length of 8, the data column ABABABCD can be encoded as three repetitions of the dictionary data AB and the data column CD.

[0010] Patent Document 1 discloses a method in which a storage device compresses data to be written by a host using a larger compression unit to improve data reduction effect, but does not consider how to process the compressed data when the host updates only a part of the compressed data.

[0011] Means used to solve problems

[0012] A storage device of a technical solution of the present invention includes: a processor; and an accelerator, which performs data compression and decompression; the processor receives first updated write data of a part of the first logical address area for the first compressed data of the first logical address area compressed by the basic compression unit; the processor instructs the accelerator to compress the first updated write data with a size smaller than the basic compression unit in order to compress the first updated write data; the accelerator compresses the first updated write data with the smaller size; the processor merges the non-updated data of the first logical address area decompressed by the accelerator and the first updated write data to generate uncompressed data of the basic compression unit; the processor instructs the accelerator to compress the uncompressed data with the basic compression unit.

[0013] Effects of the Invention

[0014] According to a technical solution of the present invention, the data reduction rate can be increased to reduce the data retention cost and improve the I / O performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram showing the concept of compression processing for host writes with a data length shorter than the compression unit.

[0016] Figure 2 This is a diagram showing the concept of garbage collection processing for compressed data in which a portion of the data is in a garbage state.

[0017] Figure 3 This is a diagram showing the concept of integrated processing (intensive processing) of compressed data.

[0018] Figure 4 It is a diagram showing the structure of a storage device.

[0019] Figure 5 This is a diagram showing the structure of compressed data management information.

[0020] Figure 6 is a flowchart showing the compression process.

[0021] Figure 7 This is a flowchart showing the useless data collection process.

[0022] Figure 8 is a flow chart showing the integration process of compressed data.

[0023] Fig. 9 This is a flowchart showing the data merging process within the logical address range.

[0024] Fig.10 This is a flowchart showing the garbage collection process for implementing left-aligned recompression.

[0025] Fig.11 This is a flowchart showing a useless data collection process for implementing the integration (aggregation) of compressed data.

[0026] Fig.12 This is a flowchart showing the compression process of switching the compression unit.

[0027] Description of Figure Numbers

[0028] 1…storage controller; 2…processor; 3…accelerator; 4…memory; 5…storage medium; 6…storage device; 7…host; 8…host I / F; 10…compressed data management information; 11…logical address; 12…physical address; 13…compressed data size; 14…offset within the logical address; 15…physical address according to the offset; 16…compressed data size according to the offset. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. However, the present invention is not limited to the description of the embodiments shown below. It is easy for a person skilled in the art to understand that the specific configuration can be changed without departing from the scope of the idea or purpose of the present invention.

[0030] The expressions “first”, “second”, “third”, etc. in this specification are provided to identify components, and do not necessarily limit the number or order.

[0031] In the configuration of the invention described below, the same or similar configurations or functions are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0032] In the following description, when describing the same kind of elements without distinguishing them, common reference numerals (or reference numerals) are used, and when describing the same kind of elements by distinguishing them, reference numerals (or element IDs) may be used.

[0033] In the following description, "main memory" may be one or more storage devices including a memory. For example, the main memory may be at least one of a main storage device (typically a volatile storage device) and an auxiliary storage device (typically a non-volatile storage device). In addition, the storage unit may also include at least one of a cache area (e.g., a cache memory or a part thereof) and a buffer area (e.g., a buffer memory or a part thereof).

[0034] In the following description, "LUN" refers to a logical storage device or volume, which is mapped to a storage area of ​​a part or all of a pool. That is, a LUN is composed of a storage area of ​​a part or all of a pool. The host performs an I / O (Input / Output) request for a "LUN". A LUN is a logical volume. The allocation of storage areas between a LUN and a storage drive is managed via a pool.

[0035] The program is executed by a processor (e.g., CPU (Central Processing Unit)) included in the storage controller, thereby performing the set processing while appropriately using storage resources (e.g., main memory) and / or communication interface devices (e.g., HCA), so the subject of the processing can be the storage controller or the processor. In addition, the storage controller can also include a part or all of the hardware circuits that perform the processing. The computer program can also be installed from a program source. The program source can be, for example, a program distribution server or a computer-readable storage medium.

[0036] In the following description, a "host" is a system that sends I / O requests to a storage device, and may include an interface device, a storage unit (e.g., memory), and a processor connected to them. A host system may also be composed of more than one host computer. At least one host computer may be a physical computer, and a host system may include a virtual host computer in addition to a physical host computer.

[0037] First, an example of an operation envisioned as a compression process of a storage device when a host writes data smaller than a compression unit (hereinafter referred to as a basic compression unit) specified by the storage device to the storage device is described. In order to maintain a high data reduction rate regardless of the size of the write data received from the host, the storage device attempts to compress the data in the basic compression unit. This is achieved, for example, by the following steps.

[0038] The storage device reads out the compressed data including the write data from the storage medium in the storage device and decompresses it. Then, the storage device merges the received write data with the decompressed data so that the size of the write data is consistent with the basic compression unit. Then, the storage device compresses the write data in the basic compression unit and writes it to the storage medium. In this way, when the size of the write data is smaller than the basic compression unit, the storage device uses the data in the compressed data to complete the write data, so that the storage device can compress the write data in the basic compression unit.

[0039] However, in this assumed operation, the storage device not only compresses the write data received from the host, but also reads, decompresses, and merges the compressed data from the storage medium. As the storage device processes more, the I / O performance decreases.

[0040] Hereinafter, compression processing for preventing the above-mentioned decrease in write performance will be described in each embodiment.

[0041] [Example 1]

[0042] The present invention describes a mode in which a storage device compresses data in the size of the written data and saves the data in a storage medium when the size of the host write data is smaller than the basic compression unit. This embodiment performs compression processing, useless data collection processing, and compressed data integration processing. According to this embodiment, the useless data collection processing and the compressed data integration processing are performed asynchronously with the host write, and the written data is recompressed in the basic compression unit of the storage device, thereby improving the I / O performance of the host write whose size is smaller than the basic compression unit.

[0043] First, use Figure 1 This section describes the outline of the compression process. Figure 1 In the example, the host 7 writes data A, data B, data C, and data D, and the storage device 6 compresses them in basic compression units to generate compressed data abcd and stores them in the storage medium 5.

[0044] Figure 1 The following figure shows the operation of the compression process S1 when the host 7 sends update write data E to the location of data B. When the storage device 6 receives the update write data E from the host 7 , it stores the write data E in the memory 4 in the storage controller 1 in the storage device 6 .

[0045] The processor 2 recognizes that the size of the update write data E is smaller than the basic compression unit, and instructs the accelerator 3 to compress the update write data E with the size of the update write data E. The accelerator 3 reads and compresses the update write data E from the memory 4, and stores the compressed data e in the memory 4. The processor 2 stores the compressed data e in the storage medium 5. Here, the processor 2 records in the management information that the data B before writing becomes unnecessary data (called useless data, garbage).

[0046] Next, use Figure 2 The outline of the useless data collection process S10 is described below. Figure 2 In the Figure 1 The useless data B recorded by the compression process S1 in the storage medium 5 is deleted, and the area of ​​the storage medium 5 is released. The processor 2 reads the compressed data abcd including the useless data B from the storage medium 5 and stores it in the memory 4.

[0047] Next, the processor 2 instructs the accelerator 3 to decompress the compressed data abcd. The accelerator 3 reads the compressed data abcd in the memory 4, decompresses it, and saves the data sequence ABCD in the memory 4. In addition, the processor 2 writes zero data at the location of the useless data B, and updates the data sequence A0CD consisting of the non-updated data A, C, D and 0 data.

[0048] The processor 2 instructs the accelerator 3 to compress the data sequence A0CD. The accelerator 3 reads the data sequence A0CD from the memory 4, compresses it, and stores the compressed data a0cd in the memory 4. Then, the processor 2 stores the compressed data a0cd in the storage medium 5 and deletes the compressed data abcd in the storage medium 5. In this way, the useless data B is deleted.

[0049] Finally, use Figure 3 The following describes the outline of the compressed data integration process S30. Figure 3 , it is shown that the data reduction effect is maintained high by collecting the compressed data e and the compressed data a0cd and replacing them with the compressed data aecd obtained based on the basic compression unit.

[0050] The processor reads out the compressed data e and the compressed data a0cd which cannot be compressed in the basic compression unit from the storage medium 5 and stores them in the memory 4. The processor 2 instructs the accelerator 3 to decompress the compressed data e and the compressed data a0cd. The accelerator 3 reads out and decompresses the compressed data e and the compressed data a0cd, respectively, and stores the data E and the data sequence A0cd in the memory 4, respectively. In addition, the decompression instruction issued from the processor 2 to the accelerator 3 may also be divided into two times.

[0051] Processor 2 combines data E with data sequence A0CD to generate data sequence AECD, and instructs accelerator 3 to compress. Accelerator 3 reads and compresses data sequence AECD, and stores compressed data aecd in memory 4. Processor 2 stores compressed data aecd in storage medium 5, and deletes compressed data e and compressed data a0cd in storage medium 5.

[0052] The above is an overview of the compression process S1, the useless data collection process S10, and the compressed data integration process S30. In addition, the compression and decompression processes may be executed by the processor 2 instead of the accelerator 3. The storage device 6 of the first embodiment will be described in detail below.

[0053] Figure 4 This is a diagram showing an example of the configuration of the storage device 6 according to the first embodiment.

[0054] The storage device 6 is connected to a host 7 providing a storage area via a network such as a SAN (Storage Area Network) or a LAN (Local Area Network). The host 7 is, for example, a personal computer or a smartphone.

[0055] The storage device 6 includes a storage controller 1 and a storage medium 5. The storage controller 1 executes processing corresponding to a command. The storage controller 1 includes a processor 2, an accelerator 3, a memory 4, and a host interface (I / F) 8. Each hardware is connected to each other via an internal network.

[0056] The host I / F 8 is an interface for connecting to the host 7. The host I / F 8 performs transmission and reception of commands and data between the storage device 6 and the host 7. The processor 2 executes a program stored in the memory 4. The processor 2 of the first embodiment functions as a calculation unit or a control unit that performs various processes according to commands.

[0057] The accelerator 3 executes compression processing and decompression processing according to the instruction of the processor 2. The accelerator 3 is hardware designed to execute compression processing and decompression processing at high speed, and is implemented by using, for example, FPGA (Field Programmable Gate Array).

[0058] The memory 4 is a storage device such as DRAM (Dynamic Random Access Memory), and stores programs executed by the processor 2 and information used by the programs. In addition, the memory 4 is also used as a work area used by the programs. The memory 4 can be either a volatile memory or a non-volatile memory.

[0059] The memory 4 of this embodiment stores the compressed data management information 10. In addition, the memory 4 stores the program (omitted from the figure) that realizes the operation unit or the control unit. Figure 5 The details of the compressed data management information 10 will be described.

[0060] The storage medium 5 is a non-volatile storage device. The storage medium 5 is, for example, a semiconductor storage device such as an SSD (Solid State Drive) or a hard disk drive. The storage medium 5 is connected to the storage controller 1 via an internal network, and performs the sending and receiving processing of commands between the processor 2 and the sending and receiving processing of data between the memory 4. In addition, the storage medium 5 is directly connected to the storage controller 1 via the internal network, but can also be connected to the storage controller 1 via an interface for the storage medium connected to the internal network.

[0061] Figure 5 1 is a diagram showing an example of compressed data management information 10 of Embodiment 1. The compressed data management information 10 is information for managing compressed data. The compressed data management information 10 stores entries consisting of a logical address 11, a physical address 12, a compressed data size 13, an offset 14 within the logical address, a physical address 15 by the offset, and a compressed data size 16 by the offset. One entry has a plurality of offsets 14 within the logical address, physical addresses 15 by the offset, and compressed data sizes 16 by the offset. One entry corresponds to one compressed data compressed in a basic compression unit.

[0062] The logical address 11 is a field for storing the logical address indicating the storage location of the data column in the volume provided to the host 7. The compression unit is managed by the logical address. For example, when the compression unit is 32KB, 32KB of data of consecutive logical addresses are compressed together. The combination of logical addresses constituting each compression unit is certain. The logical address 11 indicates the starting address of the compression unit. The physical address 12 is a field for storing the address of the storage medium 5 indicating the storage location of the compressed data in the storage device 6. Here, the compressed data is the data generated by the accelerator 3 compressing the data column.

[0063] The compressed data size 13 is a field for storing the data size of the compressed data. The data size of the compressed data depends on the size of the original data column and the value to be stored. Therefore, the size of each compressed data is generally different. In order to improve the data reduction effect, the compressed data needs to be stored in the storage medium 5 in a gap-free manner. Therefore, the processor 2 uses the compressed data management information 10 to control the arrangement of the compressed data on the storage medium 5.

[0064] The offset 14 within the logical address is a field that stores the logical address of the storage location of the host's write data unit in the compression unit before compression. The host's write data unit is the minimum size written by the host, for example, 8KB. The data length specified by a write command is an integer multiple of the data unit. Hereinafter, the size of the write data refers to the host's write data unit. The offset 14 within the logical address is the position information of the difference when the logical address at the beginning of the compression in the basic compression unit is set to 0. In addition, in the offset 14 within the logical address, it is also possible to store the logical address of the host's write data unit instead of the difference.

[0065] The physical address by offset 15 is a field for storing the address of the storage medium 5 indicating the storage location of the compressed data obtained by compressing not the basic compression unit but the size of the data written by the host. The compressed data size by offset 16 is a field for storing the data size of the compressed data obtained by compressing according to the size of the data written by the host.

[0066] In addition, in the physical address 12 and the physical address 15 by offset, the address of the storage medium 5 may be replaced by the address provided by the storage medium 5 to the storage controller 1, or the address of a RAID (Redundant Arrays of Inexpensive Disks) volume generated using multiple storage media 5, or the address of an external storage device 6 provided by a capacity virtualization mechanism.

[0067] The compressed data management information 10 is described in a table format as one form, but any format may be used as long as it can manage information required for processing in the following embodiments, and is not limited to the table format.

[0068] Figure 6 This is a flowchart for explaining an example of the compression process executed by the processor 2 of the first embodiment.

[0069] The processor 2 performs the compression process S1 when the write process is executed or periodically. The write process is executed when the storage device 6 receives the write data from the host 7. Here, it is assumed that the compression process S1 is performed when the write process is executed, and this is explained. In addition, during the write process, the storage device 6 saves the write data to the memory 4 and sends a completion notification of the write process to the host 7.

[0070] Processor 2 determines whether the size of the unprocessed portion of the write data stored in memory 4 is smaller than the basic compression unit (step S2).

[0071] When the size of the unprocessed portion of the write data is smaller than the basic compression unit, the processor 2 instructs the accelerator 3 to perform compression according to the size of the write data (step S3).

[0072] After the accelerator 3 compresses the unprocessed part of the write data and stores the compressed data in the memory 4, the processor 2 refers to the physical address 12, the compressed data size 13, the physical address 15 by offset, and the compressed data size 16 by offset of the compressed data management information 10, determines the last position (address) of the storage area storing the compressed data of the storage medium 5, and determines the physical address of the storage destination of the compressed data on the memory 4 (step S4). In this way, the write data is appended to the free area of ​​the storage medium 5.

[0073] The processor 2 updates the entry for the corresponding logical address internal offset in the compressed data management information 10. Specifically, the processor 2 retrieves the corresponding logical address internal offset 14 in the compressed data management information 10 from the logical address of the written data, saves the physical address determined in step S4 in the physical address 15 by offset corresponding to the logical address internal offset 14, and saves the size of the compressed data on the memory 4 in the compressed data size 16 by offset (step S5).

[0074] On the other hand, in step S2, when the size of the unprocessed portion is not smaller than the basic compression unit, the processor 2 instructs the accelerator 3 to perform compression in the basic compression unit (step S6).

[0075] The accelerator 3 reads and compresses the data in the logical address range of the basic compression unit in the unprocessed write data from the memory 4, and stores the compressed data in the memory 4. The processor 2 performs the processing described in step S4 on the compressed data stored in the memory 4, and determines the physical address of the storage destination.

[0076] The processor 2 updates the entry for the corresponding logical address in the compressed data management information 10. Specifically, the processor 2 retrieves the corresponding logical address 11 in the compressed data management information 10 from the logical address of the written data, saves the physical address determined in step S4 to the physical address 12 corresponding to the logical address 11, and saves the size of the compressed data on the memory 4 to the compressed data size 13 (step S7). In addition, the processor 2 saves "None" as an invalid value to the multiple physical addresses 15 by offset and the compressed data size 16 by offset corresponding to the logical address 11. In addition, "None" is described as an example of an invalid value, but other values ​​can also be used as long as they can be distinguished from valid values.

[0077] Next, the processor 2 determines whether there is an unprocessed portion in the write data (step S8). If there is an unprocessed portion in the write data, the processor 2 executes the process of step S2. If there is no unprocessed portion in the write data, the compression process S1 ends.

[0078] The above is the description of the process of step S1.

[0079] When the compression process S1 is executed periodically, the processor 2 executes the following steps for each data: Figure 6 Processing described in .

[0080] After executing the compression process S1, the processor 2 saves the compressed data to a determined address of the storage medium 5 at an arbitrary timing (time point). For example, the compression process S1 and the compressed data saving process may be continuously executed, or the compressed data saving process may be periodically executed. When the compressed data saving process is periodically executed, the processor 2 retrieves the compressed data saved in the memory 4 and saves the retrieved compressed data to the storage medium 5.

[0081] Figure 7 1 is a flowchart for explaining an example of the useless data collection process executed by the processor 2 of the first embodiment. The useless data collection process deletes the compressed data in the storage medium 5 that is not referenced by updating the data, so that the storage area becomes an unused area. The useless data collection process S10 may be started when the processor 2 receives write data from the host 7 and the compressed data becomes useless data, or it may be executed periodically.

[0082] Processor 2 selects the physical address of the useless data collection object (step S11). The physical address of the useless data collection object is managed in management information not shown in the figure. Here, if a physical address containing more useless data is selected, the movement of compressed data described later is reduced, and more physical addresses can be released. Therefore, processor 2 selects a physical address containing more useless data. For example, the following method can be cited: in compression processing S1, when processor 2 updates compressed data management information 10, the size of compressed data that becomes useless data is obtained, the amount of useless data is totaled for each physical address, and these physical addresses with a large amount of useless data are found and selected.

[0083] The processor 2 searches for an entry that matches the physical address selected in step S11 from the physical address 12 in the compressed data management information 10 (step S12). The processor 2 determines whether there is a matching entry (step S13). If there is a matching entry, the processor 2 determines whether a valid value is stored in any of the physical addresses 15 by offset in the entry (step S14).

[0084] When no valid value is stored in the physical address 15 according to the offset, that is, when the processor 2 does not compress the write data of a size smaller than the basic compression unit, and the compressed data corresponding to the logical address of the entry is only data compressed in the basic compression unit, the processor 2 executes the processing of step S4 described later.

[0085] On the other hand, when a valid value is stored in the physical address 15 according to the offset, the processor 2 reads the compressed data represented by the physical address 12 of the entry from the storage medium 5 and stores it in the memory 4, and instructs the accelerator 3 to decompress it (step S15).

[0086] After the data decompressed by the accelerator 3 is stored in the memory 4, the processor 2 rewrites the decompressed data of the memory 4 corresponding to the offset storing the determined valid value into 0 data in step S14 (step S16). Thus, the compression rate of data compressed in basic compression units can be improved. In addition, the shift of data in data reading is no longer necessary. In addition, 0 data is data with a higher compression rate. It can also be rewritten into specified data (bit column) different from 0 data. For the specified data, data with a higher regularity of compression rate is predefined. For example, it can also be a bit column in which each bit represents 1.

[0087] The processor 2 instructs the accelerator 3 to compress the data rewritten in step S16 in basic compression units (step S6 ). The accelerator 3 reads the data in the memory 4 , compresses the data, and stores the compressed data in the memory 4 .

[0088] Next, processor 2 refers to Figure 6 The processing described in step S4 is performed to determine the physical address of the storage destination of the compressed data. The processor 2 stores the physical address determined in step S4 in the physical address 12 of the entry in the compressed data management information 10, and stores the size of the compressed data on the memory 4 in the compressed data size 13 (step S17).

[0089] The processor 2 releases the physical address determined in step S11 so that other processes can use the physical address (step S18).

[0090] On the other hand, in step S13, if there is no entry, processor 2 searches for an entry that matches the physical address selected in step S11 from the offset-by-offset physical addresses 15 in compressed data management information 10 (step S19).

[0091] Processor 2 determines whether there is a consistent entry (step S20). If there is a consistent entry, that is, if it is compressed data obtained by compressing the data written by the host, processor 2 performs the processing of step S4. On the other hand, if there is no consistent entry, that is, if it is compressed data that becomes useless data due to write update, processor 2 performs the processing of step S18. The above is the description of the processing of step S10.

[0092] Figure 8 1 is a flowchart for explaining an example of the compressed data integration process executed by the processor 2 of Embodiment 1. The processor 2 periodically executes the compressed data integration process S30.

[0093] The processor 2 searches for the logical address 11 corresponding to the entry storing a valid value in the physical address 15 by offset in the compressed data management information 10 (step S31). The processor 2 determines whether the logical address 11 is found as a result of the search (step S32).

[0094] If the logical address 11 is not found, the compressed data integration process S30 is terminated. On the other hand, if the logical address 11 is found, the processor 2 performs a merge process of the compressed data in the range corresponding to the logical address 11 (step S40). Through this merge process, the processor 2 instructs to decompress the compressed data compressed in the basic compression unit and the compressed data compressed in the size written by the host, respectively, and merges the decompressed data and saves them in the memory 4. For details of this merge process, refer to Fig. 9 This will be explained later.

[0095] Processor 2 executes reference Figure 6 The process described in step S6 causes the accelerator 3 to store the compressed data in the memory 4 regarding the merged data generated in step S40 .

[0096] Processor 2 executes reference Figure 6 The process described in step S4 determines the physical address of the storage destination of the compressed data.

[0097] Next, the processor 2 stores the physical address determined in step S4 in the physical address 12 and the size of the compressed data stored in the memory 4 in step S6 in the compressed data size 13 for the entry retrieved in step S31. Furthermore, the processor 2 stores an invalid value in the physical address by offset 15 and the compressed data size by offset 16 in the entry (step S33). The above is the description of the processing of step S30.

[0098] Fig. 9This is a flowchart for explaining an example of the data merging process S40 within the logical address range executed by the processor 2 of the first embodiment.

[0099] The processor 2 reads the compressed data indicated by the physical address 12 from the storage medium 5 and stores it in the memory 4 regarding the processing target entry in the compressed data management information 10, and instructs the accelerator 3 to decompress the data (step S41).

[0100] The accelerator 3 reads out and decompresses the compressed data in the memory 4 , and stores the decompressed data in the memory 4 .

[0101] The processor 2 determines whether there is a valid value and unprocessed in the offset-by-offset physical address 15 in the entry in the compressed data management information 10 (step S42). If there is no valid value and unprocessed offset-by-offset physical address 15, the data merging process in the logical address range is terminated.

[0102] On the other hand, if there is a valid value and it is an unprocessed physical address 15 by offset, the processor 2 reads the compressed data represented by the physical address 15 by offset from the storage medium 5 and stores it in the memory 4, and instructs the accelerator 3 to decompress it (step S43). The accelerator 3 reads the compressed data in the memory 4 and decompresses it, and stores the decompressed data in the memory 4.

[0103] Processor 2 calculates the position information of the merge object in the decompressed data stored in memory 4 based on step S41 according to the offset 14 in the logical address, and copies the decompressed data stored in memory 4 based on the instruction of step S43 to the calculated position, thereby merging the two compressed data (step S44).

[0104] Next, processor 2 executes the process of step S42.

[0105] The above is the description of the process of step S40.

[0106] The above describes a method in which the storage device 6 compresses the write data received from the host 7 according to the size of the write data. The storage device 6 re-compresses the data in basic compression units asynchronously with the host write, thereby improving the I / O performance of the host write.

[0107] In the above example, one of two compression units, compression based on a basic compression unit and compression based on a unit of data writing smaller than the basic compression unit, is selected to compress the update data received from the host. In another example, one compression unit may be selected from more than three compression units. For example, a compression unit of a size between the basic compression unit and the data writing compression unit is prepared. For example, the basic compression unit is 32KB, the data writing unit is 8KB, and the intermediate compression unit is 16KB. For example, a 16KB compression unit is used to compress 16KB data, and a 16KB compression unit and an 8KB compression unit are used to compress 24KB data.

[0108] [Example 2]

[0109] The following describes a mode in which the useless data collection process removes useless data in the compressed data and compresses the data which is not useless data by left-aligning it.

[0110] According to the present embodiment, data that is not useless data is combined to generate duplicate portions, thereby improving the I / O performance when the free capacity of the storage medium 5 is small.

[0111] The configuration of the storage device 6 of the second embodiment is similar to that of the first embodiment. Figure 6 The compression process and the compressed data integration process performed by the storage device 6 of the second embodiment are the same as the compression process S1 and the compressed data integration process S30 of the first embodiment.

[0112] Fig.10 1 is a flowchart for explaining an example of a useless data collection process for left-alignment performed by the processor 2 of the second embodiment. Figure 7 The detailed description of the same processing is omitted.

[0113] The starting trigger for executing the left-aligned useless data collection process S50 is the same as the useless data collection process S10 of Embodiment 1. That is, the process may be started when the processor 2 receives write data from the host 7 and the compressed data becomes useless data, or it may be executed periodically.

[0114] The processor 2 executes the processing described in step S11, step S12, step S13, step S14, and step S15 of the first embodiment.

[0115] After step S15, processor 2 generates a data sequence concatenating decompressed data corresponding to physical address by offset 15 storing an invalid value in physical address by offset 15 in the entry in compressed data management information 10, and stores the data in memory 4 (step S51).

[0116] The processor 2 instructs the accelerator 3 to compress the data column connected in step S51 (step S52). The accelerator 3 has a data compression function of compressing in a basic compression unit, compressing in a size of written data, and compressing in a size between them. For example, the basic compression unit is 32KB, the minimum unit of written data is 8KB, and the accelerator 3 has a compression function of compressing in 16KB and 24KB.

[0117] After step S52, processor 2 executes the processes described in step S4, step S17, and step S18 of the first embodiment.

[0118] Furthermore, in step S13, if there is no entry, processor 2 executes the processing described in steps S19 and S20 of the first embodiment.

[0119] The above is the description of the process of step S50.

[0120] As described above, in the useless data collection process performed by the storage device 6, only the data that is not useless data is combined and recompressed, thereby generating a repeated portion across the combined data, and the compression efficiency is improved. Thus, by suppressing the amount of physical addresses newly secured in the useless data collection, the I / O performance can be improved when the free capacity of the storage medium 5 is small. In addition, in addition to being able to select the basic compression unit and the unit for writing data, the update data compression process from the host can also be selected from the compression units between them. Thus, even when the data length of the update data is shorter than the basic compression unit, it can be compressed with its data length. For example, in addition to the 32KB of the basic compression unit and the 8KB of the write data unit, 24KB or 16KB of update data can also be compressed together.

[0121] [Example 3]

[0122] The following describes a form in which the useless data collection process overwrites and compresses the useless data portion in the compressed data with the data written by the host.

[0123] According to the present embodiment, the useless data collection process includes the compressed data integration process S30, thereby being able to suppress the amount of useless data generated and improve the I / O performance when the free capacity of the storage medium 5 is small.

[0124] The configuration of the storage device 6 of the third embodiment is similar to that of the first embodiment. Figure 6 The compression process and the compressed data integration process performed by the storage device 6 of the third embodiment are the same as the compression process S1 and the compressed data integration process S30 of the first embodiment.

[0125] Fig.111 is a flowchart for explaining an example of useless data collection processing for implementing data integration executed by the processor 2 of the third embodiment. Figure 7 The detailed description of the same processing is omitted.

[0126] The useless data collection process S60 for implementing data integration is executed periodically. This is because since step S60 includes data integration, if it is executed when write data is received from the host 7, the effect of improving the I / O performance of host write cannot be obtained.

[0127] The processor 2 executes the processing described in step S11, step S12, step S13, and step S14 of the first embodiment.

[0128] In step S14, if a valid value is stored in the physical address 15 by the offset, the processor 2 specifies the entry retrieved in step S12 and executes the process of step S40. Thus, the compressed data corresponding to the physical address 12 of the entry and the data decompressed from the compressed data corresponding to the physical address 15 by the offset are combined and stored in the memory 4.

[0129] Next, processor 2 executes reference Figure 6 The processing described in step S6 and step S4.

[0130] Next, the processor 2 stores the physical address determined in step S4 in the physical address 12 and the size of the compressed data generated in step S6 in the compressed data size 13 for the entry in the compressed data management information 10. Furthermore, the processor 2 stores invalid values ​​in the physical address by offset 15 and the compressed data size by offset 16 in the entry (step S61).

[0131] Then, processor 2 executes reference Figure 7 The processing described in step S18.

[0132] Furthermore, in step S13, if there is no entry, processor 2 executes the processing described in steps S19 and S20 of the first embodiment.

[0133] The above is the description of the process of step S60.

[0134] As described above, by performing the compressed data integration process in the useless data collection process performed by the storage device 6 , the amount of useless data generated can be suppressed, and the I / O performance can be improved when the free capacity of the storage medium 5 is small.

[0135] [Example 4]

[0136] The compression process will be described in which the compression unit is switched according to the usage status of the storage medium 5.

[0137] In the compression process S1 and the compressed data integration process S30 of the first embodiment, new compressed data is generated, so that part or all of the original compressed data is in a useless data state. Therefore, the amount of useless data generated in the first embodiment is larger than an example of the operation assumed as the aforementioned compression process. In the case where the free capacity of the storage medium 5 is smaller than the amount of useless data generated by the compression process S1 and the compressed data integration process S30 of the first embodiment, there is a case where the free capacity of the storage medium 5 is insufficient only by the process described in the first embodiment.

[0138] According to this embodiment, when the free capacity of the storage medium 5 is less than a threshold value, compression is performed only in basic compression units, thereby achieving an effect of suppressing a reduction in the free capacity of the storage medium 5 due to host writing.

[0139] The configuration of the storage device 6 of the fourth embodiment is similar to that of the first embodiment. Figure 6 The useless data collection process and the compressed data integration process performed by the storage device 6 of the second embodiment are the same as the useless data collection process S10 and the compressed data integration process S30 of the first embodiment.

[0140] Fig.12 1 is a flowchart for explaining an example of compression processing for switching compression units executed by the processor 2 of the fourth embodiment. Figure 6 The detailed description of the same processing is omitted.

[0141] The start trigger of the compression process S70 for switching the compression unit is the same as the compression process S1 of Embodiment 1. That is, the processor 2 executes it when executing the write process or periodically.

[0142] Processor 2 executes the process described in step S2 of the first embodiment.

[0143] When the size of the unprocessed portion of the write data is smaller than the basic compression unit, the processor 2 determines whether the free capacity of the storage medium 5 is below a threshold value (step S71). Here, the threshold value can be a fixed value pre-set in the product design, or a value set by the user of the storage device 6 during the use of the storage device 6. In addition, the determination of step S71 can be as follows: whether the release speed of the physical address of the storage medium 5 performed by the useless data collection process S10 is lower than the write speed of the host 7, and the free capacity of the storage medium 5 will decrease in the future and cannot accommodate the write data of the host 7. In this determination, for example, the following method can be cited: according to the change of the useless data amount in the LUN, the useless data amount continues to increase, thereby determining that the free capacity of the storage medium 5 is below the threshold value.

[0144] In step S71, when the free capacity of the storage medium 5 is below the threshold, the processor 2 reads the compressed data including the write data from the storage medium 5 and stores it in the memory 4, and instructs the accelerator 3 to decompress it. The accelerator 3 reads the compressed data in the memory 4 and decompresses it, and stores the decompressed data in the memory 4. The processor 2 overwrites the decompressed data in the memory 4 with the write data, thereby merging the decompressed data with the write data (step S72).

[0145] The processor 2 instructs the accelerator 3 to compress the data generated in step S72 in basic compression units (step S73).

[0146] The accelerator 3 reads and compresses the data in the memory 4 , and stores the compressed data in the memory 4 .

[0147] Then, the processor 2 executes the processing described in step S4, step S7, and step S8 of the first embodiment.

[0148] On the other hand, in step S71, when the free capacity of the storage medium 5 is not less than the threshold value, the processor executes the processing described in steps S3, S4, and S5 of the first embodiment.

[0149] Furthermore, in step S2, when the size of the unprocessed portion of the write data is not smaller than the basic compression unit, processor 2 executes the processing described in steps S6, S4, S7, and S8 of the first embodiment.

[0150] The above is the description of the process of step S70.

[0151] As described above, in the compression processing performed by the storage device 6, when the free capacity of the storage medium 5 is small, when compression is performed only with basic compression units so that the free capacity of the storage medium 5 is so small that the storage medium 5 cannot save the useless data generated in the compression processing S1 of Example 1 and the integration processing S30 of the compressed data, the reduction of the free capacity of the storage medium 5 caused by the host writing can be suppressed.

[0152] In addition, the present invention is not limited to the above-mentioned embodiments, but includes various modified examples. For example, the above-mentioned embodiments are contents described in detail in order to explain the present invention in an easy-to-understand manner, and are not limited to necessarily having all the described structures. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the structure of a certain embodiment. In addition, with respect to a part of the structure of each embodiment, other structures can be added / deleted / replaced.

[0153] In addition, the above-mentioned components, functions, processing units, etc. may also be partially or entirely implemented by hardware, such as by integrated circuit design, etc. In addition, the above-mentioned components, functions, etc. may also be implemented by software by interpreting and executing programs that implement each function through a processor. Information on programs, tables, files, etc. that implement each function may be placed in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card or an SD card.

[0154] Furthermore, the control lines and information lines are shown as those considered necessary for the description, and do not necessarily represent all the control lines and information lines on the product. In fact, it can be considered that almost all components are connected to each other.

Claims

1. A storage device having a data compression function, characterized in that: The storage device comprises: Processor; and Accelerator, performs data compression and decompression, The processor receives first update write data of a part of the first logical address area with respect to first compressed data of the first logical address area compressed in the basic compression unit, the processor instructs the accelerator to compress the first update write data in a size smaller than the basic compression unit, The accelerator compresses the first update write data into the small size. The processor combines the non-updated data in the first logical address area decompressed by the accelerator with the first updated write data to generate uncompressed data of the basic compression unit. The processor instructs the accelerator to compress the uncompressed data using the basic compression unit.

2. The storage device according to claim 1, wherein: The processor executes a useless data collection process in which compressed data that is no longer referenced due to data update is deleted to form an unused area. The processor performs the useless data collection process before the merging. In the above useless data collection process, instructing the accelerator to decompress the first compressed data; rewriting the data of the part of the first logical address area in the decompressed first compressed data into a predetermined bit sequence; The accelerator is instructed to compress the rewritten first compressed data using the basic compression unit.

3. The storage device according to claim 1, wherein: The processor executes a useless data collection process in which compressed data that is no longer referenced due to data update is deleted to form an unused area. The processor performs the useless data collection process before the merging. In the above useless data collection process, causing the accelerator to decompress the first compressed data; concatenating the non-updated data with the decompressed first compressed data; The accelerator is instructed to compress the concatenated non-updated data into a size of the concatenated non-updated data.

4. The storage device according to claim 1, wherein: The processor executes a useless data collection process in which compressed data that is no longer referenced due to data update is deleted to form an unused area. The processor performs the merging in the useless data collection process. In the above useless data collection process, Instructing the accelerator to decompress the first compressed data and the first updated written data; rewriting the part of the first logical address area in the decompressed first compressed data with the first update write data; The accelerator is instructed to compress the rewritten first compressed data using the basic compression unit.

5. The storage device according to claim 1, wherein: The storage device also includes a storage medium. The above processors, When the free capacity of the storage medium is larger than a threshold, instructing the accelerator to compress the first update write data with a size smaller than the basic compression unit; When the free capacity of the storage medium is below the threshold, instructing the accelerator to decompress the first compressed data; updating the decompressed first compressed data with the first update write data; The accelerator is instructed to compress the updated first compressed data using the basic compression unit.

6. A data processing method for storing compressed data in a storage medium, characterized in that: receiving first update write data of a part of the first logical address area for the first compressed data of the first logical address area compressed in the basic compression unit, The first update write data is compressed into a size smaller than the basic compression unit. Decompressing and merging the compressed non-updated data in the first logical address area and the compressed first update write data to generate uncompressed data of the basic compression unit. The uncompressed data is compressed using the basic compression unit.

7. The data processing method according to claim 6, characterized in that: Before the above-mentioned merging, a useless data collection process is performed, in which compressed data that is no longer referenced due to data update is deleted to form an unused area. In the above useless data collection process, Decompressing the first compressed data; rewriting the data of the part of the first logical address area in the decompressed first compressed data into a predetermined bit sequence; The rewritten first compressed data is compressed in the basic compression unit.

8. The data processing method according to claim 6, characterized in that: Before the above-mentioned merging, a useless data collection process is performed, in which compressed data that is no longer referenced due to data update is deleted to form an unused area. In the above useless data collection process, Decompressing the first compressed data; concatenating the non-updated data with the first compressed data after being decompressed; The concatenated non-updated data is compressed to a size of the concatenated non-updated data.

9. The data processing method according to claim 6, characterized in that: A useless data collection process is performed in which compressed data that is no longer referenced due to data update is deleted to form an unused area. In the above useless data collection process, Includes the above merger; decompressing the first compressed data and the first updated written data; rewriting the part of the first logical address area in the decompressed first compressed data with the first update write data; The rewritten first compressed data is compressed in the basic compression unit.

10. The data processing method according to claim 6, characterized in that: When the free capacity of the storage medium is larger than a threshold value, the first update write data is compressed into a size smaller than the basic compression unit. When the free capacity of the storage medium is below the threshold, Decompressing the first compressed data; updating the decompressed first compressed data with the first update write data; The updated first compressed data is compressed using the basic compression unit.

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