Packaging method and system of multi-layer stacked storage chip

Abstract

The invention relates to the technical field of microelectronic packaging, and discloses a packaging method of a multi-layer stacked memory chip, which comprises the following steps: constructing a 3D packaging structure layout of a memory chip to be packaged; constructing a physical field of the 3D packaging structure layout, and integrating the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout; calculating a hot spot, a high stress area and a high electric field area of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout to obtain a target packaging structure layout; performing multi-layer stacking on the to-be-packaged storage chip to obtain a multi-layer stacked storage chip; and packaging the multi-layer stacked memory chip to obtain a packaged multi-layer stacked memory chip, activating packaging repair of the self-repair material by using a preset material repair algorithm to obtain a packaging repair material, and performing multi-layer stacked packaging of the to-be-packaged memory chip based on the packaging repair material. According to the invention, the packaging stability of the multi-layer stacked storage chip can be improved.

Description

Technical Field

[0001] The invention relates to a packaging method and system for a multi-layer stacked memory chip, belonging to the technical field of microelectronic packaging. Background Art

[0002] The packaging technology of multi-layer stacked memory chips is an advanced semiconductor packaging method that achieves high storage density and optimized performance by stacking multiple chips vertically together. The main purpose of this technology is to reduce the space occupied by multi-chip packaging, thereby minimizing the size of memory devices.

[0003] Packaging of multi-layer stacked memory chips Traditional packaging solutions usually involve stacking multiple chips together through wire bonding or flip chip technology, and packaging them using materials such as epoxy resin or ceramics. However, this method lacks coupled simulation and optimization of multi-physical fields, resulting in poor thermal management, electrical performance and mechanical reliability of the packaged multi-layer stacked memory chips, thereby limiting the performance improvement of the memory chips. Summary of the invention

[0004] The present invention provides a packaging method and system for a multi-layer stacked memory chip, the main purpose of which is to improve the packaging stability of the multi-layer stacked memory chip.

[0005] To achieve the above object, the present invention provides a packaging method for a multi-layer stacked memory chip, comprising:

[0006] Obtaining packaging requirements of the memory chip to be packaged, determining packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements;

[0007] Constructing a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field, and a mechanical field, defining a field action relationship of the physical field, and integrating the physical field and the field action relationship into the 3D packaging structure layout based on the field action relationship to obtain a coupled 3D packaging structure layout;

[0008] Calculating hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout;

[0009] Based on the target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged, constructing the redistribution layer of the packaging material corresponding to the packaging substrate, and stacking the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip;

[0010] The multi-layer stacked memory chip is packaged using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and packaging status data of the packaged multi-layer stacked memory chip is collected. Based on the packaging status data, the packaging repair of the self-repairing material is activated using a preset material repair algorithm to obtain a packaging repair material, and based on the packaging repair material, multi-layer stacking packaging of the memory chip to be packaged is performed.

[0011] Optionally, constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging material, the packaging environment and the packaging requirement includes:

[0012] Identifying memory chip characteristics of the memory chip to be packaged;

[0013] Determining the key packaging parameters of the memory chip to be packaged according to the packaging requirements, wherein the key packaging parameters include size, thermal resistance and electrical characteristics;

[0014] Based on the key packaging parameters, determining the packaging structure components of the memory chip to be packaged;

[0015] The 3D packaging structure layout of the memory chip to be packaged is planned based on the memory chip characteristics, the key packaging parameters, the packaging materials, the packaging environment and the packaging structure components, wherein the chip packaging layout includes chip layout, interconnection paths and heat dissipation paths.

[0016] Optionally, constructing the physical field of the 3D packaging structure layout includes:

[0017] Performing finite element meshing on the 3D packaging structure layout to obtain a meshed packaging structure layout;

[0018] Defining thermal field parameters, thermal field boundary conditions, electric field parameters, electric field boundary conditions, mechanical field parameters and mechanical field boundary conditions of the grid packaging structure layout;

[0019] Constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions;

[0020] The electric field analysis function of the grid packaging structure layout is constructed by using the electric field parameters and the electric field boundary conditions using the following formula, wherein the electric field analysis function is:

[0021]

[0022] in, represents the gradient operator, E represents the electric potential of the grid package structure layout under the electric field boundary condition, ε0 represents the permittivity of the electric field parameter in vacuum, Δε(e) represents the change in capacitance at position e under the electric field boundary condition, σ0 represents the background charge density of the grid package structure layout under the electric field boundary condition, Δσ(e) represents the charge density disturbance at position e under the electric field boundary condition, and e represents the position e of the grid package structure layout;

[0023] Based on the mechanical field parameters and the mechanical field boundary conditions, constructing a mechanical field analysis function of the gridded packaging structure layout;

[0024] Constructing the thermal field, electric field and mechanical field of the grid packaging structure layout through the thermal field analysis function, the electric field analysis function and the mechanical field analysis function;

[0025] The thermal field, electric field and mechanical field are combined to construct a physical field of the grid packaging structure layout.

[0026] Optionally, constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions includes:

[0027] Determine the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate of the gridded packaging structure layout based on the thermal field parameters and the thermal field boundary conditions;

[0028] According to the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate, the following formula is used to construct a thermal field analysis function of the grid packaging structure layout, wherein the thermal field analysis function is:

[0029]

[0030] in, represents the gradient operator, α represents the thermal conductivity, T represents the temperature distribution of the grid packaging structure layout, P represents the heat source term, ρ represents the material density, γ represents the specific heat capacity, represents the derivative function, It represents the rate of change of temperature over time.

[0031] Optionally, the defining the field action relationship of the physical field includes:

[0032] Simulating the action data of the physical field;

[0033] Based on the action data, a thermo-electric action function, a thermo-mechanical action function and an electro-mechanical action function of the physical field are constructed; wherein the thermo-mechanical action function:

[0034]

[0035] Among them, τ th represents thermal stress, θ represents the thermal expansion coefficient in the action data, m represents the elastic modulus in the action data, ΔB represents the temperature change in the action data, represents Poisson's ratio;

[0036] The thermo-electric action function:

[0037] R(S)=R0[1+alpha_R(S-S0)]

[0038] Wherein, R(S) represents the resistance at temperature S in the action data, R0 represents the resistance at reference temperature S0 in the action data, and alpha_R represents the resistance temperature coefficient;

[0039] The electro-mechanical action function:

[0040] epsilon = pi_c·m·m_field

[0041] Among them, epsilon represents the electrostrictive strain in the action data, pi_c represents the electrostrictive coefficient in the action data, m represents the elastic modulus in the action data, and m_field represents the electric field intensity in the action data;

[0042] The field action relationship of the physical field is defined according to the thermo-electric action function, the thermo-mechanical action function and the electro-mechanical action function.

[0043] Optionally, the calculating the hot spots, high stress areas and high electric field areas of the coupled 3D packaging structure layout based on the battery parameters includes:

[0044] Simulating the coupled 3D packaging structure layout to obtain simulation data;

[0045] Analyzing the layout temperature distribution, layout stress distribution and layout electric field distribution of the coupled 3D packaging structure layout through the simulation data;

[0046] Calculating hot spots of the coupled 3D packaging structure layout based on the layout temperature distribution;

[0047] Marking high stress areas of the coupled 3D packaging structure layout according to the layout stress distribution;

[0048] The high electric field area of ​​the coupled 3D packaging structure layout is marked by the layout electric field distribution.

[0049] Optionally, the optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas and high electric field areas to obtain a target packaging structure layout includes:

[0050] Using the preset hot spot risk threshold, stress risk threshold and electric field risk threshold, respectively analyze the hot spot anomaly, stress anomaly and electric field anomaly of the hot spot, high stress area and high electric field area;

[0051] Based on the hot spot anomaly, stress anomaly, and electric field anomaly, determining an abnormal design defect of the coupled 3D packaging structure layout;

[0052] Analyze the design defect characteristics of the abnormal design defect;

[0053] Based on the design defect characteristics, construct an optimization strategy for the coupled 3D packaging structure layout;

[0054] The coupled 3D packaging structure layout is optimized according to the optimization strategy to obtain a target packaging structure layout.

[0055] Optionally, the memory chip to be packaged is stacked in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target package structure layout and the packaging material to obtain a multi-layer stacked memory chip, including:

[0056] Placing the memory chip to be packaged on the packaging substrate corresponding to the packaging material, and aligning the micro-bumps and the redistribution layer corresponding to the memory chip to be packaged to obtain an aligned micro-bump-redistribution layer;

[0057] Hot pressing the aligned micro-bump-rewiring layer to obtain a connected micro-bump-rewiring layer;

[0058] Using the TSV and the target package structure layout, the connection micro-bump-rewiring layer is connected to obtain a multi-layer connection memory chip;

[0059] The multi-layer connected memory chip is welded by using the corresponding solder of the packaging material to obtain the multi-layer stacked memory chip.

[0060] Optionally, based on the packaging state data, activating the packaging repair of the self-repairing material using a preset material repair algorithm to obtain a packaging repair material includes:

[0061] Based on the packaging status data, identifying material loss of the self-healing material;

[0062] identifying a material loss characteristic of the material loss;

[0063] Calculating a loss coefficient of the material loss according to the material loss characteristics;

[0064] When the loss coefficient meets a preset loss coefficient threshold, activating a self-repairing reaction of the self-repairing material using the material repair algorithm;

[0065] In order to solve the above problems, the present invention further provides a packaging system for multi-layer stacked memory chips, the system comprising:

[0066] A 3D packaging structure layout construction module is used to obtain the packaging requirements of the memory chip to be packaged, determine the packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and construct the 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements;

[0067] A packaging structure layout coupling module, used to construct a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field and a mechanical field, define a field action relationship of the physical field, and based on the field action relationship, integrate the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout;

[0068] A package structure layout optimization module, used to calculate the hot spots, high stress areas and high electric field areas of the coupled 3D package structure layout, and optimize the coupled 3D package structure layout based on the hot spots, high stress areas and high electric field areas to obtain a target package structure layout;

[0069] A memory chip multi-layer stacking module is used to construct TSV and micro-bumps of the memory chip to be packaged based on the target packaging structure layout, construct a redistribution layer of the packaging material corresponding to the packaging substrate, and stack the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip;

[0070] A multi-layer stacked memory chip packaging module is used to package the multi-layer stacked memory chip using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and collect packaging status data of the packaged multi-layer stacked memory chip, based on the packaging status data, activate the packaging repair of the self-repairing material using a preset material repair algorithm to obtain a packaging repair material, and perform multi-layer stacking packaging of the memory chip to be packaged based on the packaging repair material.

[0071] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising:

[0072] at least one processor; and,

[0073] a memory communicatively connected to the at least one processor; wherein,

[0074] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to implement the packaging method of the multi-layer stacked memory chip described above.

[0075] In order to solve the above problems, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned packaging method of the multi-layer stacked memory chip.

[0076] Compared with the problems described in the background technology, the present invention obtains the packaging requirements of the memory chip to be packaged, and according to the packaging requirements, determines the packaging materials and packaging environment of the memory chip to be packaged, which can be used as data basis for constructing a 3D packaging structure layout that meets specific requirements; further, the present invention can ensure that the packaging meets predetermined performance and reliability requirements by constructing the physical field of the 3D packaging structure layout, thereby improving the packaging effect of multi-layer stacked memory chips; further, the present invention calculates the hot spots, high stress areas and high electric field areas of the coupled 3D packaging structure layout to provide a basis for subsequent optimization of the packaging structure layout; further, the present invention optimizes the coupled 3D packaging structure layout based on the hot spots, high stress areas and high electric field areas, and obtains an optimized target packaging structure layout, which can improve thermal management efficiency, mechanical strength and electrical reliability while ensuring performance; further, the present invention is based on the The target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged can construct TSV and micro-bumps that meet the requirements of the target packaging structure layout, thereby realizing high-density and high-performance packaging of the memory chip. Next, the present invention performs multi-layer stacking of the memory chip to be packaged according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material, and obtains a packaging solution for a multi-layer stacked memory chip to achieve high density and high performance. Finally, the present invention uses the packaging material to encapsulate the multi-layer stacked memory chip corresponding to the self-repairing material to obtain a packaged multi-layer stacked memory chip. The long-term stability and reliability of the chip can be improved and based on the packaging state data, the packaging repair of the self-repairing material is activated by a preset material repair algorithm, and the packaging repair material can achieve effective self-repair of the self-repairing material in the packaged multi-layer stacked memory chip, ensuring the long-term stability and reliability of the package. Therefore, the present invention can improve the packaging stability of the multi-layer stacked memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Figure 1 A schematic diagram of a process for packaging a multi-layer stacked memory chip provided by an embodiment of the present invention;

[0078] Figure 2 A functional module diagram of a packaging system for multi-layer stacked memory chips provided by an embodiment of the present invention;

[0079] Figure 3 A schematic structural diagram of an electronic device of a packaging system for multi-layer stacked memory chips provided by an embodiment of the present invention;

[0080] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0081] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0082] The embodiment of the present application provides a packaging method for a multi-layer stacked memory chip. The execution subject of the packaging method for the multi-layer stacked memory chip includes but is not limited to at least one of the electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided by the embodiment of the present application. In other words, the packaging method for the multi-layer stacked memory chip can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0083] Embodiment 1:

[0084] Reference Figure 1 , which is a schematic flow chart of a packaging method for a multi-layer stacked memory chip provided by an embodiment of the present invention.

[0085] In this embodiment, the packaging method of the multi-layer stacked memory chip includes:

[0086] S1. Obtain packaging requirements of a memory chip to be packaged, determine packaging materials and a packaging environment for the memory chip to be packaged according to the packaging requirements, and construct a 3D packaging structure layout for the memory chip to be packaged based on the packaging materials, the packaging environment, and the packaging requirements.

[0087] The present invention obtains the packaging requirements of the memory chip to be packaged, and according to the packaging requirements, determines the packaging materials and packaging environment of the memory chip to be packaged, which can be used as the data basis for constructing a 3D packaging structure layout that meets specific requirements. Among them, the packaging requirements refer to the specific requirements of the memory chip to be packaged in terms of performance, reliability, application environment, etc., such as performance requirements, size and shape, thermal management and other requirements; the packaging materials refer to various materials used to protect and fix the chip, and provide electrical connection and thermal management, including substrate materials, interconnect materials, dielectric materials, conductive materials, heat dissipation materials and other materials; the packaging environment refers to the specific environmental conditions in the chip packaging process, including cleanliness, temperature and humidity, atmosphere, equipment conditions and other environments.

[0088] Optionally, the present invention constructs a 3D packaging structure layout of the memory chip to be packaged based on the packaging material, the packaging environment and the packaging requirements, and can provide detailed design guidance for the packaging of multi-layer stacked memory chips.

[0089] In detail, the constructing of the 3D packaging structure layout of the memory chip to be packaged based on the packaging material, the packaging environment and the packaging requirements includes:

[0090] Identifying memory chip characteristics of the memory chip to be packaged;

[0091] Determining the key packaging parameters of the memory chip to be packaged according to the packaging requirements, wherein the key packaging parameters include size, thermal resistance and electrical characteristics;

[0092] Based on the key packaging parameters, determining the packaging structure components of the memory chip to be packaged;

[0093] The 3D packaging structure layout of the memory chip to be packaged is planned based on the memory chip characteristics, the key packaging parameters, the packaging materials, the packaging environment and the packaging structure components, wherein the chip packaging layout includes chip layout, interconnection paths and heat dissipation paths.

[0094] Among them, the memory chip characteristics refer to the basic functions and performance indicators of the memory chip, including but not limited to storage capacity, read and write speed, power consumption, and signal integrity. The size refers to the overall physical size of the packaged memory chip, including length, width, height, and stacking spacing between chips. The thermal resistance refers to an indicator that measures the ability of the package structure to hinder the flow of heat. The electrical characteristics include the insulation resistance, dielectric constant, dielectric strength, leakage current, signal transmission rate, impedance matching, etc. of the package. The package structure components refer to the various parts that constitute the package structure, including but not limited to substrates, chip bonding materials, lead frames, package shells, heat sinks, connectors, filling materials, etc. The chip layout refers to the arrangement and position of each memory chip inside the package. A good layout can optimize the signal path, thermal path, and mechanical structure. The interconnection path refers to the electrical connection between chips and between chips and external circuits, including wire bonding, flip chip connection, through silicon vias (TSV), etc. The heat dissipation path refers to the path used to conduct and dissipate heat in the package structure, including parameters such as heat sinks, heat pipes, and thermal interface materials. The 3D package structure layout refers to a model that shows all the components, layouts, interconnection paths, and heat dissipation paths of the package in detail.

[0095] Optionally, the 3D packaging structure layout of the memory chip to be packaged is planned through the memory chip characteristics, the key packaging parameters, the packaging materials, the packaging environment and the packaging structure components, wherein the chip packaging layout including the chip layout, interconnection path and heat dissipation path can be constructed according to the plan using CAD (computer-aided design) software.

[0096] S2. Construct a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field and a mechanical field, define a field action relationship of the physical field, and based on the field action relationship, integrate the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout.

[0097] The present invention can ensure that the packaging meets predetermined performance and reliability requirements by constructing the physical field of the 3D packaging structure layout, thereby improving the packaging effect of the multi-layer stacked memory chip.

[0098] In detail, the physical field of constructing the 3D packaging structure layout includes:

[0099] Performing finite element meshing on the 3D packaging structure layout to obtain a meshed packaging structure layout;

[0100] Defining thermal field parameters, thermal field boundary conditions, electric field parameters, electric field boundary conditions, mechanical field parameters and mechanical field boundary conditions of the grid packaging structure layout;

[0101] Constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions;

[0102] The electric field analysis function of the grid packaging structure layout is constructed by using the electric field parameters and the electric field boundary conditions using the following formula, wherein the electric field analysis function is:

[0103]

[0104] in, represents the gradient operator, E represents the electric potential of the grid package structure layout under the electric field boundary condition, ε0 represents the permittivity of the electric field parameter in vacuum, Δε(e) represents the change in capacitance at position e under the electric field boundary condition, σ0 represents the background charge density of the grid package structure layout under the electric field boundary condition, Δσ(e) represents the charge density disturbance at position e under the electric field boundary condition, and e represents the position e of the grid package structure layout;

[0105] Based on the mechanical field parameters and the mechanical field boundary conditions, constructing a mechanical field analysis function of the gridded packaging structure layout;

[0106] Constructing the thermal field, electric field and mechanical field of the grid packaging structure layout through the thermal field analysis function, the electric field analysis function and the mechanical field analysis function;

[0107] The thermal field, electric field and mechanical field are combined to construct a physical field of the grid packaging structure layout.

[0108] Among them, the thermal field parameters refer to the parameters describing the heat transfer characteristics in the packaging structure layout, including the thermal conductivity, specific heat capacity, density, etc. of the material; the thermal field boundary conditions refer to the thermal conditions defined on the boundary of the packaging structure layout, such as fixed temperature, heat flux density, convection heat transfer coefficient and other parameters; the electric field parameters refer to the electrical characteristics described in the packaging structure layout, including the dielectric constant, conductivity and other parameters of the material; the electric field boundary conditions refer to the electrical conditions defined on the boundary of the packaging structure layout, such as fixed potential, background charge density and other parameters; the mechanical field parameters refer to the mechanical characteristics described in the packaging structure layout, including elastic modulus, Poisson's ratio, yield stress and other parameters; the mechanical field boundary conditions It refers to the mechanical conditions defined on the boundary of the packaging structure layout, such as fixed displacement, force load, stress, etc. The thermal field analysis function refers to the function used to simulate and calculate the temperature distribution and heat flow in the packaging structure layout. The electric field analysis function refers to the function used to simulate and calculate the potential distribution and electric field strength in the packaging structure layout. The mechanical field analysis function refers to the function used to simulate and calculate the stress, strain and displacement in the packaging structure layout. The thermal field refers to the field that describes the temperature distribution and heat flow in the packaging structure layout. The electric field describes the field of potential distribution and electric field strength in the packaging structure layout. The mechanical field refers to the field that describes the stress, strain and displacement distribution in the packaging structure layout.

[0109] Furthermore, constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions includes:

[0110] Determine the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate of the gridded packaging structure layout based on the thermal field parameters and the thermal field boundary conditions;

[0111] According to the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate, the following formula is used to construct a thermal field analysis function of the grid packaging structure layout, wherein the thermal field analysis function is:

[0112]

[0113] in, represents the gradient operator, α represents the thermal conductivity, T represents the temperature distribution of the grid packaging structure layout, P represents the heat source term, ρ represents the material density, γ represents the specific heat capacity, represents the derivative function, It represents the rate of change of temperature over time.

[0114] Among them, the thermal conductivity refers to the ability of a material to transfer heat, the temperature distribution refers to the temperature value at each grid node in the entire grid packaging structure layout, the heat source term refers to the heat generated inside the packaging structure, the material density refers to the density of the material used in the packaging structure, the specific heat capacity refers to the amount of heat required to increase the unit temperature of a unit mass of material, and the temperature-time rate of change refers to the rate of change of temperature over time.

[0115] The present invention defines the field interaction relationship of the physical fields to predict and analyze the behavior of complex systems under different working conditions, thereby improving the reliability of packaging structure layout design. The field interaction relationship refers to the interaction and influence between different physical fields.

[0116] In detail, the field action relationship of defining the physical field includes:

[0117] Simulating the action data of the physical field;

[0118] Based on the action data, a thermo-electric action function, a thermo-mechanical action function and an electro-mechanical action function of the physical field are constructed; wherein the thermo-mechanical action function:

[0119]

[0120] Among them, τ th represents thermal stress, θ represents the thermal expansion coefficient in the action data, m represents the elastic modulus in the action data, ΔB represents the temperature change in the action data, represents Poisson's ratio;

[0121] The thermo-electric action function:

[0122] R(S)=R0[1+alpha_R(S-S0)]

[0123] Wherein, R(S) represents the resistance at temperature S in the action data, R0 represents the resistance at reference temperature S0 in the action data, and alpha_R represents the resistance temperature coefficient;

[0124] The electro-mechanical action function:

[0125] epsilon = pi_c·m·m_field

[0126] Among them, epsilon represents the electrostrictive strain in the action data, pi_c represents the electrostrictive coefficient in the action data, m represents the elastic modulus in the action data, and m_field represents the electric field intensity in the action data;

[0127] The field action relationship of the physical field is defined according to the thermo-electric action function, the thermo-mechanical action function and the electro-mechanical action function.

[0128] Among them, the action data refers to numerical data obtained from experiments or simulations, which describe the influence of physical fields (such as thermal fields, electric fields, and mechanical fields) on the packaging structure. These data generally include temperature, voltage, current, stress, strain, etc. The thermo-electric action function refers to the interaction between thermal and electric fields, the thermo-mechanical action function refers to the interaction between thermal and mechanical fields, the electro-mechanical action function refers to the interaction between electric and mechanical fields, the thermal expansion coefficient refers to the relative amount of length change when the temperature changes, the elastic modulus refers to the measure of the ability of a material to resist deformation, the temperature change refers to the amount of temperature change in a material or structure, the Poisson's ratio refers to the ratio of the transverse strain to the longitudinal strain of a material when it is compressed in one direction, the temperature coefficient of resistance refers to the coefficient that describes the sensitivity of resistance to temperature change, the electrostrictive strain refers to the strain generated by the material under the action of the electric field, the electrostrictive coefficient refers to the coefficient that describes the relationship between the strain of the material under the action of the electric field and the electric field strength, and the electric field strength refers to the ratio of the electric field force at a certain point in the electric field to the unit charge.

[0129] Based on the field action relationship, the physical field and the field action relationship are integrated into the 3D packaging structure layout, and the coupled 3D packaging structure layout is obtained, which can simulate the complex physical phenomena under actual working conditions and provide detailed guidance for packaging design. Among them, the coupled 3D packaging structure layout refers to a layout design that comprehensively considers different physical fields (such as thermal fields, electric fields, magnetic fields, stress fields, etc.) and the interactions between them in a three-dimensional packaging design.

[0130] S3. Calculate the hot spots, high stress areas and high electric field areas of the coupled 3D packaging structure layout, and optimize the coupled 3D packaging structure layout based on the hot spots, high stress areas and high electric field areas to obtain a target packaging structure layout.

[0131] The present invention calculates the hot spots, high stress areas and high electric field areas of the coupled 3D packaging structure layout to provide a basis for subsequent packaging structure layout optimization.

[0132] In detail, the calculating of hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout includes:

[0133] Simulating the coupled 3D packaging structure layout to obtain simulation data;

[0134] Analyzing the layout temperature distribution, layout stress distribution and layout electric field distribution of the coupled 3D packaging structure layout through the simulation data;

[0135] Calculating hot spots of the coupled 3D packaging structure layout based on the layout temperature distribution;

[0136] Marking high stress areas of the coupled 3D packaging structure layout according to the layout stress distribution;

[0137] The high electric field area of ​​the coupled 3D packaging structure layout is marked by the layout electric field distribution.

[0138] Among them, the simulation data refers to the numerical results obtained by multi-physics field simulation software (such as ANSYS, COMSOL Multiphysics, etc.), including specific numerical values ​​of physical quantities such as temperature, stress, and electric field strength. These data are usually distributed in the form of grids on each node of the model. The layout temperature distribution refers to the description of the temperature distribution in the entire 3D packaging structure layout, the layout stress distribution refers to the description of the stress distribution in the entire 3D packaging structure layout, the layout electric field distribution refers to the description of the electric field distribution in the entire 3D packaging structure layout, the hot spot refers to the area with the highest temperature in the layout temperature distribution, the high stress area refers to the area in the layout stress distribution where the stress level exceeds the material's bearing capacity, and the high electric field area refers to the area in the layout electric field distribution where the electric field strength exceeds the material breakdown electric field.

[0139] Optionally, the present invention optimizes the coupled 3D packaging structure layout based on the hot spots, high stress areas and high electric field areas to obtain an optimized target packaging structure layout, which can improve thermal management efficiency, mechanical strength and electrical reliability while ensuring performance.

[0140] In detail, the coupled 3D packaging structure layout is optimized based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout, including:

[0141] Using the preset hot spot risk threshold, stress risk threshold and electric field risk threshold, respectively analyze the hot spot anomaly, stress anomaly and electric field anomaly of the hot spot, high stress area and high electric field area;

[0142] Based on the hot spot anomaly, stress anomaly, and electric field anomaly, determining an abnormal design defect of the coupled 3D packaging structure layout;

[0143] Analyze the design defect characteristics of the abnormal design defect;

[0144] Based on the design defect characteristics, construct an optimization strategy for the coupled 3D packaging structure layout;

[0145] The coupled 3D packaging structure layout is optimized according to the optimization strategy to obtain a target packaging structure layout.

[0146] Among them, the hot spot risk threshold refers to a preset temperature value, exceeding which may cause overheating problems in certain areas of the packaging structure, the stress risk threshold refers to a preset stress value, exceeding which may cause mechanical failures in certain areas of the packaging structure, the electric field risk threshold refers to a preset electric field strength value, exceeding which may cause electrical breakdown or arc discharge in certain areas of the packaging structure, affecting the electrical performance and safety of the device, the hot spot anomaly refers to an area exceeding the hot spot risk threshold in the temperature distribution found in simulation or experiment, the stress anomaly refers to an area exceeding the stress risk threshold in the stress distribution found in simulation or experiment, the electric field anomaly refers to an area exceeding the electric field risk threshold in the electric field distribution found in simulation or experiment, the abnormal design defect refers to a design problem that causes hot spot anomaly, stress anomaly or electric field anomaly. These defects may be due to inappropriate material selection, unreasonable geometric design, insufficient cooling measures or other factors that are not well considered in design, the design defect feature refers to the specific attributes that describe the abnormal design defect, including the location, shape, size, impact range and cause of the defect, etc., and the optimization strategy refers to a series of measures taken to solve specific design defects. These strategies may include changing design parameters, material selection, manufacturing processes or using new design concepts. The target package structure layout refers to the final package structure design that is optimized to meet all performance and reliability requirements and has no hot spot anomalies, stress anomalies and electric field anomalies.

[0147] Optionally, based on the hot spot anomaly, stress anomaly and electric field anomaly, the abnormal design defects of the coupled 3D packaging structure layout are determined; and the analysis can be performed using thermodynamic finite element analysis, static and dynamic structural analysis and electromagnetic finite element analysis.

[0148] S4. Based on the target packaging structure layout, construct the TSV and micro-bumps of the storage chip to be packaged, construct the redistribution layer of the packaging material corresponding to the packaging substrate, and according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material, stack the storage chip to be packaged in multiple layers to obtain a multi-layer stacked storage chip.

[0149] The present invention constructs TSVs and micro-bumps of the memory chip to be packaged based on the target packaging structure layout, and can construct TSVs and micro-bumps that meet the requirements of the target packaging structure layout, thereby achieving high-density and high-performance packaging of the memory chip.

[0150] It should be explained that TSV refers to the vertical channel created on the chip, and micro-bumps refer to the metal protrusions located on the surface of the chip. TSV is used for vertical connection inside the chip, while micro-bumps are used for horizontal connection between chips, together forming a complex 3D packaging structure.

[0151] Optionally, the present invention constructs a redistribution layer corresponding to the packaging substrate of the packaging material to construct a redistribution layer that meets specific packaging requirements, providing a reliable path for signal transmission between the chip and the external circuit. Wherein, the redistribution layer refers to a conductive layer added in addition to the original signal layer in a multi-layer PCB or packaging substrate to meet specific design requirements (such as signal integrity, power and ground plane allocation, thermal management, space constraints, etc.).

[0152] The present invention performs multi-layer stacking of the memory chip to be packaged according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a packaging solution for the multi-layer stacked memory chip to achieve high density and high performance.

[0153] In detail, the memory chip to be packaged is stacked in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip, including:

[0154] Placing the memory chip to be packaged on the packaging substrate corresponding to the packaging material, and aligning the micro-bumps and the redistribution layer corresponding to the memory chip to be packaged to obtain an aligned micro-bump-redistribution layer;

[0155] Hot pressing the aligned micro-bump-rewiring layer to obtain a connected micro-bump-rewiring layer;

[0156] Using the TSV and the target package structure layout, the connection micro-bump-rewiring layer is connected to obtain a multi-layer connection memory chip;

[0157] The multi-layer connected memory chip is welded by using the corresponding solder of the packaging material to obtain the multi-layer stacked memory chip.

[0158] Among them, the aligned micro-bump-rewiring layer refers to the precise alignment of the micro-bumps on the memory chip to be packaged with the rewiring layer on the packaging substrate during the packaging process; the connected micro-bump-rewiring layer refers to a layer formed by combining the metal contact surfaces between the micro-bumps and the rewiring layer through hot pressing or other connection technologies; the multi-layer connected memory chip refers to a memory chip structure in which multiple memory chips are stacked up through the above-mentioned connection steps and electrical connections between layers are achieved through micro-bumps and TSV; the multi-layer stacked memory chip refers to the final three-dimensional stacked memory chip product formed after completing all interlayer connection and welding steps.

[0159] Optionally, the multi-layer connected storage chips are welded by using the corresponding solder of the packaging material, so that the solder of the multi-layer stacked storage chips is solidified by overheating to ensure the reliability of the connection.

[0160] S5. Use the self-repairing material corresponding to the packaging material to package the multi-layer stacked memory chip to obtain a packaged multi-layer stacked memory chip, and collect packaging status data of the packaged multi-layer stacked memory chip. Based on the packaging status data, use a preset material repair algorithm to activate the packaging repair of the self-repairing material to obtain a packaging repair material, and perform multi-layer stacking packaging of the memory chip to be packaged based on the packaging repair material.

[0161] The present invention utilizes the packaging material corresponding to the self-repairing material to encapsulate the multi-layer stacked memory chip, and the encapsulated multi-layer stacked memory chip can improve the long-term stability and reliability of the chip, especially in harsh environments or under mechanical stress. It should be explained that the self-repairing material refers to an intelligent material that can automatically repair itself without external intervention when damage (such as cracks, holes or debonding) occurs inside the material. The encapsulated multi-layer stacked memory chip refers to integrating multiple memory chips together by vertically stacking to form a high-density, high-performance storage unit. The encapsulation state data refers to various data related to the packaging process and the performance of the product after packaging. These data may include, but are not limited to, temperature, humidity, mechanical stress, electrical properties, thermal resistance, damage, etc.

[0162] Finally, based on the packaging status data, the present invention utilizes a preset material repair algorithm to activate the packaging repair of the self-repairing material, and obtains a packaging repair material that can achieve effective self-repair of the self-repairing material in the packaged multi-layer stacked memory chip, thereby ensuring the long-term stability and reliability of the package.

[0163] In detail, based on the packaging state data, using a preset material repair algorithm to activate the packaging repair of the self-repairing material to obtain the packaging repair material includes:

[0164] Based on the packaging status data, identifying material loss of the self-healing material;

[0165] identifying a material loss characteristic of the material loss;

[0166] Calculating a loss coefficient of the material loss according to the material loss characteristics;

[0167] When the loss coefficient meets a preset loss coefficient threshold, activating a self-repairing reaction of the self-repairing material using the material repair algorithm;

[0168] Based on the self-repairing reaction, the self-repairing material is packaged and repaired to obtain the packaged and repaired material.

[0169] Among them, the material loss refers to the performance degradation or structural damage of the self-repairing material caused by various reasons (such as mechanical stress, thermal cycle, chemical corrosion, etc.) during packaging or use. This may be micro cracks, macro cracks, holes or other forms of defects. The material loss characteristics refer to the specific attributes of the material loss, including but not limited to the size, shape, location, type, distribution pattern, depth, etc. of the loss. The loss coefficient is a parameter that quantifies the severity of the material loss. The loss coefficient threshold is a preset standard used to determine whether the material loss is serious enough to trigger a self-repair reaction. The material repair algorithm is a set of pre-designed calculation programs that analyze and determine when and how to activate the self-repair reaction based on the packaging state data and material loss characteristics. The algorithm may include steps such as data analysis, pattern recognition, and decision making. The self-repair reaction refers to a series of chemical reactions or physical processes occurring inside the self-repairing material, which can automatically fill the material loss area and restore or partially restore the original performance of the material. The packaging repair material refers to the packaging material whose material loss is repaired after the self-repair reaction.

[0170] Optionally, based on the self-repairing reaction, the self-repairing material is packaged and repaired, and the catalyst or repair agent in the packaged repair material self-repairing material starts to react to repair the damaged area. Exemplarily, for a thermally responsive self-repairing material, it may be necessary to heat it to a certain temperature to start the repair reaction, and the self-repairing material solidifies or cross-links in the damaged area to form new chemical bonds and restore the structure and performance of the material.

[0171] Compared with the problems described in the background technology, the present invention obtains the packaging requirements of the memory chip to be packaged, and according to the packaging requirements, determines the packaging materials and packaging environment of the memory chip to be packaged, which can be used as data basis for constructing a 3D packaging structure layout that meets specific requirements; further, the present invention can ensure that the packaging meets predetermined performance and reliability requirements by constructing the physical field of the 3D packaging structure layout, thereby improving the packaging effect of multi-layer stacked memory chips; further, the present invention calculates the hot spots, high stress areas and high electric field areas of the coupled 3D packaging structure layout to provide a basis for subsequent optimization of the packaging structure layout; further, the present invention optimizes the coupled 3D packaging structure layout based on the hot spots, high stress areas and high electric field areas, and obtains an optimized target packaging structure layout, which can improve thermal management efficiency, mechanical strength and electrical reliability while ensuring performance; further, the present invention is based on the The target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged can construct TSV and micro-bumps that meet the requirements of the target packaging structure layout, thereby realizing high-density and high-performance packaging of the memory chip. Next, the present invention performs multi-layer stacking of the memory chip to be packaged according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material, and obtains a packaging solution for a multi-layer stacked memory chip to achieve high density and high performance. Finally, the present invention uses the packaging material to encapsulate the multi-layer stacked memory chip corresponding to the self-repairing material to obtain a packaged multi-layer stacked memory chip. The long-term stability and reliability of the chip can be improved and based on the packaging state data, the packaging repair of the self-repairing material is activated by a preset material repair algorithm, and the packaging repair material can achieve effective self-repair of the self-repairing material in the packaged multi-layer stacked memory chip, ensuring the long-term stability and reliability of the package. Therefore, the present invention can improve the packaging stability of the multi-layer stacked memory chip.

[0172] Embodiment 2:

[0173] like Figure 2 1 is a functional module diagram of a packaging system for multi-layer stacked memory chips provided by an embodiment of the present invention.

[0174] The packaging system 200 of the multi-layer stacked memory chip of the present invention can be installed in an electronic device. According to the functions to be implemented, the packaging system 200 of the multi-layer stacked memory chip can include a 3D packaging structure layout construction module 201, a packaging structure layout coupling module 202, a packaging structure layout optimization module 203, a memory chip multi-layer stacking module 204 and a multi-layer stacked memory chip packaging module 205. The module of the present invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0175] In this embodiment, the functions of each module / unit are as follows:

[0176] The 3D packaging structure layout construction module 201 is used to obtain the packaging requirements of the memory chip to be packaged, determine the packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and construct the 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements;

[0177] The packaging structure layout coupling module 202 is used to construct the physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field and a mechanical field, define the field action relationship of the physical field, and based on the field action relationship, integrate the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout;

[0178] The package structure layout optimization module 203 is used to calculate the hot spots, high stress areas and high electric field areas of the coupled 3D package structure layout, and optimize the coupled 3D package structure layout based on the hot spots, high stress areas and high electric field areas to obtain a target package structure layout;

[0179] The memory chip multi-layer stacking module 204 is used to construct the TSV and micro-bumps of the memory chip to be packaged based on the target packaging structure layout, construct the redistribution layer of the packaging material corresponding to the packaging substrate, and stack the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip;

[0180] The multi-layer stacked memory chip packaging module 205 is used to package the multi-layer stacked memory chip using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and collect packaging status data of the packaged multi-layer stacked memory chip, based on the packaging status data, activate the packaging repair of the self-repairing material using a preset material repair algorithm to obtain a packaging repair material, and perform multi-layer stacking packaging of the memory chip to be packaged based on the packaging repair material.

[0181] In detail, each module described in the packaging system 200 of the multi-layer stacked memory chip described in the embodiment of the present invention adopts the same technical means as the packaging method of the multi-layer stacked memory chip described in the accompanying drawings when used, and can produce the same technical effects, which will not be repeated here.

[0182] An embodiment of the present invention provides an electronic device for implementing a packaging method for multi-layer stacked memory chips.

[0183] See also Figure 3 As shown, the electronic device may include a processor 30, a memory 31, a communication bus 32 and a communication interface 33, and may also include a computer program stored in the memory 31 and executable on the processor 30, such as a packaging method program for multi-layer stacked memory chips.

[0184] In some embodiments, the processor may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules stored in the memory (for example, executing a packaged program of a multi-layer stacked memory chip, etc.), and calls data stored in the memory to execute various functions of the electronic device and process data.

[0185] The memory includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (for example: SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. The memory may be an internal storage unit of an electronic device in some embodiments, such as a mobile hard disk of the electronic device. The memory may also be an external storage device of an electronic device in other embodiments, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory may also include both an internal storage unit of the electronic device and an external storage device. The memory may not only be used to store application software and various types of data installed in the electronic device, such as the code of a packaged program based on a multi-layer stacked memory chip, but may also be used to temporarily store data that has been output or is to be output.

[0186] The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The bus is configured to realize connection and communication between the memory and at least one processor, etc.

[0187] The communication interface is used for communication between the above-mentioned electronic device and other devices, including a network interface and a user interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device and other electronic devices. The user interface may be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally, the user interface may also be a standard wired interface, a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode, organic light-emitting diode) touch device, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device and to display a visual user interface.

[0188] For example, although not shown, the electronic device may also include a power source (such as a battery) for supplying power to each component. Preferably, the power source may be logically connected to the at least one processor through a power management system, so that the power management system can realize functions such as charging management, discharging management, and power consumption management. The power source may also include any components such as one or more DC or AC power sources, recharging systems, power failure detection circuits, power converters or inverters, and power status indicators. The electronic device may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0189] It should be understood that the embodiment is for illustration only and the scope of the patent application is not limited to this structure.

[0190] The packaged program of the multi-layer stacked memory chip stored in the memory in the electronic device is a combination of multiple instructions, which, when executed in the processor, can achieve:

[0191] Obtaining packaging requirements of the memory chip to be packaged, determining packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements;

[0192] Constructing a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field, and a mechanical field, defining a field action relationship of the physical field, and integrating the physical field and the field action relationship into the 3D packaging structure layout based on the field action relationship to obtain a coupled 3D packaging structure layout;

[0193] Calculating hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout;

[0194] Based on the target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged, constructing the redistribution layer of the packaging material corresponding to the packaging substrate, and stacking the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip;

[0195] The multi-layer stacked memory chip is packaged using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and packaging status data of the packaged multi-layer stacked memory chip is collected. Based on the packaging status data, the packaging repair of the self-repairing material is activated using a preset material repair algorithm to obtain a packaging repair material, and based on the packaging repair material, multi-layer stacking packaging of the memory chip to be packaged is performed.

[0196] Specifically, the specific implementation method of the processor for the above instructions can refer to the description of the relevant steps in the corresponding embodiment of the accompanying drawings, which will not be repeated here.

[0197] Furthermore, if the module / unit integrated in the electronic device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0198] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement:

[0199] Obtaining packaging requirements of the memory chip to be packaged, determining packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements;

[0200] Constructing a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field, and a mechanical field, defining a field action relationship of the physical field, and integrating the physical field and the field action relationship into the 3D packaging structure layout based on the field action relationship to obtain a coupled 3D packaging structure layout;

[0201] Calculating hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout;

[0202] Based on the target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged, constructing the redistribution layer of the packaging material corresponding to the packaging substrate, and stacking the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip;

[0203] The multi-layer stacked memory chip is packaged using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and packaging status data of the packaged multi-layer stacked memory chip is collected. Based on the packaging status data, the packaging repair of the self-repairing material is activated using a preset material repair algorithm to obtain a packaging repair material, and based on the packaging repair material, multi-layer stacking packaging of the memory chip to be packaged is performed.

[0204] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0205] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0206] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0207] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0208] Therefore, no matter from which point of view, the embodiments should be regarded as illustrative and non-restrictive, and the scope of the present invention is limited by the appended claims rather than the above description, so it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any attached figure mark in the claims should not be regarded as limiting the claims involved.

[0209] The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Among them, artificial intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0210] In addition, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim can also be implemented by one unit or system through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any particular order.

Claims

1. A packaging method for a multi-layer stacked memory chip, characterized in that: The method comprises: Obtaining packaging requirements of the memory chip to be packaged, determining packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements; Constructing a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field, and a mechanical field, defining a field action relationship of the physical field, and integrating the physical field and the field action relationship into the 3D packaging structure layout based on the field action relationship to obtain a coupled 3D packaging structure layout; Calculating hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout, and optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout; Based on the target packaging structure layout, constructing the TSV and micro-bumps of the memory chip to be packaged, constructing the redistribution layer of the packaging material corresponding to the packaging substrate, and stacking the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip; The multi-layer stacked memory chip is packaged using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and packaging status data of the packaged multi-layer stacked memory chip is collected. Based on the packaging status data, the packaging repair of the self-repairing material is activated using a preset material repair algorithm to obtain a packaging repair material, and based on the packaging repair material, multi-layer stacking packaging of the memory chip to be packaged is performed.

2. The packaging method of the multi-layer stacked memory chip according to claim 1, characterized in that: The step of constructing a 3D packaging structure layout of the memory chip to be packaged based on the packaging material, the packaging environment and the packaging requirement includes: Identifying memory chip characteristics of the memory chip to be packaged; Determining the key packaging parameters of the memory chip to be packaged according to the packaging requirements, wherein the key packaging parameters include size, thermal resistance and electrical characteristics; Based on the key packaging parameters, determining the packaging structure components of the memory chip to be packaged; The 3D packaging structure layout of the memory chip to be packaged is planned based on the memory chip characteristics, the key packaging parameters, the packaging materials, the packaging environment and the packaging structure components, wherein the chip packaging layout includes chip layout, interconnection paths and heat dissipation paths.

3. The packaging method of the multi-layer stacked memory chip according to claim 2, characterized in that: The physical field for constructing the 3D packaging structure layout includes: Performing finite element meshing on the 3D packaging structure layout to obtain a meshed packaging structure layout; Defining thermal field parameters, thermal field boundary conditions, electric field parameters, electric field boundary conditions, mechanical field parameters and mechanical field boundary conditions of the grid packaging structure layout; Constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions; The electric field analysis function of the grid packaging structure layout is constructed by using the electric field parameters and the electric field boundary conditions using the following formula, wherein the electric field analysis function: in, represents the gradient operator, E represents the electric potential of the grid package structure layout under the electric field boundary condition, ε0 represents the permittivity of the electric field parameter in vacuum, Δε(e) represents the change in capacitance at position e under the electric field boundary condition, σ0 represents the background charge density of the grid package structure layout under the electric field boundary condition, Δσ(e) represents the charge density disturbance at position e under the electric field boundary condition, and e represents the position e of the grid package structure layout; Based on the mechanical field parameters and the mechanical field boundary conditions, constructing a mechanical field analysis function of the gridded packaging structure layout; Constructing the thermal field, electric field and mechanical field of the grid packaging structure layout through the thermal field analysis function, the electric field analysis function and the mechanical field analysis function; The thermal field, electric field and mechanical field are combined to construct a physical field of the grid packaging structure layout.

4. The packaging method of the multi-layer stacked memory chip according to claim 3, characterized in that: The step of constructing a thermal field analysis function of the gridded packaging structure layout according to the thermal field parameters and the thermal field boundary conditions includes: Determine the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate of the gridded packaging structure layout based on the thermal field parameters and the thermal field boundary conditions; According to the thermal conductivity, temperature distribution, heat source term, material density, specific heat capacity, and temperature-time change rate, the following formula is used to construct a thermal field analysis function of the grid packaging structure layout, wherein the thermal field analysis function is: in, represents the gradient operator, α represents the thermal conductivity, T represents the temperature distribution of the grid packaging structure layout, P represents the heat source term, ρ represents the material density, γ represents the specific heat capacity, represents the derivative function, It represents the rate of change of temperature over time.

5. The packaging method of the multi-layer stacked memory chip according to claim 4, characterized in that: The field action relationship of defining the physical field includes: Simulating the action data of the physical field; Based on the action data, a thermo-electric action function, a thermo-mechanical action function and an electro-mechanical action function of the physical field are constructed; wherein the thermo-mechanical action function: Among them, τ th represents thermal stress, θ represents the thermal expansion coefficient in the action data, m represents the elastic modulus in the action data, ΔB represents the temperature change in the action data, represents Poisson's ratio; The thermo-electric action function: R(S)=R0[1+alpha_R(S-S0)] Wherein, R(S) represents the resistance at temperature S in the action data, R0 represents the resistance at reference temperature S0 in the action data, and alpha_R represents the resistance temperature coefficient; The electro-mechanical action function: epsilon = pi_c·m·m_field Among them, epsilon represents the electrostrictive strain in the action data, pi_c represents the electrostrictive coefficient in the action data, m represents the elastic modulus in the action data, and m_field represents the electric field intensity in the action data; The field action relationship of the physical field is defined according to the thermo-electric action function, the thermo-mechanical action function and the electro-mechanical action function.

6. The packaging method of the multi-layer stacked memory chip according to claim 5, characterized in that: The calculating, based on the battery parameters, hot spots, high stress areas, and high electric field areas of the coupled 3D packaging structure layout includes: Simulating the coupled 3D packaging structure layout to obtain simulation data; Analyzing the layout temperature distribution, layout stress distribution and layout electric field distribution of the coupled 3D packaging structure layout through the simulation data; Calculating hot spots of the coupled 3D packaging structure layout based on the layout temperature distribution; Marking high stress areas of the coupled 3D packaging structure layout according to the layout stress distribution; The high electric field area of ​​the coupled 3D packaging structure layout is marked by the layout electric field distribution.

7. The packaging method of the multi-layer stacked memory chip according to claim 6, characterized in that: The step of optimizing the coupled 3D packaging structure layout based on the hot spots, high stress areas, and high electric field areas to obtain a target packaging structure layout includes: Using the preset hot spot risk threshold, stress risk threshold and electric field risk threshold, respectively analyze the hot spot anomaly, stress anomaly and electric field anomaly of the hot spot, high stress area and high electric field area; Based on the hot spot anomaly, stress anomaly, and electric field anomaly, determining an abnormal design defect of the coupled 3D packaging structure layout; Analyze the design defect characteristics of the abnormal design defect; Based on the design defect characteristics, construct an optimization strategy for the coupled 3D packaging structure layout; The coupled 3D packaging structure layout is optimized according to the optimization strategy to obtain a target packaging structure layout.

8. The packaging method of the multi-layer stacked memory chip according to claim 7, characterized in that: The method of stacking the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip comprises: Placing the memory chip to be packaged on the packaging substrate corresponding to the packaging material, and aligning the micro-bumps and the redistribution layer corresponding to the memory chip to be packaged to obtain an aligned micro-bump-redistribution layer; Hot pressing the aligned micro-bump-rewiring layer to obtain a connected micro-bump-rewiring layer; Using the TSV and the target package structure layout, the connection micro-bump-rewiring layer is connected to obtain a multi-layer connection memory chip; The multi-layer connected memory chip is welded by using the corresponding solder of the packaging material to obtain the multi-layer stacked memory chip.

9. The packaging method of multi-layer stacked memory chip according to claim 8, characterized in that: The method of activating the packaging repair of the self-repairing material based on the packaging state data by using a preset material repair algorithm to obtain a packaging repair material includes: Based on the packaging status data, identifying material loss of the self-healing material; identifying a material loss characteristic of the material loss; Calculating a loss coefficient of the material loss according to the material loss characteristics; When the loss coefficient meets a preset loss coefficient threshold, activating a self-repairing reaction of the self-repairing material using the material repair algorithm; Based on the self-repairing reaction, the self-repairing material is packaged and repaired to obtain the packaged and repaired material.

10. A packaging system for multi-layer stacked memory chips, characterized in that: A system for executing a packaging method for a multi-layer stacked memory chip according to any one of claims 1 to 9, the system comprising: A 3D packaging structure layout construction module is used to obtain the packaging requirements of the memory chip to be packaged, determine the packaging materials and packaging environment of the memory chip to be packaged according to the packaging requirements, and construct the 3D packaging structure layout of the memory chip to be packaged based on the packaging materials, the packaging environment and the packaging requirements; A packaging structure layout coupling module, used to construct a physical field of the 3D packaging structure layout, wherein the physical field includes a thermal field, an electric field and a mechanical field, define a field action relationship of the physical field, and based on the field action relationship, integrate the physical field and the field action relationship into the 3D packaging structure layout to obtain a coupled 3D packaging structure layout; A package structure layout optimization module, used to calculate the hot spots, high stress areas and high electric field areas of the coupled 3D package structure layout, and optimize the coupled 3D package structure layout based on the hot spots, high stress areas and high electric field areas to obtain a target package structure layout; A memory chip multi-layer stacking module is used to construct TSV and micro-bumps of the memory chip to be packaged based on the target packaging structure layout, construct a redistribution layer of the packaging material corresponding to the packaging substrate, and stack the memory chip to be packaged in multiple layers according to the TSV, the micro-bumps, the redistribution layer, the target packaging structure layout and the packaging material to obtain a multi-layer stacked memory chip; A multi-layer stacked memory chip packaging module is used to package the multi-layer stacked memory chip using the self-repairing material corresponding to the packaging material to obtain a packaged multi-layer stacked memory chip, and collect packaging status data of the packaged multi-layer stacked memory chip, based on the packaging status data, activate the packaging repair of the self-repairing material using a preset material repair algorithm to obtain a packaging repair material, and perform multi-layer stacking packaging of the memory chip to be packaged based on the packaging repair material.

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