Processor low-power-consumption state switching method based on RISC-V server platform

Abstract

The invention relates to a processor low-power-consumption state switching method based on an RISC-V server platform, and belongs to the technical field of computers. The method comprises the following steps: (1) configuring multi-stage low-power-consumption state information of the RISC-V processor; (2) initializing a CPU idle state management module by utilizing the multi-stage low-power-consumption state information; (3) the CPU idle state management module selects an optimal low-power-consumption state for the RISC-V processor based on a control strategy of a reinforcement learning SARSA algorithm; and (4) enabling the RISC-V processor to enter a specified low-power-consumption state. According to the invention, efficient power management of the RISC-V processor on a server platform is realized, the energy consumption can be obviously reduced while the system performance is ensured, the energy efficiency ratio of the server is effectively improved, and the method is particularly suitable for power management of a large-scale server cluster and construction of a green data center.

Description

Technical Field

[0001] The invention relates to a processor low-power state switching method based on a RISC-V server platform, and belongs to the technical field of computers. Background Art

[0002] In the RISC-V architecture, ACPI (Advanced Configuration and Power Interface) is an important standard interface for implementing power management. In traditional x86 and ARM processors, ACPI is widely used to define and manage the power state of the system. As RISC-V is gradually applied in servers and embedded systems, the RISC-V ecosystem has also begun to support ACPI to better compatibility with existing operating systems and hardware management software.

[0003] Processor states (C-States) are part of ACPI power management and are used to represent different energy-saving states of the processor when it is idle. The levels of C-States range from C0 to Cn, where C0 means the processor is working, and C1 to Cn represent different depths of sleep states. The deeper the C-State, the lower the power consumption, but the delay in returning to the working state may be higher. Through ACPI, the operating system can dynamically monitor and manage the C-States of the processor, and then adjust the power consumption and performance of the processor according to the system load to achieve power optimization.

[0004] Implementing processor state (C-States) transitions in the RISC-V architecture is critical because it directly affects the energy efficiency and performance management of the system. Processor state transitions allow RISC-V processors to enter deeper power-saving states when idle or under load, significantly reducing power consumption, which is particularly critical in servers, mobile devices, and embedded systems. By efficiently managing C-States, the RISC-V architecture is able to dynamically adjust the processor's operating state to balance performance requirements and power consumption constraints, improve power utilization efficiency, extend battery life, and reduce heat dissipation and operating costs in scenarios such as data centers. Therefore, implementing processor state transitions is a key factor in the expansion of RISC-V applications, especially in the field of low-power and efficient computing. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a processor low-power state switching method for a RISC-V server platform, aiming to reduce the power consumption of the RISC-V server platform when it is under low load or idle, and achieve efficient energy consumption management.

[0006] Terminology explanation: 1. RISC-V: RISC-V is an open source instruction set architecture that adopts the concepts of reduced instruction set, modular design, and scalability. This makes the RISC-V processor simple to design, low cost, and can be flexibly expanded according to demand. This design flexibility makes RISC-V suitable for a variety of different application scenarios, including embedded systems, servers, high-performance computing, and IoT devices.

[0007] 2. UEFI (Unified Extensible Firmware Interface): UEFI is a firmware interface specification designed to replace the traditional BIOS (Basic Input / Output System). It provides a more flexible and standardized boot solution that can load operating systems and applications, and provides more powerful hardware initialization and configuration functions.

[0008] 3. ACPI (Advanced Configuration and Power Interface): ACPI is an advanced configuration and power interface, a standard interface for implementing advanced configuration and power management. It aims to provide a unified interface between the operating system and computer hardware for energy management and hardware configuration.

[0009] 4. OSPM (Open Source Power Management): OSPM is an open source energy management framework that aims to provide effective energy management and optimization solutions for computer systems. OSPM is committed to developing portable, flexible and extensible software tools to support various operating systems and hardware platforms.

[0010] 5. Differential System Description Table (DSDT): DSDT contains information related to system-specific hardware. By defining devices, resources, methods, and events in the ACPI namespace, it provides the operating system and firmware with key information for dynamically configuring hardware and managing power at runtime.

[0011] 6. CPU Idle Management (CPUIdle): A subsystem of the Linux kernel that manages the transition of CPU idle states. It monitors the CPU load and automatically selects different idle states based on the length of idle time, thereby saving power when the processor is not working. The CPUIdle framework will decide which low-power state to enter based on factors such as the current system load and task scheduling when the CPU enters idle mode, and quickly restore it to the working state when a task arrives. This mechanism is crucial for saving power, improving battery life, and optimizing system performance.

[0012] 7. Control strategy (Governor): In the Linux kernel, Governor is a scheduling strategy module that is responsible for dynamically managing the CPU frequency and power state to achieve a balance between performance and power consumption. Different Governors will adjust the CPU's operating frequency and idle state in real time based on factors such as system load, temperature, and user needs.

[0013] 8. Low Power Idle (_LPI): _LPI is an object defined in the ACPI specification that describes the low power state that system components can enter when idle. Through the _LPI object, the system can identify and manage the low power modes of different hardware components to reduce energy consumption when idle.

[0014] 9. SBI (Supervisor Binary Interface) firmware service: SBI firmware service is a standard interface provided for the operating system kernel in the RISC-V architecture, which is used to implement access to low-level system functions between the operating system and the hardware. The SBI service is responsible for handling some hardware-related operations, such as power management, timer configuration, and interrupt control, and especially plays a bridging role between different privilege levels.

[0015] 10. Reinforcement Learning: Reinforcement learning is a machine learning method in which an agent learns decision-making strategies by interacting with the environment to achieve goals in a specific task. The agent obtains feedback (rewards or penalties) from the environment by trying different actions and uses this feedback to adjust its strategy to maximize long-term benefits. It is particularly suitable for solving problems in dynamic, complex, and incompletely determined environments, such as robot control, game strategy, and resource allocation.

[0016] 11. SARSA (State-Action-Reward-State-Action): SARSA is a reinforcement learning algorithm for agents to learn optimal strategies in dynamic environments by interacting with the environment. It updates the strategy based on the current state and action and the subsequent reward and new state, making the agent more efficient in future decisions. By associating the current state-action pair with the next state-action pair, SARSA is able to gradually improve decision-making in dynamic environments and is suitable for scenarios that require online learning.

[0017] The technical solution of the present invention is as follows: A method for switching a processor to a low-power state of a RISC-V server platform, the steps are as follows: (1) Configure the multi-level low power state information of the RISC-V processor in the DSDT table of the ACPI firmware; (2) The ACPI driver module in the operating system uses the multi-level low-power state information of the RISC-V processor in the DSDT table to initialize the CPU idle state management module; (3) The CPU idle state management module selects the optimal low-power state for the RISC-V processor based on the control strategy of the reinforcement learning SARSA algorithm; (4) The operating system calls the SBI firmware service to put the RISC-V processor into a specified low-power state.

[0018] Preferably, according to the present invention, in step (1), the multi-level low power consumption state information is: The low power state object is defined in the DSDT table of the ACPI firmware, which provides complete information about the low power state, including the minimum dwell time, the worst case wake-up delay, the dwell counter frequency, the dwell counter register, the entry method, and the state name. The _LPI object uses a resource descriptor to specify the entry method of the processor low power state. The processor state transition of the RISC-V system is implemented using the SBI HSM extension.

[0019] According to the preferred embodiment of the present invention, in step (2), specifically: the CPU idle state management module includes a core component, a control strategy component and a driver component. The core component is the center of the entire idle management system and is responsible for coordinating the workflow of the CPU idle state management. Through the interface provided by the core component, other modules of the operating system can request the CPU to enter the idle state. The core component will select a suitable idle state according to the instructions of the control strategy, thereby realizing power consumption optimization. The core component is also responsible for managing the state transition of different processors to ensure the reasonable allocation of idle states in a multi-core system. The control strategy component determines which idle state the system should choose under different loads. The control strategy component uses the SARSA algorithm to dynamically optimize the idle state selection process by introducing the idea of ​​reinforcement learning. While considering the balance between power consumption and performance, it continuously adjusts and improves the correction factor of idle state selection, so that the system can adapt to complex load changes and achieve more accurate and efficient decision-making. The driver component is the part that deals with specific hardware and is responsible for implementing the actual state transition. It places the CPU in the corresponding C-State based on the selection of the control strategy and manages the hardware details during the state transition process. The driver component also provides the core component with a list of available C-States and provides feedback on the execution status of the state transition.

[0020] The initialization process includes the core component initialization process, the control strategy component initialization process and the driver component initialization process.

[0021] According to the present invention, it is further preferred that the core component initialization process is to initialize the key variables and functions required for idle state management. First, the key variables are initialized, that is, the variables for storing registered device nodes. Then, the functions are initialized one by one for entering the idle state, selecting the idle state, and recording the idle state, providing the core functions of idle state management.

[0022] Preferably, according to the present invention, the control strategy component initialization process is as follows: first, define and initialize a scheduler structure, including the name, score and two key function pointers of the scheduler, which are used to select an idle state and reflect state changes respectively; then, call a registration function to register the scheduler structure; this process ensures that the scheduler is correctly loaded when the system starts and can perform state management according to system requirements at runtime; the registration operation of the scheduler is usually completed in the kernel's post-core initialization phase, ensuring that it is initialized and ready to provide services in the early stages of the system.

[0023] Preferably, according to the present invention, the driver component initialization process is to register the device driver and perform the initialization operation when the device is started.

[0024] The driver component extracts the low-power state description information related to the RISC-V processor by parsing the DSDT table. The specific low-power state object is determined by the architecture and hardware resources of the processor, and usually includes multiple low-power states, such as "RISC-V WFI", "RISC-V RET_DEFAULT" and "RISC-V NONRET_DEFAULT". Each state object has different parameters and characteristics, such as minimum residence time, worst wake-up delay, counting frequency and dependency on the parent state. Specifically, the "RISC-V WFI" state has a shorter minimum residence time and wake-up delay, which is suitable for quickly entering low-power mode, while the "RISC-V The "NONRET_DEFAULT" state has a longer residence time and wake-up delay, which is suitable for a deeper low-power mode. The driver component classifies and manages different low-power states according to the characteristics, generates corresponding management entries, and maintains a low-power state table when the system is running. These table items include key parameters such as exit delay, target residence time, and power consumption, and are uniformly described through the "CPU idle state" structure to ensure that each CPU can enter different low-power modes according to specific hardware requirements. Then, the driver component will set the corresponding callback function so that the CPU power consumption state can be dynamically adjusted when needed.

[0025] According to the preferred embodiment of the present invention, in step (3), specifically: The control strategies include ladder strategy and menu strategy. The ladder strategy is a simple fixed-order strategy, that is, to reach a higher level, you must go up step by step from the lower level. In the ladder strategy, the ladder governor will first enter the shallowest Idle state, and then if it stays long enough, it will enter a deeper Idle state, and so on, until it reaches the deepest Idle state. When it is awakened, it will restart the CPU as quickly as possible; when it is idle next time, it will start from the shallowest Idle state. In this strategy, the system may not enter the deepest Idle state for a long time, resulting in some loss of power consumption. The ladder strategy is not suitable for server platforms with large load changes.

[0026] The menu strategy is an intelligent dynamic strategy that mainly selects the best C-State idle state based on the predicted time (expected stay time) and the system's delay tolerance, thereby achieving a more balanced optimization between performance and power consumption. The Idle Menu controller decides which idle state to enter based on the CPU load, the next timer event time, the number of active I / O threads, etc.

[0027] In the process of calculating the predicted idle time, the Menu controller gives a predicted value based on the time of the next timer event. However, since the time point of the next timer event may be interfered by other events, resulting in a deviation in the actual idle time, a set of correction factors needs to be introduced to further adjust the predicted value. The correction factor is based on past experience data, especially the ratio of past prediction time to actual event time, and is calculated by a dynamic average algorithm. In order to improve the accuracy of the prediction, the Menu controller uses 12 different correction factors, corresponding to different time periods. The value of each correction factor is adjusted according to the fluctuation of historical data to adapt to different system behaviors, especially in different io waiting scenarios. The Menu controller checks the consistency of the time interval through the latest 8 residence times. If the standard deviation of these time intervals is less than the threshold, the average value of the 8 residence times is selected as the supplementary prediction value, and the minimum value of the above two prediction values ​​is taken as the final prediction time, so as to more accurately adjust the CPU idle state to optimize energy efficiency. The Menu controller uses the performance multiplier, the expected residence time, and the system delay requirement to calculate the system delay tolerance. The system delay requirement is used as the first system tolerance. The other system tolerance is calculated by the formula: expected residence time / (1+10*number of IO waiting tasks on the current CPU). The minimum value of the two system tolerances is taken as the system delay tolerance. Select an idle state based on the predicted time (expected stay time) and system delay tolerance, compare the predicted time with the stay time of all Idle states, and select a specific Idle state if the corresponding stay time is less than the predicted time. In addition, compare the exit delay of the state with the system delay tolerance. The exit delay of the state must be less than the system delay tolerance. Select the idle state that meets the two conditions and has the lowest power consumption as the optimal low-power state.

[0028] The Menu controller is responsible for selecting the appropriate idle state. Although the deep idle state can significantly save power consumption, it requires additional entry and exit overhead and increases latency. Therefore, in order to achieve a better balance between power consumption and performance, the present invention uses the idea of ​​reinforcement learning to dynamically adjust and improve the idle state selection process. Reinforcement learning is a method in which an intelligent agent obtains rewards and updates its decision-making strategy by interacting with the environment. Initially, the intelligent agent understands the environment and takes actions according to the initial strategy. The environment then feeds back new state information and reward values. The intelligent agent dynamically adjusts its strategy based on these feedbacks. In this process, the agent moves from the current state to the next state and improves its decision through reward and punishment feedback.

[0029] Preferably, according to the present invention, the idle state selection strategy is optimized by using the SARSA algorithm. The SARSA algorithm is a policy-based reinforcement learning algorithm suitable for online decision-making problems. The algorithm updates the Q value based on the state-action pair by the following formula: Q(S t ,a t )←Q(S t ,a t )+α[r t+1 +γQ(S t+1 ,a t+1 )−Q(S t+1 ,a t+1 )], where S t Indicates the current state, a t Indicates the action taken in the current state, r t+1 is the immediate reward obtained when entering the next state after executing the action, S t+1 Indicates the next state to be transferred to after executing the action, a t+1 Indicates the action selected in the next state, Q(S t ,a t ) is the Q value of the current state-action pair, which is used to represent the state S t Take action a tThe expected cumulative reward that can be obtained, α is the learning rate, which is used to balance the weight of new information and historical information, and γ is the discount factor, which is used to measure the impact of future rewards. By adjusting these parameters, the SARSA algorithm can achieve an effective trade-off between optimizing short-term energy consumption and improving long-term performance.

[0030] In the present invention, the SARSA model learns the value of a state-action pair by considering the transition from one state-action pair to another, and adjusts the strategy according to the current state "S" and the selected action "A" and its reward "R" until entering a new state "S1" and selecting the next action "A1". This mechanism dynamically evaluates and adjusts the correction factor of the idle state selection, allowing the Menu controller to adapt to the changing environment, thereby achieving more accurate idle state selection.

[0031] Preferably, step (4) of the present invention specifically involves the collaboration between the operating system and the SBI firmware, wherein the operating system sends a request to specify the target low power state of the RISC-V processor, and after the SBI firmware receives the ecall call request, it parses the call parameters to determine the target low power state and related configuration parameters, and controls the RISC-V processor to quickly switch from the running state to the specified low power state.

[0032] The beneficial effects of the present invention are: 1. The present invention reduces the power consumption of the server platform system. By intelligently switching the processor state, the power consumption of the server platform when it is under low load or idle is significantly reduced, thereby effectively reducing the overall energy consumption.

[0033] 2. The present invention improves the stability of the server system. By dynamically adjusting the processor state, the system overheating caused by long-term high power consumption operation is avoided, and the reliability and stability of the system are enhanced.

[0034] 3. The present invention has strong adaptability and portability. Through the SBI interface, the operating system can request and manage the low power mode without directly accessing the hardware, ensuring that the RISC-V platform has good compatibility and consistency between different hardware implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic flow chart of the method of the present invention; Figure 2 It is a schematic diagram of the energy consumption management architecture of the operating system and UEFI involved in an embodiment of the present invention; Figure 3 It is a schematic diagram of the initialization process of the CPU idle state management module involved in an embodiment of the present invention; DETAILED DESCRIPTION

[0036] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0037] Embodiment 1: like Figure 1 As shown, this embodiment provides a method for switching the processor low power consumption state of a RISC-V server platform, and the steps are as follows: Step 1: Based on the UEFI firmware boot mode, configure the multi-level low power state information of the RISC-V processor in the ACPI DSDT table to achieve more sophisticated power management.

[0038] The DSDT table configuration will contain information about different low-power states, including minimum dwell time, worst-case wake-up latency, dwell counter frequency, dwell counter register, entry method, and state name. The _LPI object uses a resource descriptor to specify the entry method for the processor's low-power state. The RISC-V processor executes the wfi instruction when it enters the core WFI state. The entry methods for other low-power states are implemented using the SBI HSM extension. The HSM extension defines SUSPENDED, SUSPEND_PENDING, RESUMING_PENDING states, and the sbi_hart_suspend() interface to allow the processor to enter a platform-level low-power state.

[0039] Step 2: By obtaining the low power state parameters defined in the DSDT table, the Linux operating system can initialize the CPU idle state management module, thereby accurately identifying and controlling different idle states of the processor and dynamically managing the power consumption level of the system.

[0040] The CPU idle state management module of the Linux operating system includes core components, control strategy components, and driver components. Figure 2 As shown, the CPU idle state management module initialization process of this embodiment includes the following steps: Step 201, CPUIdle core component initialization; The core component is responsible for implementing the idle state management framework and providing the system with support for selecting and managing the processor idle state. The core component initialization process includes the initialization of key variables and functions required for idle state management. First, the system initializes the variables used to store registered device nodes. Next, the functions initialize entering the idle state, selecting the idle state, and recording the idle state one by one to provide the core functions of idle state management. Specifically, an Idle unified interface is provided for other modules related to Idle, including cpuidle_select, cpuidle_reflect, cpuIdle_enter, and cpuIdle_enter_s2idle functions.

[0041] Step 202, CPUIdle control strategy component initialization; The control strategy component first defines and initializes a scheduler structure, which contains the name of the scheduler, the score, and two key function pointers, which are used to select the idle state and reflect the state change. Then, the registration function is called to register the scheduler structure. Specifically, the cpuidle_register_governor() interface is called to register the governor. This process ensures that the scheduler is correctly loaded when the system starts and can manage the state according to the system requirements at runtime.

[0042] Step 203, initializing the CPUIdle driver of the specific CPU; The driver component registers a device driver during the initialization process and performs related initialization operations when the device starts. The driver component extracts the low-power state description information related to the RISC-V processor by parsing the DSDT table. The driver component classifies and manages different low-power states according to the characteristics, generates corresponding management entries, and maintains a low-power state table when the system is running. These table entries include key parameters such as exit delay, target dwell time, and power consumption, and are uniformly described through the "CPU idle state" structure to ensure that each CPU can enter different low-power modes according to specific hardware requirements. Specifically, cpuidle_driver calls sbi_cpuidle_init_cpu() to initialize and register the cpuidle driver for all CPUs, mainly to initialize the properties of Idle States and Idle functions. Then, the driver component sets the corresponding callback function so that the power consumption state of the CPU can be dynamically adjusted when needed. Specifically, the sbi_idle_init_cpuhp() function is called to set the callback function of the hot-swap CPUHP_AP_CPU_PM_STARTING state. The sbi_cpuidle_init_cpu() function finally calls the cpuidle_register() function to register the above driver.

[0043] Step 204, the scheduler enters the Idle cycle and enters the Idle State according to the Governor selection; When the idle thread is scheduled, the do_idle() function will be executed cyclically, the interface provided by the CPUIdle framework for scheduling will be executed, the cpuidle_select() function will be called to select the corresponding idle state by the governor, and then the call_cpuidle() function will be called to execute the entry function of this idle state. The sbi_cpuidle_enter_state() function in the sbi_cpuidle driver will call the sbi_hart_suspend() interface of the HSM extension to put the processor into a low power state. The cpuidle_reflect() function will be executed to notify the governor to exit from the current idle state.

[0044] Step 3: The CPU idle state management module selects a suitable low-power state for the RISC-V processor based on the control strategy of the reinforcement learning SARSA algorithm.

[0045] The control strategy adopts ladder and menu strategies to adapt to different system loads and power consumption requirements. The ladder strategy is a simple fixed-order strategy that selects idle states in ascending order, which is suitable for environments where the load does not change much. In contrast, the menu strategy is a more intelligent dynamic strategy that mainly selects the best C-State idle state based on the predicted time (expected stay time) and the system's delay tolerance, thereby achieving a more balanced optimization between performance and power consumption. Specifically, the Menu controller decides which idle state to enter based on the CPU load, the next timer event time, the number of active I / O threads, etc.

[0046] In the process of calculating the predicted idle time, the Menu governor preliminarily calculates a predicted time based on the time of the next timer event. However, since the time point of the next timer event may be interfered by other events, resulting in a deviation in the actual idle time, a set of correction factors need to be introduced to further adjust the predicted value. The correction factor is based on past experience data, especially the ratio of past prediction time to actual event time, and is calculated by a dynamic average algorithm. To improve the accuracy of the prediction, the Menu governor uses 12 different correction factors, corresponding to different time periods. The value of each correction factor is adjusted according to the fluctuation of historical data to adapt to different system behaviors, especially in different IO waiting scenarios. The Menu governor checks the consistency of the time intervals through the most recent 8 dwell times. If the standard deviation of these intervals is less than the threshold, the system will select the average of these times as a supplementary prediction value. Finally, the system takes the minimum of the above two prediction values ​​as the final idle time prediction, so as to more accurately adjust the CPU idle state to optimize energy efficiency.

[0047] The Menu controller uses the performance multiplier, the expected dwell time, and the system delay requirement to calculate the system delay tolerance. The system delay requirement is used as the first system tolerance, and the other system tolerance is calculated by the formula: expected dwell time / (1+10*number of IO waiting tasks on the current CPU). The minimum value of the first two system tolerances is taken as the system delay tolerance.

[0048] Finally, the appropriate idle state is selected based on the calculated predicted time (expected stay time) and the system delay tolerance. The calculated expected stay time is compared with the stay time of all idle states. The condition for selecting a specific idle state is that the corresponding stay time should be less than the expected predicted time. In addition, the exit delay of the state is compared with the delay tolerance of the system. The exit delay of the state must be less than the system delay tolerance. The best low-power state is the idle state that meets the two conditions and has the lowest power consumption.

[0049] The Menu controller is responsible for selecting the appropriate idle state. Although the deep idle state can significantly save power consumption, it requires additional entry and exit overhead and increases latency. Therefore, in order to achieve a better balance between power consumption and performance, the present invention uses the idea of ​​reinforcement learning to dynamically adjust and improve the idle state selection process. Reinforcement learning is a method in which an intelligent agent obtains rewards and updates its decision-making strategy by interacting with the environment. Initially, the intelligent agent understands the environment and takes actions according to the initial strategy. The environment then feeds back new state information and reward values, and the intelligent agent dynamically adjusts its strategy based on these feedbacks. In this process, the agent moves from the current state to the next state and improves its decision through reward and punishment feedback.

[0050] The SARSA algorithm is used to optimize the idle state selection strategy. SARSA is a policy-based reinforcement learning algorithm suitable for online decision-making problems. Based on the state-action pair, the algorithm updates the Q value through the following formula: Q(S t ,a t )←Q(S t ,a t )+α[r t+1 +γQ(S t+1 ,a t+1 )−Q(S t+1 ,a t+1 )], where S t Indicates the current state, a t Indicates the action taken in the current state, r t+1 is the immediate reward obtained when entering the next state after executing the action, S t+1 Indicates the next state to be transferred to after executing the action, a t+1 represents the action selected in the next state, Q(S t ,a t ) is the Q value of the current state-action pair, which is used to represent the state S t Take action a t The expected cumulative reward that can be obtained, α is the learning rate, which is used to balance the weight of new information and historical information, and γ is the discount factor, which is used to measure the impact of future rewards. By adjusting these parameters, the SARSA algorithm can achieve an effective trade-off between optimizing short-term energy consumption and improving long-term performance.

[0051] In the present invention, the SARSA model learns the value of a state-action pair by considering the transition from one state-action pair to another, and adjusts the strategy according to the current state "S" and the selected action "A" and its reward "R" until entering a new state "S1" and selecting the next action "A1". This mechanism dynamically evaluates and adjusts the correction factor of the idle state selection, allowing the Menu controller to adapt to the changing environment, thereby achieving more accurate idle state selection.

[0052] Step 4: The operating system calls the SBI firmware service to put the RISC-V processor into a specified low-power state.

[0053] This process involves the collaboration between the operating system and the SBI firmware. The operating system sends a request to specify the target low-power state of the RISC-V processor. After receiving the request, the SBI firmware parses the call parameters to determine the target low-power state and related configuration parameters, and controls the RISC-V processor to quickly switch from the running state to the specified low-power state.

[0054] Figure 3 This is a schematic diagram of the energy consumption management architecture of the operating system and UEFI used in this embodiment, see Figure 3 ,The modules related to the CPU idle state component in the operating system include an ACPI driver module and a CPU idle state management module, wherein the ACPI driver module can perform operations based on the ACPI system description table provided by UEFI, and the CPU idle state management module can be used to monitor the CPU load and automatically select different C-States according to the length of idle time.

[0055] In specific applications, the system can be initialized after it is powered on and enters the operating system. If the system runs UEFI firmware, it jumps to the ACPI driver module under the Linux kernel driver. The ACPI driver module parses the ACPI system description table of UEFI, obtains the resource description related to the processor low power state from the ACPI system description table, enumerates the Idle states in cpuidle_driver and initializes its entry function, and finally registers through cpuidle_register().

[0056] In the actual CPU operating environment, different CPUs have different requirements for the Idle state and entry / exit methods, and power consumption and exit delay have become a set of irreconcilable contradictions in the Idle scheduling process. How to ensure that power consumption is saved as much as possible while meeting performance requirements has become an important part of the CPUIdle subsystem. The control strategy component is responsible for providing strategies such as selecting the idle state. The Linux kernel provides two strategies: Menu and Ladder. The Menu controller has a correction factor array consisting of 12 indexes for the selection of the idle state. After the idle state exits, the actual idle time and the predicted idle time ratio are taken, and the correction coefficient of the last transition is calculated. The calculated correction factor will be updated in the corresponding index of the one-dimensional correction factor array. The existing logic does not consider the fact that the current transition occurs from which index to index or from idle state to idle state. It only considers the final result.

[0057] In this embodiment, the "state-action-reward-state-action" situation is tracked through a circular linked list containing 3 members. Each structure contains the state index, action index, and reward information obtained. The reward_matrix[number_of_idle_states x 12] is designed to index the state-action pair and store the reward factor according to the action taken during the state transition. After the idle state is exited, the index of reward_matrix [state][action] will be updated to the new reward factor calculated based on SARSA. For example, when the CPU is in state 0 and performs action 1 on instance T, it will enter state 1 on instance T+1 and get some reward. In this case, the index of reward_matrix[state-0][action-1] will update the reward by referencing the structure pointer.

[0058] The SARSA modeling steps under the CPUIdle subsystem include: Step 301, enable the Menu controller; Allocate a circular linked list consisting of 3 structure pointers, which contain information about the idle state index, action index, reward value, and next pointer, and assign the idle_sarsa_ptr of the idle data structure to the head of the linked list.

[0059] Idle_sarsa_ptr = ptr0; Allocate a reward matrix [number_of_idle_states x 12] that indexes state-action pairs and holds the respective state transition reward values. Initialize the matrix with the default unit reward value.

[0060] Step 302, select idle state; When predicting the next timer event, factor in the previous reward obtained during the respective state transitions - based on the environment, consider the next action indicator; Action_index = get_bucket_index(next_timer_event, number_of_iotask); Predicted_event_time=scheduler_next_timer_event x reward_matrix[state_index][action_index]; Idle_sarsa_ptr ->action_index = action_index; Idle_sarsa_ptr = Idle_sarsa_ptr ->next; Step 303, exit the idle state and update the reward; idle_sarsa_ptr->state_index = Get the current state index.

[0061] Idle_sarsa_ptr ->reward= state_action_reward; Update the reward matrix with the reward by referencing the linked list entry.

[0062] Idx_ptr_local = idle_sarsa_ptr->next; s t =idx_ptr_local->state_index; a t =idx_ptr_local->action_index; s t1 =idx_ptr_local->next->state_index; a t1 =idx_ptr_local->next->action_index; Reward_matrix [s t ][a t ] += learning_rate x (idx_ptr_local->next->reward) + discounting_factor x Reward_matrix [s t1 ][a t1 ] - Reward_matrix [s t ][a t ]); In this embodiment, the RISC-V processor can enter a deeper idle state when using the Menu governor optimized by the reinforcement learning SARSA algorithm than when using the conventional Menu governor, but the average idle time error for all states and all RISC-V processors is still very low, indicating better idle state selection and more power saving.

[0063] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for a terminal (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to execute the methods described in each embodiment of the present invention.

[0064] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A processor low power consumption state switching method for a RISC-V server platform, characterized in that: Here are the steps: (1) Configure multi-level low-power state information of the RISC-V processor; (2) Initialize the CPU idle state management module using multi-level low power state information; (3) The CPU idle state management module selects the optimal low-power state for the RISC-V processor based on the control strategy of the reinforcement learning SARSA algorithm; (4) The RISC-V processor enters a specified low-power state.

2. The processor low power consumption state switching method of the RISC-V server platform according to claim 1, characterized in that: In step (1), the multi-level low power consumption state information is: A low-power state object is defined in the DSDT table of the ACPI firmware, which provides complete information of the low-power state, including minimum dwell time, worst-case wakeup latency, dwell counter frequency, dwell counter register, entry method, and state name.

3. The processor low power consumption state switching method of the RISC-V server platform according to claim 2, characterized in that: In step (2), specifically: the CPU idle state management module includes a core component, a control strategy component and a driver component, and the initialization process includes a core component initialization process, a control strategy component initialization process and a driver component initialization process.

4. The processor low power consumption state switching method of the RISC-V server platform as claimed in claim 3, characterized in that: The core component initialization process is to initialize the key variables and functions required for idle state management. First, the key variables are initialized, that is, the variables that store registered device nodes. Then, the functions are initialized one by one for entering the idle state, selecting the idle state, and recording the idle state.

5. The processor low power consumption state switching method of the RISC-V server platform according to claim 4, characterized in that: The initialization process of the control strategy component is as follows: first, define and initialize the scheduler structure, which includes the scheduler's name, score, and two key function pointers, which are used to select the idle state and reflect the state change respectively. Then, call the registration function to register the scheduler structure.

6. The processor low power consumption state switching method of the RISC-V server platform according to claim 5, characterized in that: The driver component initialization process is to register the device driver and perform initialization operations when the device starts.

7. The processor low power consumption state switching method of the RISC-V server platform according to claim 6, characterized in that: In step (3), specifically: The control strategies include trapezoidal strategy and vegetable strategy; The Menu controller gives a prediction value based on the time of the next timer event. The Menu controller checks the consistency of the time intervals through the latest 8 dwell times. If the standard deviation of these time intervals is less than the threshold, the average of the 8 dwell times is selected as the supplementary prediction value, and the minimum of the above two prediction values ​​is taken as the final prediction time. The Menu controller uses the performance multiplier, the expected residence time, and the system delay requirement to calculate the system delay tolerance. The system delay requirement is used as the first system tolerance. The other system tolerance is calculated using the formula: expected residence time / (1+10*number of IO waiting tasks on the current CPU). The minimum value of the two system tolerances is taken as the system delay tolerance. An idle state is selected based on the predicted time and system delay tolerance, and the predicted time is compared with the residence time of all Idle states. The condition for selecting a specific Idle state is that the corresponding residence time is less than the predicted time. In addition, the exit delay of the state is compared with the system delay tolerance. The exit delay of the state must be less than the system delay tolerance. The idle state that meets these two conditions and has the lowest power consumption is selected as the optimal low-power state.

8. The processor low power consumption state switching method of the RISC-V server platform according to claim 7, characterized in that: In step (3), the SARSA algorithm is used to optimize the idle state selection strategy. Based on the state-action pair, the algorithm updates the Q value through the following formula: Q(S t ,a t )←Q(S t ,a t )+α[r t+1 +γQ(S t+1 ,a t+1 )−Q(S t+1 ,a t+1 )], where S t Indicates the current state, a t Indicates the action taken in the current state, r t+1 is the immediate reward obtained when entering the next state after executing the action, S t+1 Indicates the next state to be transferred to after executing the action, a t+1 represents the action selected in the next state, Q(S t ,a t ) is the Q value of the current state-action pair, which is used to represent the state S t Take action a t The expected cumulative reward that can be obtained, α is the learning rate, which is used to balance the weight of new information and historical information, and γ is the discount factor, which is used to measure the impact of future rewards.

9. The processor low power consumption state switching method of the RISC-V server platform according to claim 8, characterized in that: Step (4) specifically involves the collaboration between the operating system and the SBI firmware. The operating system sends a request to specify the target low-power state of the RISC-V processor. After receiving the ecall call request, the SBI firmware parses the call parameters to determine the target low-power state and related configuration parameters, and controls the RISC-V processor to quickly switch from the running state to the specified low-power state.

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