Semiconductor device

Abstract

The purpose of the present invention is to suppress insulation defects in a lead frame type transfer molding power module. A semiconductor device (101) is provided with: at least one control chip (1a, 1b) which is provided at a position overlapping a first die pad (3) in plan view, and which is electrically connected to the first die pad (3); a plurality of power chips (2a-2f) that are mounted on each of the plurality of second die pads (4c-4f); a plurality of circuit patterns (7) and a plurality of lead pads (12) formed on the upper surface of the insulating substrate (11) provided on the upper surface of the first die pad (3); a plurality of first control wires (9) that electrically connect the plurality of wire pads (12) and the at least one control chip (1a, 1b); and a plurality of second control wires (14) that electrically connect the at least one control chip (1a, 1b) and the plurality of power chips (2a-2f).

Description

Technical Field

[0001] The present invention relates to a transfer molded power module. Background Art

[0002] The transfer molded power module is a structure in which a power chip and a control chip for controlling the power chip are built-in and the power chip and the control chip are encapsulated by an insulating molding resin. The transfer molded power module has a lead frame type in which a die pad and a terminal of the control chip are formed by a lead frame formed from a copper plate, and circuits are connected by wires (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-141237

[0004] In a lead frame type transfer molded power module, there is a problem that a wire connecting a control chip and a power chip is deformed during injection of a molding resin and comes into contact with the lead frame, causing insulation failure. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to suppress insulation failure in a lead frame type transfer molded power module.

[0006] The semiconductor device of the present invention comprises: a first tube core pad; at least one control chip, which is arranged on the upper surface side of the first tube core pad and overlaps with the first tube core pad when viewed from above, and is electrically connected to the first tube core pad; a plurality of control side terminals, which are used to supply signals to at least one control chip; a plurality of second tube core pads; a plurality of power chips, which are respectively mounted on the plurality of second tube core pads and controlled by at least one control chip; a plurality of power side terminals, which are respectively connected to the plurality of second tube core pads; an insulating substrate, which is arranged on the upper surface of the first tube core pad; a plurality of conductive circuit patterns, which are formed on the insulating substrate the upper surface of the insulating substrate being electrically connected to the control side terminal; a plurality of wire pads formed on the upper surface of the insulating substrate being electrically connected to the plurality of circuit patterns respectively; a plurality of first control wires electrically connecting the plurality of wire pads to at least one control chip; a plurality of second control wires electrically connecting at least one control chip to the first connection area of ​​a plurality of power chips; and a molding resin encapsulating at least one control chip, a plurality of power chips, a plurality of first control wires and a plurality of second control wires, the first tube core pad, the plurality of second tube core pads, the plurality of control side terminals and the plurality of power side terminals being formed by a lead frame.

[0007] Effects of the Invention

[0008] In the semiconductor device according to the present invention, control signals are transmitted from a plurality of control-side terminals to at least one control chip via a plurality of circuit patterns, a plurality of wire bonding pads, and a plurality of first control wires. According to the above-described structure, by disposing the plurality of wire bonding pads in proximity to at least one control chip, the plurality of first control wires can be shortened. Therefore, it is possible to suppress deformation of the plurality of first control wires and accompanying insulation defects during injection of the molding resin. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view of the semiconductor device according to Embodiment 1.

[0010] Figure 2 is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0011] Figure 3 is a top view of the semiconductor device according to Embodiment 2.

[0012] Figure 4 is a cross-sectional view of the semiconductor device according to Embodiment 2.

[0013] Figure 5 is a top view of the semiconductor device according to Embodiment 3. DETAILED DESCRIPTION

[0014] <A. Embodiment 1>

[0015] <A-1. Structure>

[0016] Figure 1 is a top view of the semiconductor device 101 according to Embodiment 1. Figure 2 is a cross-sectional view of the semiconductor device 101. The semiconductor device 101 is a transfer molding type power module.

[0017] As Figure 1 and Figure 2As shown, the semiconductor device 101 of the first embodiment includes a plurality of control chips 1a, 1b, a plurality of power chips 2a, 2b, 2c, 2d, 2e, 2f, a first die pad 3, a plurality of second die pads 4c, 4d, 4e, 4f, a plurality of control-side terminals 5, a plurality of power-side terminals 6, an insulating substrate 11, a plurality of circuit patterns 7, a plurality of wire pads 12, an insulating layer 13, and a molding resin 15. The first die pad 3, the plurality of second die pads 4c, 4d, 4e, 4f, the plurality of control-side terminals 5, and the plurality of power-side terminals 6 are formed by a lead frame. In addition, in this specification, when the plurality of control chips 1a, 1b are not identified individually but are referred to as a whole, they may be referred to as control chips 1, and the plurality of power chips 2a, 2b, 2c, 2d, 2e, 2f or the plurality of second die pads 4c, 4d, 4e, 4f may also be referred to as power chips 2 or second die pads 4 in the same manner.

[0018] The plurality of control-side terminals 5 and the plurality of power-side terminals 6 are terminals for electrically connecting the semiconductor device 101 to an external device provided outside the semiconductor device 101. The plurality of control-side terminals 5 are terminals for controlling the operation of the power chip 2 or notifying an external device of an abnormality of the semiconductor device 101. For example, the plurality of control-side terminals 5 are connected to a microcontroller. The plurality of power-side terminals 6 are paths for the main current flowing through the semiconductor device 101 and are terminals for allowing the main current to flow to an external device.

[0019] The semiconductor device 101 of embodiment 1 has a built-in three-phase AC output inverter circuit. Here, the three phases refer to the U phase, the V phase and the W phase. The control chip 1b is a LVIC (Low Voltage Integrated Circuit) that controls the drive of the power chip 2d of the U phase, the power chip 2e of the V phase and the power chip 2f of the W phase. The three power chips 2a, 2b, and 2c constitute the P side. The control chip 1a is an HVIC (High Voltage Integrated Circuit) that controls the drive of the power chips 2a, 2b, and 2c. In addition, the control chip 1a and the control chip 1b can also be integrated into one control chip. That is, the semiconductor device 101 only needs to have at least one control chip.

[0020] The power chips 2a, 2b, and 2c are mounted on the second die pad 4c. The terminal of the power side terminal 6 connected to the second die pad 4c is the P terminal. The power chip 2d is mounted on the second die pad 4d. The terminal of the power side terminal 6 connected to the second die pad 4d is the U terminal. The power chip 2e is mounted on the second die pad 4e. The terminal of the power side terminal 6 connected to the second die pad 4e is the V terminal. The power chip 2f is mounted on the second die pad 4f. The terminal of the power side terminal 6 connected to the second die pad 4f is the W terminal. If the power side terminal 6 is integrated with the second die pad 4, the material can be minimized and the manufacturing process can be simplified. However, the two may not be integrated. For example, the power side terminal 6 and the second die pad 4 may also be composed of different components and connected by solder or US bonding.

[0021] The control chip 1 is mounted on the first die pad 3. The first die pad 3 may be integrated with a part of the control-side terminals 5. By integrating the first die pad 3 with a part of the control-side terminals 5, positional deviation is suppressed.

[0022] An insulating substrate 11 is provided on the upper surface of the first tube core pad 3. The insulating substrate 11 is, for example, a PCB substrate. The insulating substrate 11 is not required to have heat dissipation properties, so an inexpensive substrate can also be used. A circuit pattern 7 is provided on the upper surface of the insulating substrate 11 through a conductive material. In addition, a plurality of through holes 8 penetrating the insulating substrate 11 in the thickness direction are provided on the insulating substrate 11. A conductive material is arranged in the through hole 8. In addition, a wire pad 12 is provided on the upper surface of the insulating substrate 11.

[0023] A portion of the circuit pattern 7 is joined to the control side terminal 5 via the through hole 8 and is electrically connected to the control side terminal 5. The circuit pattern 7 and the control side terminal 5 at the through hole 8 are joined using, for example, solder. A portion of the through hole 8 is not electrically connected to the circuit pattern 7. The through hole 8 that is not electrically connected to the circuit pattern 7 is joined to the first die pad 3 by solder or the like, thereby achieving the function of fixing the insulating substrate 11 to the first die pad 3.

[0024] A portion of the circuit pattern 7 is electrically connected to the wire pad 12. One end of the first control wire 9 is connected to the wire pad 12. The other end of the first control wire 9 is connected to the control chip 1. With these structures, in the semiconductor device 101, a signal for controlling the power chip 2 is transmitted from the control-side terminal 5 to the control chip 1 via the through hole 8, the circuit pattern 7, the wire pad 12, and the first control wire 9.

[0025] The control chip 1 transmits a control signal to the power chip 2 via the second control wire 14 to control the operation of the power chip 2 as a three-phase AC output inverter. The second control wire 14 connects the control chip 1 to the power chip 2. The area in the power chip 2 connected to the second control wire 14 is called the first connection area 21. When the power chip 2 includes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the first connection area 21 is a gate pad and the second control wire 14 is a gate wire. In addition, the power chip 2 is not limited to a MOSFET, but may also be an SBD (Schottky Barrier Diode), an IGBT (Insulated Gate Bipolar Transistor) or a PN diode. The control chip 1 is connected to the first die pad 3 via a through hole 8 and solder provided in the insulating substrate 11.

[0026] The power chip 2 is connected to the power side terminal 6 through the main conductor 10. The area of ​​the power chip 2 connected to the main conductor 10 is called the second connection area 22. The main conductor 10 is different from the first control conductor 9 and the second control conductor 14. A large current flows through the main conductor 10, and therefore, in order to suppress heat generation, the main conductor 10 is configured to have a larger diameter than the first control conductor 9 and the second control conductor 14. The plurality of conductor pads 12 are arranged close to the control chip 1, so the longest first control conductor 9 is shorter than the longest second control conductor 14.

[0027] The control chip 1, the power chip 2, the first die pad 3, the second die pad 4, the insulating substrate 11, the plurality of circuit patterns 7, the plurality of wire pads 12, the first control wire 9, the main wire 10, the second control wire 14, and the insulating layer 13 are encapsulated by the molding resin 15. Thus, the internal circuits of the control chip 1 and the power chip 2 are fixed, and insulation from the outside of the semiconductor device 101 is ensured. However, the control side terminal 5 and the power side terminal 6 protrude in a manner exposed from the molding resin 15 so as to enable electrical connection to the outside. The second die pad 4 is connected to the insulating layer 13. The insulating layer 13 is composed of a member having a higher thermal conductivity than the molding resin 15, thereby effectively dissipating the heat generated by the power chip 2.

[0028] Although in Figure 1 as well as Figure 2 Although not shown, the semiconductor device 101 may also have a built-in BSD (Boot Strap Diode). In this case, an opening is provided in the insulating substrate 11 at a position overlapping with the position of the first die pad 3 on which the BSD is mounted when viewed from above, and the BSD and the control-side terminal 5 are connected through the opening by solder or the like.

[0029] <A-2. Effect>

[0030] The semiconductor device 101 according to Embodiment 1 includes a first die pad 3, a plurality of control chips 1a, 1b, a plurality of control-side terminals 5, a plurality of second die pads 4c-4f, a plurality of power chips 2a-2f, a plurality of power-side terminals 6, an insulating substrate 11, a plurality of conductive circuit patterns 7, a plurality of wire pads 12, a plurality of first control wires 9, a plurality of second control wires 14, and a molding resin 15. The plurality of control chips 1a, 1b are disposed on the upper surface side of the first die pad 3 and are located at positions overlapping the first die pad 3 in a top view, and are electrically connected to the first die pad 3. The plurality of control-side terminals 5 are terminals for supplying signals to the plurality of control chips 1a, 1b. The plurality of power chips 2a-2f are mounted on respective ones of the plurality of second die pads 4c-4f and are controlled by the plurality of control chips 1a, 1b. The plurality of power-side terminals 6 are each connected to the plurality of second die pads 4c-4f. The insulating substrate 11 is disposed on the upper surface of the first die pad 3. The circuit patterns 7 are formed on the upper surface of the insulating substrate 11 and are electrically connected to the control-side terminals 5. The plurality of wire pads 12 are formed on the upper surface of the insulating substrate 11 and are each electrically connected to the plurality of circuit patterns 7. The plurality of first control wires 9 electrically connect the plurality of wire pads 12 to the plurality of control chips 1a, 1b. The plurality of second control wires 14 electrically connect the plurality of control chips 1a, 1b to the first connection regions 21 of the plurality of power chips 2. The molding resin 15 encapsulates the plurality of control chips 1a, 1b, the plurality of power chips 2, the plurality of first control wires 9, and the plurality of second control wires 14. The first die pad 3, the plurality of second die pads 4, the plurality of control-side terminals 5, and the plurality of power-side terminals 6 are formed of a lead frame.

[0031] With the above structure, in the semiconductor device 101, control signals are transmitted from the control-side terminals 5 to the control chips 1a, 1b via the circuit patterns 7, the wire pads 12, and the first control wires 9. By disposing the wire pads 12 near the control chips 1a, 1b, the first control wires 9 can be shortened. It is also possible to make the longest first control wire 9 among the plurality of first control wires 9 shorter than the longest second control wire 14 among the plurality of second control wires 14. Therefore, deformation of the first control wires 9 can be suppressed during encapsulation by the molding resin 15, and insulation failure associated therewith can be suppressed.

[0032] As Figure 2As shown, the second control wire 14 extends from the control chip 1 in the first direction D1 and reaches the power chip 2. Moreover, the end portion 11E of the insulating substrate 11 in the first direction D1 protrudes toward the first connection region 21 side of the plurality of power chips 2 compared with the end portion 3E of the first die pad 3 in the first direction D1. With the above structure, even if the second control wire 14 is deformed during the molding process, it contacts the end portion 11E of the insulating substrate 11 as shown by the dashed line in Figure 2 . Therefore, contact between the second control wire 14 and the end portion 3E of the first die pad 3 and the accompanying insulation failure are suppressed.

[0033] In the semiconductor device 101, a plurality of control chips 1a, 1b are mounted on the upper surface of the insulating substrate 11 and are electrically connected to the first die pad 3 via the through holes 8 provided in the insulating substrate 11. As described above, since the control chips 1a, 1b are mounted on the insulating substrate 11 instead of the first die pad 3, there is no need to change the lead frame for a small number of product types, and cost increase can be suppressed by component commonalization. Further, a plurality of elements with different reference voltages such as a floating electrode or an insulated drive, which are difficult to form in the case of a lead frame, can be mounted on the insulating substrate 11.

[0034] In addition, by finely forming the circuit pattern 7 on the insulating substrate 11, the area of the control chips 1a, 1b can be reduced. As a result, the area of the power chip 2 and its die area can be enlarged.

[0035] Furthermore, an increase in current capacity, that is, an increase in power density can be achieved without changing the external shape of the general package.

[0036] <A-3. Modified Example>

[0037] The insulating substrate 11 may also be made of a high heat-resistant material having a heat resistance greater than or equal to the curing temperature of the molding resin 15. Thereby, a power semiconductor device can be formed from a general package or a general pin arrangement. In addition, cost reduction can be achieved by material and process commonalization, and total cost reduction can also be achieved by substrate commonalization in an application set.

[0038] A MOSFET made of a wide bandgap material such as SiC, GaN, or Ga2O3 may also be mounted on the power chip 2. Since this MOSFET is a high-voltage single-polarity device, it has low on-off loss and can perform high-carrier operation. However, by using a gate driver with high narrow-pulse reactivity (such as a micro-transformer method, etc.), the pulse response can be improved and the efficiency of waveform generation can be increased.

[0039] In addition, in the case of being composed of packages of the same size, by using a control substrate, the wiring area can be reduced, and thus the output ability of the IC driver can be improved. That is, the high-speed operation of the power semiconductor chip can be realized. In addition, in the case of a gate driver based on a multi-chip structure such as a micro-transformer, a floating electrode or a power supply is required, but by using the insulating substrate 11, the degree of freedom in the mounting position is provided, and thus the module area can be reduced.

[0040] <B. Embodiment 2>

[0041] <B-1. Structure>

[0042] Figure 3 It is a top view of the semiconductor device 102 according to Embodiment 2. Figure 4 It is a cross-sectional view of the semiconductor device 102.

[0043] The difference between the semiconductor device 102 and the semiconductor device 101 according to Embodiment 1 is that the control chips 1a and 1b are conductively joined to the first die pad 3 by a conductive joining material such as solder. The insulating substrate 11 has an opening 11A, and at the opening 11A, the control chips 1a and 1b are joined to the upper surface of the first die pad 3. In other words, the control chips 1a and 1b are disposed at positions that overlap the opening 11A of the insulating substrate 11 in a top view.

[0044] <B-2. Effects>

[0045] In the semiconductor device 102 according to Embodiment 2, the control chips 1a and 1b are mounted on the upper surface of the first die pad 3 within the opening 11A of the insulating substrate 11. The first die pad 3 made of a lead frame such as copper has higher heat dissipation than the insulating substrate 11, so the semiconductor device 102 has a structure with higher heat dissipation than the semiconductor device 101 according to Embodiment 1. Therefore, the temperature rise of the semiconductor device 102 during high-voltage or high-carrier operation is also suppressed.

[0046] <C. Embodiment 3>

[0047] <C-1. Structure>

[0048] Figure 5 It is a top view of the semiconductor device 103 according to Embodiment 3.

[0049] The semiconductor device 103 is different from the semiconductor device 102 according to the second embodiment in that the plurality of power chips 2 and the plurality of second die pads 4 are each arranged below the insulating substrate 11 in such a manner that a portion thereof overlaps with the insulating substrate 11 when viewed from above. In addition, the semiconductor device 103 may be configured such that a portion of each of the plurality of power chips 2 and the plurality of second die pads 4 on which the plurality of power chips 2 are mounted is arranged below the insulating substrate 11, relative to the semiconductor device 101 according to the first embodiment.

[0050] On the other hand, the first connection regions 21 connected to the second control wires 14 and the second connection regions 22 connected to the main wires 10 in the plurality of power chips 2 do not overlap with the insulating substrate 11 in a plan view.

[0051] In the semiconductor device 103 according to the third embodiment, the plurality of power chips 2 and the plurality of second die pads 4c-4f are arranged below the insulating substrate 11 in such a manner that a portion of them overlaps with the insulating substrate 11 when viewed from above. Furthermore, the connection regions of the plurality of power chips 2 do not overlap with the insulating substrate 11 when viewed from above. With the above structure, the area of ​​the power chip 2 can be enlarged in the case of a general-purpose package for the semiconductor device 103, and the power density can be improved.

[0052] As mentioned above, although the preferred embodiments and the like have been described in detail, the present invention is not limited to the above-mentioned embodiments and the like, and various modifications and substitutions can be made to the above-mentioned embodiments and the like without departing from the scope described in the claims.

[0053] Hereinafter, each aspect of the present invention will be summarized and described as supplementary notes.

[0054] (Note 1)

[0055] A semiconductor device comprising:

[0056] The first die pad;

[0057] at least one control chip, which is disposed on the upper surface side of the first die pad and is located at a position overlapping with the first die pad when viewed from above, and is electrically connected to the first die pad;

[0058] A plurality of control-side terminals, which are used to supply signals to the at least one control chip;

[0059] a plurality of second die pads;

[0060] a plurality of power chips mounted on each of the plurality of second die pads and controlled by the at least one control chip;

[0061] a plurality of power-side terminals connected to each of the plurality of second die pads;

[0062] An insulating substrate, which is disposed on the upper surface of the first tube core pad;

[0063] a plurality of conductive circuit patterns formed on the upper surface of the insulating substrate and electrically connected to the control-side terminal;

[0064] a plurality of wire pads formed on the upper surface of the insulating substrate and electrically connected to each of the plurality of circuit patterns;

[0065] a plurality of first control wires electrically connecting the plurality of wire pads to the at least one control chip;

[0066] a plurality of second control wires electrically connecting the at least one control chip to the first connection regions of the plurality of power chips; and

[0067] a molding resin that encapsulates the at least one control chip, the plurality of power chips, the plurality of first control wires, and the plurality of second control wires,

[0068] The first die pad, the plurality of second die pads, the plurality of control-side terminals, and the plurality of power-side terminals are formed by a lead frame.

[0069] (Note 2)

[0070] The semiconductor device according to Supplementary Note 1, wherein:

[0071] A longest first control conductive wire among the plurality of first control conductive wires is shorter than a longest second control conductive wire among the plurality of second control conductive wires.

[0072] (Note 3)

[0073] The semiconductor device according to Supplement 1 or Supplement 2, wherein:

[0074] The second control wire extends from the at least one control chip along a first direction to reach the power chip.

[0075] An end portion of the insulating substrate in the first direction protrudes toward the first connection region side of the plurality of power chips more than an end portion of the first die pad in the first direction.

[0076] (Note 4)

[0077] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0078] The at least one control chip is mounted on the upper surface of the insulating substrate and is electrically connected to the first die pad via a through hole provided in the insulating substrate.

[0079] (Note 5)

[0080] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0081] The at least one control chip is mounted on the upper surface of the first die pad in an opening provided in the insulating substrate.

[0082] (Note 6)

[0083] The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0084] The plurality of power chips and the second die pad are arranged below the insulating substrate in a manner such that a portion of the power chips and the second die pad overlap the insulating substrate when viewed from above.

[0085] The first connection regions of the plurality of power chips do not overlap with the insulating substrate in a plan view.

[0086] (Note 7)

[0087] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0088] The insulating substrate is composed of a material having heat resistance greater than or equal to a curing processing temperature of the molding resin.

[0089] (Note 8)

[0090] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0091] The power chip includes a MOSFET made of wide bandgap material.

[0092] Description of the label

[0093] 1, 1a, 1b control chip, 2, 2a, 2b, 2c, 2d, 2e, 2f power chip, 3 1st tube core pad, 3E end, 4, 4c, 4d, 4e, 4f second tube core pad, 5 control side terminal, 6 power side terminal, 7 circuit pattern, 8 through hole, 9 1st control wire, 10 main wire, 11 insulating substrate, 11A opening, 11E end, 12 wire pad, 13 insulating layer, 14 second control wire, 15 molding resin, 21 1st connection area, 22 2nd connection area, 101, 102, 103 semiconductor device.

Claims

1. A semiconductor device comprising: The first die pad; at least one control chip, which is disposed on the upper surface side of the first die pad and is located at a position overlapping with the first die pad when viewed from above, and is electrically connected to the first die pad; A plurality of control-side terminals, which are used to supply signals to the at least one control chip; a plurality of second die pads; a plurality of power chips mounted on each of the plurality of second die pads and controlled by the at least one control chip; a plurality of power-side terminals connected to each of the plurality of second die pads; An insulating substrate, which is disposed on the upper surface of the first tube core pad; a plurality of conductive circuit patterns formed on the upper surface of the insulating substrate and electrically connected to the control-side terminal; a plurality of wire pads formed on the upper surface of the insulating substrate and electrically connected to each of the plurality of circuit patterns; a plurality of first control wires electrically connecting the plurality of wire pads to the at least one control chip; a plurality of second control wires electrically connecting the at least one control chip to the first connection regions of the plurality of power chips; as well as a molding resin that encapsulates the at least one control chip, the plurality of power chips, the plurality of first control wires, and the plurality of second control wires, The first die pad, the plurality of second die pads, the plurality of control-side terminals, and the plurality of power-side terminals are formed by a lead frame.

2. The semiconductor device according to claim 1, wherein A longest first control conductive wire among the plurality of first control conductive wires is shorter than a longest second control conductive wire among the plurality of second control conductive wires.

3. The semiconductor device according to claim 1 or 2, wherein: The second control wire extends from the at least one control chip along a first direction to reach the power chip. An end portion of the insulating substrate in the first direction protrudes toward the first connection region side of the plurality of power chips more than an end portion of the first die pad in the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The at least one control chip is mounted on the upper surface of the insulating substrate and is electrically connected to the first die pad via a through hole provided in the insulating substrate.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The at least one control chip is mounted on the upper surface of the first die pad in an opening provided in the insulating substrate.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The plurality of power chips and the second die pad are arranged below the insulating substrate in a manner such that a portion of the power chips and the second die pad overlap the insulating substrate when viewed from above. The first connection regions of the plurality of power chips do not overlap with the insulating substrate in a plan view.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The insulating substrate is composed of a material having heat resistance greater than or equal to a curing processing temperature of the molding resin.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The power chip includes a MOSFET made of wide bandgap material.

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