Gallium oxide-based MOSFET device and preparation method thereof

Abstract

The invention discloses a gallium oxide-based MOSFET device and a preparation method thereof, and relates to the field of semiconductor devices. The device has the characteristics of high voltage resistance and low electric leakage, and comprises a conductive region and an edge terminal region connected with the conductive region, the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current barrier layer and a highly-doped gallium oxide N + region which are sequentially stacked from bottom to top, and a groove which is positioned on the surface of the highly-doped gallium oxide N + region and of which the bottom is propped against the first gallium oxide epitaxial layer; the conductive region further comprises a first p-type semiconductor buried layer located at the bottom and on the side wall of the groove, a gate dielectric layer located on the surface of the first p-type semiconductor buried layer, the side wall of the groove and the surface of the highly-doped gallium oxide N + region, and a gate metal layer located on the surface of the gate dielectric layer. The first interlayer dielectric layer covers the surface and the side face of the gate metal layer and the side face of the gate dielectric layer, and the source metal layer is located on the surface of the first interlayer dielectric layer and the surface of the highly-doped gallium oxide N + region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a gallium oxide-based MOSFET device and a preparation method thereof. Background Art

[0002] The ultra-high critical breakdown electric field of gallium oxide (Ga2O3) material of about 8MV / cm can greatly improve the withstand voltage capability of power devices; the ultra-wide bandgap of about 4.8eV can improve the reliability of power devices in extreme environments such as high temperature and strong radiation; the substrate material grown by the melt method can reduce the material cost of power devices. Therefore, gallium oxide materials can bring breakthroughs in the development of power devices. However, due to the lack of p-type doping in Ga2O3 materials, gallium oxide-based power metal-oxide-semiconductor field effect transistors (MOSFETs) cannot use the structure of conventional silicon (Si) / SiC-based MOSFETs to achieve enhanced characteristics. Therefore, the current enhanced gallium oxide-based power MOSFET devices have bottleneck problems of low withstand voltage and high leakage, which greatly limits the development of gallium oxide-based power devices. Therefore, it is of great practical significance to develop high withstand voltage and low leakage gallium oxide-based MOSFET devices to achieve high withstand voltage and low leakage. Summary of the invention

[0003] Based on the above-mentioned deficiencies of the prior art, the object of the present invention is to provide a gallium oxide-based MOSFET device and a preparation method thereof, aiming to solve the problems of low withstand voltage and high leakage of the existing gallium oxide-based MOSFET devices.

[0004] The technical solution of the present invention is as follows:

[0005] In a first aspect of the present invention, a gallium oxide-based MOSFET device is provided, wherein the gallium oxide-based MOSFET device comprises a conductive region and an edge terminal region connected to the conductive region; the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current blocking layer and a highly doped gallium oxide N + The highly doped gallium oxide N + The conductive region further comprises: a groove on the surface of the conductive region that is recessed toward the first gallium oxide substrate, and the bottom of the groove reaches the first gallium oxide epitaxial layer; and the conductive region further comprises:

[0006] A first p-type semiconductor buried layer is located on the bottom and sidewalls of the groove;

[0007] The gate dielectric layer is located on the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + on the surface of the area;

[0008] A gate metal layer, located on the surface of the gate dielectric layer;

[0009] A first interlayer dielectric layer covers the surface and side surfaces of the gate metal layer and the side surfaces of the gate dielectric layer;

[0010] The source metal layer is located between the first interlayer dielectric layer and the highly doped gallium oxide N + on the surface of the area.

[0011] Optionally, the edge termination region includes a second drain metal layer, a second gallium oxide substrate, and a second gallium oxide epitaxial layer stacked in sequence;

[0012] The second drain metal layer is connected to the first drain metal layer, the second gallium oxide substrate is connected to the first gallium oxide substrate, the second gallium oxide epitaxial layer is connected to the first gallium oxide epitaxial layer, and the thickness of the second gallium oxide epitaxial layer is less than the thickness of the first gallium oxide epitaxial layer, and the edge termination region further includes:

[0013] a second p-type semiconductor buried layer, located on the surface of the second gallium oxide epitaxial layer and on the sidewall of the first gallium oxide epitaxial layer;

[0014] The second interlayer dielectric layer is located on the surface of the second gallium oxide epitaxial layer and the surface of the second p-type semiconductor buried layer, and the second interlayer dielectric layer extends upward to the source metal layer and covers a portion of the highly doped gallium oxide N + Area surface.

[0015] Optionally, the thickness of the first gallium oxide substrate is 50-650 μm, and the first gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 The thickness of the second gallium oxide substrate is 50 to 650 μm, and the second gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 .

[0016] Optionally, the thickness of the first gallium oxide epitaxial layer is 2 to 20 μm;

[0017] The first gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 ;

[0018] The second gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

[0019] Optionally, the gallium oxide current blocking layer has a thickness of 500 nm to 3 μm, and the gallium oxide current blocking layer comprises nitrogen-doped gallium oxide, and the nitrogen doping concentration is 10 17 ~10 19 cm -3 ;

[0020] The highly doped gallium oxide N + The thickness of the region is 100 to 300 nm, and the doping concentration is 10 18 ~10 20 cm -3 .

[0021] Optionally, the thickness of the first p-type semiconductor buried layer is 100-600 nm, and the hole concentration of the first p-type semiconductor buried layer is 10 16 ~10 19 cm -3 , the first p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide;

[0022] The height of the portion of the first p-type semiconductor buried layer located on the sidewall of the groove is not higher than the lower surface of the gallium oxide current blocking layer;

[0023] The thickness of the second p-type semiconductor buried layer is 100-600 nm, and the hole concentration of the second p-type semiconductor buried layer is 10 16 ~10 19 cm -3 The second p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide.

[0024] Optionally, the gate dielectric layer has a thickness of 10-100 nm, and the gate dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

[0025] Optionally, the gate metal layer has a thickness of 50 to 300 nm; the gate metal layer includes at least one of chromium, nickel, gold, polysilicon and aluminum;

[0026] Optionally, the thickness of the first interlayer dielectric layer is 500 nm to 1.5 μm, and the thickness of the second interlayer dielectric layer is 500 nm to 1.5 μm;

[0027] The gallium oxide-based MOSFET device further includes a passivation layer, which is located on a portion of the surface of the source metal layer and on a surface of the second interlayer dielectric layer.

[0028] A second aspect of the present invention provides a method for preparing a gallium oxide-based MOSFET device, comprising the following steps:

[0029] A first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current blocking layer and a highly doped gallium oxide N are sequentially formed on the first drain metal layer. + district;

[0030] In the highly doped gallium oxide N + A groove is formed on the surface of the region and is recessed toward the first gallium oxide substrate, and the bottom of the groove reaches the first gallium oxide epitaxial layer;

[0031] forming a first p-type semiconductor buried layer on the bottom and sidewalls of the groove;

[0032] On the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + forming a gate dielectric layer on the surface of the region;

[0033] forming a gate metal layer on the surface of the gate dielectric layer;

[0034] forming a first interlayer dielectric layer on the surface and side surfaces of the gate metal layer and the side surfaces of the gate dielectric layer;

[0035] The first interlayer dielectric layer and the highly doped gallium oxide N + forming a drain metal layer on the surface of the region to obtain a conductive region;

[0036] The conductive region is connected to the edge terminal region to obtain the gallium oxide-based MOSFET device.

[0037] Beneficial effects: The present invention reduces the leakage current of the device by setting a gallium oxide current blocking layer, and introduces a p-type semiconductor buried layer under the gate as an electric field shielding layer to suppress the electric field concentration phenomenon at the gate corner, reduce the electric field peak in this area, and increase the breakdown voltage of the device. The gallium oxide-based MOSFET device provided by the present invention has the characteristics of high withstand voltage and low leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of the structure of a gallium oxide-based MOSFET device.

[0039] Figure 2 Figure 1 is a schematic diagram of the partial preparation process of gallium oxide-based MOSFET devices, where (a) is a schematic diagram of forming a protective layer on the surface of a gallium oxide substrate; (b) is a schematic diagram of forming a nitrogen-doped gallium oxide layer on the surface of a gallium oxide epitaxial layer precursor layer; (c) is a schematic diagram of injecting Si ions into the upper region of the nitrogen-doped gallium oxide layer to form a highly doped gallium oxide N + Schematic diagram of the precursor layer of the region; (d) is a schematic diagram of the precursor layer of the region ... +Schematic diagram of forming a SiO2 etching hard mask on the surface of the precursor layer of the region; (e) is a schematic diagram of using an etching method to etch the highly doped gallium oxide N + (f) is a schematic diagram of etching two spaced grooves on the surface of the region precursor layer; (f) is a schematic diagram of forming a p-type semiconductor layer on the upper surface of the device obtained in step S5.

[0040] Figure 3 Schematic diagram of a partial preparation process of a gallium oxide-based MOSFET device, wherein (a) is a schematic diagram of forming a soft mask on the upper surface of the device obtained in step S6; (b) is a schematic diagram of etching the p-type semiconductor layer to obtain a first p-type semiconductor buried layer and a second p-type semiconductor buried layer; (c) is a schematic diagram of sequentially forming a gate dielectric layer precursor layer and a gate metal layer precursor layer on the upper surface of the device obtained in step S8; (d) is a schematic diagram of patterning the gate dielectric layer precursor layer and the gate metal layer precursor layer to obtain a gate dielectric layer and a gate metal layer.

[0041] Figure 4 Schematic diagram of a partial preparation process of a gallium oxide-based MOSFET device, wherein (a) is a schematic diagram of forming an interlayer dielectric layer precursor layer on the upper surface of the device obtained in step S10; (b) is a schematic diagram of opening a hole in the interlayer dielectric layer precursor layer to obtain a first interlayer dielectric layer and a second interlayer dielectric layer; (c) is a schematic diagram of forming a hole in the first interlayer dielectric layer and a highly doped gallium oxide N + (d) is a schematic diagram of forming a source metal layer on the surface of the source metal layer and the surface of the second interlayer dielectric layer, and removing the protective layer to form a drain metal layer.

[0042] Figure 5 This is a diagram showing the device-level electrical performance test results of the current blocking layer prepared by the MOCVD method.

[0043] Figure 6 The simulated electric field distribution diagrams near the gate corner of gallium oxide-based MOSFET devices with different gate structures under a bias voltage of 3 kV, where (a) is a gallium oxide-based MOSFET device with a conventional gate structure; (b) is a gallium oxide-based MOSFET device with a gate structure having a p-type nickel oxide buried layer in Example 1.

[0044] Reference numerals in the accompanying drawings:

[0045] 1. Conductive region; 10. First drain metal layer; 11. First gallium oxide substrate; 12. First gallium oxide epitaxial layer; 13. Gallium oxide current blocking layer; 13', Gallium oxide current blocking layer precursor layer; 14. Highly doped gallium oxide N + Area; 14', highly doped gallium oxide N +region precursor layer; 15, first p-type semiconductor buried layer; 16, gate dielectric layer; 16', gate dielectric layer precursor layer; 17, gate metal layer; 17', gate metal layer precursor layer; 18, first interlayer dielectric layer; 19, source metal layer; 2, edge termination region; 20, second drain metal layer; 21, second gallium oxide substrate; 22, second gallium oxide epitaxial layer; 25, second p-type semiconductor buried layer; 28, second interlayer dielectric layer; 3, passivation layer; 120, protective layer; 121, drain metal layer; 122, gallium oxide substrate; 123, gallium oxide epitaxial layer; 123', gallium oxide epitaxial layer precursor layer; 124, nitrogen-doped gallium oxide layer; 125, SiO2 etching hard mask; 126, p-type semiconductor layer; 127, soft mask; 128, interlayer dielectric layer precursor layer. DETAILED DESCRIPTION

[0046] The present invention provides a gallium oxide-based MOSFET device and a method for preparing the same. To make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0047] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0048] The terms used herein such as “vertical”, “horizontal”, “upper”, “lower”, “left”, “right” and similar expressions are for illustrative purposes only and do not represent the only implementations.

[0049] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0050] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

[0051] An embodiment of the present invention provides a gallium oxide-based MOSFET device, wherein, Figure 1 As shown, the gallium oxide-based MOSFET device includes a conductive region 1 and an edge terminal region 2 connected to the conductive region 1; the conductive region 1 includes a first drain metal layer 10, a first gallium oxide substrate 11, a first gallium oxide epitaxial layer 12, a gallium oxide current blocking layer 13 and a highly doped gallium oxide N + Region 14 and the highly doped gallium oxide N + The surface of the region 14 is recessed toward the first gallium oxide substrate 11 , and the bottom of the recess reaches the first gallium oxide epitaxial layer 12 ; the conductive region 1 also includes:

[0052] A first p-type semiconductor buried layer 15, located on the bottom and sidewalls of the groove;

[0053] The gate dielectric layer 16 is located on the surface of the first p-type semiconductor buried layer 15, the sidewall of the groove and the highly doped gallium oxide N + On the surface of region 14 (specifically, the gate dielectric layer is located on the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + on the surface of part of the area);

[0054] A gate metal layer 17, located on the surface of the gate dielectric layer 16;

[0055] A first interlayer dielectric layer 18 covers the surface and side surfaces of the gate metal layer 17 and the side surfaces of the gate dielectric layer 16 (i.e., the first interlayer dielectric layer covers all exposed surfaces of the gate metal layer and all exposed surfaces of the gate dielectric layer, the exposed surface of the gate dielectric layer is perpendicular to the horizontal plane of the device, and the unexposed surface of the gate dielectric layer is covered by the gate metal layer);

[0056] The source metal layer 19 is located between the first interlayer dielectric layer 18 and the highly doped gallium oxide N + Area 14 is on the surface.

[0057] The present invention reduces the leakage current of the device by setting a gallium oxide current blocking layer, and introduces a p-type semiconductor buried layer as an electric field shielding layer under the gate to suppress the electric field concentration phenomenon at the gate corner, reduce the electric field peak in this area, and improve the breakdown voltage of the device. Therefore, the gallium oxide-based power device provided by the present invention has the characteristics of high withstand voltage and low leakage.

[0058] In some embodiments, Figure 1 As shown, the edge terminal region 2 includes a second drain metal layer 20, a second gallium oxide substrate 21, and a second gallium oxide epitaxial layer 22 which are stacked in sequence;

[0059] The second drain metal layer 20 is connected to the first drain metal layer 10 (the second drain metal layer and the first drain metal layer are connected together to form a drain metal layer 121, more specifically, the drain metal layer is an integrated structure, which includes two parts, namely the second drain metal layer and the first drain metal layer), the second gallium oxide substrate 21 is connected to the first gallium oxide substrate 11 (the second gallium oxide substrate and the first gallium oxide substrate are connected together to form a gallium oxide substrate 122, more specifically, the gallium oxide substrate is an integrated structure), the second gallium oxide epitaxial layer 22 is connected to the first gallium oxide epitaxial layer 12 (the second gallium oxide epitaxial layer and the first gallium oxide epitaxial layer are connected together to form a gallium oxide epitaxial layer 123, and the lower surface of the second gallium oxide epitaxial layer is on the same horizontal plane as the lower surface of the first gallium oxide epitaxial layer), and the thickness of the second gallium oxide epitaxial layer is less than the thickness of the first gallium oxide epitaxial layer, and the edge terminal region 2 also includes:

[0060] a second p-type semiconductor buried layer 25, located on the surface of the second gallium oxide epitaxial layer 22 and on the sidewall of the first gallium oxide epitaxial layer 12;

[0061] The second interlayer dielectric layer 28 is located on the surface of the second gallium oxide epitaxial layer 22 and the surface of the second p-type semiconductor buried layer 25, and the second interlayer dielectric layer 28 extends upward to the source metal layer 19 and covers a portion of the highly doped gallium oxide N + The second interlayer dielectric layer 28 is located on the surface of the second gallium oxide epitaxial layer 22, the surface of the second p-type semiconductor buried layer 25, the side of the first gallium oxide epitaxial layer 12, the side of the gallium oxide current blocking layer 13, and the highly doped gallium oxide N + The side of region 14 and the highly doped gallium oxide N + Partial surface of zone 14).

[0062] In some embodiments, the thickness of the first drain metal layer is 300nm~1.5μm, for example, it can be 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc. The thickness of the second drain metal layer is 300nm~1.5μm, for example, it can be 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc. The metal used in the first drain metal layer can be a common metal used in the drain of existing semiconductor devices. As an example, the first drain metal layer includes at least one of Ti, Ni and Ag, but is not limited to this. The metal used for the second drain metal layer may be a common metal used for drains of existing semiconductor devices. For example, the second drain metal layer includes at least one of Ti, Ni and Ag, but is not limited thereto.

[0063] In some embodiments, the thickness of the first gallium oxide substrate is 50 to 650 μm (for example, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm, etc.), and the first gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (i.e., electron concentration) of 10 18 ~10 20 cm -3 , for example, it can be 10 18 cm -3 , 5×10 18 cm -3 , 10 19 cm -3 , 5×10 19 cm -3 or 10 20 cm -3 In some specific embodiments, the first gallium oxide substrate comprises Si or Sn doped β-Ga2O 3。

[0064] In some embodiments, the thickness of the second gallium oxide substrate is 50 to 650 μm (for example, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm or 650 μm, etc.), and the second gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration (i.e., electron concentration) of 10 18 ~1020 cm -3 , for example, it can be 10 18 cm -3 , 5×10 18 cm -3 , 10 19 cm -3 , 5×10 19 cm -3 or 10 20 cm -3 In some specific embodiments, the second gallium oxide substrate comprises Si or Sn doped β-Ga2O 3。

[0065] In some embodiments, the thickness of the first gallium oxide epitaxial layer is 2 to 20 μm, for example, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm or 20 μm.

[0066] The first gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, electron concentration) is 10 15 ~10 17 cm -3 , for example, it can be 10 15 cm -3 , 5×10 15 cm -3 , 10 16 cm -3 , 5×10 16 cm -3 , or 10 17 cm -3 In some specific embodiments, the first gallium oxide epitaxial layer includes Si or Sn doped β-Ga2O3.

[0067] In some embodiments, the second gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer, and the doping concentration (ie, electron concentration) is 10 15 ~10 17 cm -3 , for example, it can be 10 15 cm -3 , 5×10 15 cm -3 , 10 16 cm -3 , 5×10 16 cm -3 , or 10 17 cm -3 In some specific embodiments, the second gallium oxide epitaxial layer includes Si or Sn doped β-Ga2O3.

[0068] In some embodiments, the gallium oxide current blocking layer has a thickness of 500 nm to 3 μm, for example, 500 nm, 800 nm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm. The gallium oxide current blocking layer includes nitrogen-doped gallium oxide, and the nitrogen doping concentration is 10 17 ~10 19 cm -3 , for example, it can be 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 In some specific embodiments, the gallium oxide current blocking layer includes β-Ga2O3 doped with nitrogen (N).

[0069] In some embodiments, the highly doped gallium oxide N + The thickness of the region is 100 to 300 nm, for example, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, and the doping concentration (i.e., electron concentration) is 10 18 ~10 20 cm -3 , for example, it can be 10 18 cm -3 , 5×10 18 cm -3 , 10 19 cm -3 , 5×10 19 cm -3 or 10 20 cm -3 In some specific embodiments, the highly doped gallium oxide N + The region is a nitrogen-doped gallium oxide layer implanted with Si ions. More specifically, the highly doped gallium oxide N + The region is a nitrogen-doped β-Ga2O3 layer implanted with Si ions.

[0070] In some embodiments, the thickness of the first p-type semiconductor buried layer is 100-600nm (i.e., the thickness of all parts of the first p-type semiconductor buried layer is 100-600nm, i.e., the thickness of the part of the first p-type semiconductor buried layer located on the bottom of the groove is 100-600nm, and the thickness of the part of the first p-type semiconductor buried layer located on the sidewall of the groove is also 100-600nm), for example, it can be 100nm, 200nm, 300nm, 400nm, 500nm or 600nm. The hole concentration of the first p-type semiconductor buried layer is 10 16 ~10 19 cm -3 (For example, it can be 10 16 cm -3 , 5×10 16 cm -3 , 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 The first p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide, but is not limited thereto.

[0071] In some embodiments, Figure 1 As shown, the height of the portion of the first p-type semiconductor buried layer 15 located on the sidewall of the groove is not higher than the lower surface of the gallium oxide current blocking layer 13. That is, the highest point of the upper surface of the first p-type semiconductor buried layer is not higher than the interface between the gallium oxide current blocking layer 13 and the first gallium oxide epitaxial layer 12.

[0072] In some embodiments, the thickness of the second p-type semiconductor buried layer is 100-600nm (i.e., the thickness of all parts of the second p-type semiconductor buried layer is 100-600nm, i.e., the thickness of the part of the second p-type semiconductor buried layer located on the surface of the second gallium oxide epitaxial layer is 100-600nm, and the thickness of the part of the second p-type semiconductor buried layer located on the side wall of the first gallium oxide epitaxial layer is also 100-600nm), for example, it can be 100nm, 200nm, 300nm, 400nm, 500nm or 600nm. The hole concentration of the second p-type semiconductor buried layer is 10 16 ~10 19 cm -3 (For example, it can be 10 16 cm -3 , 5×1016 cm -3 , 10 17 cm -3 , 5×10 17 cm -3 , 10 18 cm -3 , 5×10 18 cm -3 or 10 19 cm -3 The second p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide. The height of the portion of the second p-type semiconductor buried layer 25 located on the sidewall of the first gallium oxide epitaxial layer is not higher than the upper surface of the first gallium oxide epitaxial layer, that is, the highest point of the upper surface of the second p-type semiconductor buried layer is not higher than the interface between the gallium oxide current blocking layer 13 and the first gallium oxide epitaxial layer 12.

[0073] In some embodiments, the thickness of the gate dielectric layer is 10 to 100 nm (i.e., the thickness of all parts of the gate dielectric layer is 10 to 100 nm, that is, the thickness of the portion of the gate dielectric layer located on the surface of the first p-type semiconductor buried layer is 10 to 100 nm, the thickness of the portion of the gate dielectric layer located on the sidewall of the groove is 10 to 100 nm, and the thickness of the gate dielectric layer located on the highly doped gallium oxide N + The thickness of the portion on the surface of the region is also 10 to 100 nm), for example, it can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm, etc. The gate dielectric layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide, but is not limited thereto.

[0074] In some embodiments, the thickness of the gate metal layer is 50 to 300 nm (i.e., the thickness of all parts of the gate metal layer is 50 to 300 nm), for example, it can be 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc.; the metal used in the gate metal layer can be a common metal used in the gate of existing semiconductor devices. As an example, the gate metal layer includes at least one of chromium, nickel, gold, polysilicon and aluminum.

[0075] In some embodiments, the thickness of the first interlayer dielectric layer is 500nm~1.5μm (that is, the thickness of all parts of the first interlayer dielectric layer is 500nm~1.5μm, that is, the thickness of the part of the first interlayer dielectric layer located on the surface and side of the gate metal layer is 500nm~1.5μm, and the thickness of the part of the first interlayer dielectric layer located on the side of the gate dielectric layer is also 500nm~1.5μm), for example, it can be 500nm, 800nm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc.; the material of the first interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, borophosphosilicate glass (BPSG) and tetraethoxysilane (TEOS), but is not limited thereto.

[0076] In some embodiments, the thickness of the second interlayer dielectric layer is 500nm-1.5μm (i.e., the thickness of all parts of the second interlayer dielectric layer is 500nm-1.5μm, i.e., the thickness of the part of the second interlayer dielectric layer located on the surface of the second gallium oxide epitaxial layer and the surface of the second p-type semiconductor buried layer is 500nm-1.5μm, and the second interlayer dielectric layer extends upward to the source metal layer and covers a part of the highly doped gallium oxide N + The thickness of the portion on the surface of the region is also 500nm-1.5μm), for example, 500nm, 800nm, 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc. The material of the second interlayer dielectric layer includes at least one of silicon oxide, silicon nitride, borophosphosilicate glass (BPSG) and tetraethoxysilane (TEOS), but is not limited thereto.

[0077] In some embodiments, the thickness of the source metal layer is 300nm to 4μm, for example, it can be 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.4μm or 4μm, etc.; the metal used in the source metal layer can be a common metal used in the source of existing semiconductor devices. As an example, the source metal layer includes at least one of Ti and Al, but is not limited to this.

[0078] In some embodiments, the gallium oxide-based MOSFET device further includes a passivation layer 3, which is located on a portion of the surface of the source metal layer 19 and on the surface of the second interlayer dielectric layer 28. The passivation layer can be provided according to actual needs. In some embodiments, the material of the passivation layer includes at least one of polyimide (PI), silicon nitride, silicon oxide, and SU-8 glue, but is not limited thereto.

[0079] The present invention also provides a method for preparing a gallium oxide-based MOSFET device, comprising the following steps:

[0080] A first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current blocking layer and a highly doped gallium oxide N are sequentially formed on the first drain metal layer. + district;

[0081] In the highly doped gallium oxide N + A groove is formed on the surface of the region and is recessed toward the first gallium oxide substrate, and the bottom of the groove reaches the first gallium oxide epitaxial layer;

[0082] forming a first p-type semiconductor buried layer on the bottom and sidewalls of the groove;

[0083] On the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + forming a gate dielectric layer on the surface of the region;

[0084] forming a gate metal layer on the surface of the gate dielectric layer;

[0085] forming a first interlayer dielectric layer on the surface and side surfaces of the gate metal layer and the side surfaces of the gate dielectric layer;

[0086] The first interlayer dielectric layer and the highly doped gallium oxide N + forming a drain metal layer on the surface of the region to obtain a conductive region;

[0087] The conductive region is connected to the edge terminal region to obtain the gallium oxide-based MOSFET device.

[0088] In some embodiments, the method for preparing the gallium oxide-based MOSFET device specifically includes the following steps S1 to S14.

[0089] Among them, S1, Figure 2 As shown in (a), a gallium oxide substrate 122 having a gallium oxide epitaxial layer precursor layer 123' disposed on the surface is provided, a protective layer 120 (made of silicon oxide or silicon nitride, etc., with a thickness of 500nm to 2μm, for example, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 1.2μm, 1.5μm, 1.8μm or 2μm, etc.) is formed on the surface of the gallium oxide substrate 122, and organic and inorganic cleaning are performed.

[0090] In this step, the material and thickness of the gallium oxide substrate are the material and thickness of the first gallium oxide substrate or the second gallium oxide substrate, see above for details. The material and thickness of the gallium oxide epitaxial layer precursor layer are the material and thickness of the first gallium oxide epitaxial layer, see above for details.

[0091] S2, such as Figure 2 As shown in (b) of FIG. 1 , a nitrogen-doped gallium oxide layer 124 is formed on the surface of the gallium oxide epitaxial layer precursor layer 123 ′.

[0092] In this step, a nitrogen-doped gallium oxide layer (with a nitrogen doping concentration of 10 17 ~10 19 cm -3 ), specifically using N2O as the doping reaction gas, using at least one of triethylgallium (TEGa), diisobutylgallium and trimethylgallium as the gallium source, using argon as the carrier gas, and the process parameters are: the flow rate of the doping reaction gas is 1000-50000sccm (for example, it can be 1000sccm, 2000sccm, 3000sccm, 4000sccm, 5000sccm, 6000sccm, 7000sccm, 8000sccm, 9000sccm, 10000sccm, 15000sccm, 20000sccm, 25000sccm, 30000sccm, 35000sccm, 40000sccm, 45000sccm or 50000sccm, etc.) , the flow rate of the gallium source is 20-200sccm (for example, it can be 20sccm, 30sccm, 50sccm, 80sccm, 100sccm, 120sccm, 150sccm, 180sccm or 200sccm, etc.), the growth temperature is 800-1200℃ (for example, it can be 800℃, 850℃, 900℃, 950℃, 1000℃, 1050℃, 1100℃, 1150℃ or 1200℃, etc.), and the growth pressure is 50-500mbar (for example, it can be 50mbar, 100mbar, 150mbar, 200mbar, 250mbar, 300mbar, 350mbar, 400mbar, 450mbar or 500mbar, etc.).

[0093] After the subsequent process, the nitrogen-doped gallium oxide layer finally becomes the current blocking layer. Compared with the current blocking layer realized by direct nitrogen ion implantation (the current blocking layer prepared by direct nitrogen ion implantation is of poor quality, with problems such as low impurity doping concentration, lattice damaged by high-energy ions, and a large number of vacancies, which affect the resistivity of the current blocking layer and significantly increase the leakage level of the MOSFET device, which can be reduced by 10% from the diode -4 A / cm 2 Increase to 1A / cm 2), the nitrogen-doped gallium oxide layer obtained by homoepitaxial growth on the surface of the gallium oxide epitaxial layer precursor layer by the MOCVD method of the present invention does not have the problems existing in nitrogen ion implantation. The nitrogen-doped gallium oxide layer prepared in this step has high quality, high nitrogen doping concentration and high resistivity, which can greatly reduce the leakage of the device.

[0094] Specifically, the device-level electrical performance test results of the current blocking layer prepared by MOCVD are as follows: Figure 5 As shown in the figure, it can be seen that the device has only 8×10 -5 A / cm 2 The leakage current of the device is comparable to that of the existing gallium oxide diode and FinFET (FinFET is a structure that introduces the Fin channel into the MOSFET. Under the condition of zero gate bias, the extremely narrow Fin channel is depleted by the work function difference between the gate metal and the n-type Ga2O3, thereby realizing the enhanced characteristics without the participation of the p-type Ga2O3; at the same time, due to the extremely small spacing between adjacent gates, the electric field concentration phenomenon at the gate corner can be significantly suppressed, the electric field peak at this position can be reduced, and the voltage resistance of the device can be improved. However, the threshold voltage of the FinFET device is also heavily dependent on the work function difference between the gate metal and the n-type Ga2O3, resulting in a low threshold voltage and difficulty in regulation; in addition, the FinFET requires extremely fine lithography accuracy and overlay accuracy, which significantly increases the process difficulty and processing cost of the device) device, but is much smaller than the leakage level of the MOSFET device based on the existing current blocking layer (such as the current blocking layer achieved by nitrogen ion implantation). Therefore, it is shown that the device based on the current blocking layer prepared by the present invention has the advantage of low leakage.

[0095] S3, such as Figure 2 As shown in (c), Si ions are injected into the upper region of the nitrogen-doped gallium oxide layer 124 to form a highly doped gallium oxide N + The precursor layer 14' of the region is formed, and the remaining part of the lower layer of the nitrogen-doped gallium oxide layer is the precursor layer 13' of the gallium oxide current blocking layer.

[0096] In this step, the highly doped gallium oxide N + The doping concentration and thickness of the precursor layer of the region are the highly doped gallium oxide N + The doping concentration and thickness of the region are specifically referred to above. The thickness of the gallium oxide current blocking layer precursor layer is referred to the thickness of the gallium oxide current blocking layer above.

[0097] S4, such as Figure 2 As shown in (d), the highly doped gallium oxide N + A SiO2 etching hard mask 125 is formed on the surface of the region precursor layer 14'.

[0098] S5, such as Figure 2As shown in (e), an etching method (such as ICP etching) is used to form a highly doped gallium oxide N + Two spaced grooves are etched on the surface of the region precursor layer 14', the bottoms of the two grooves both reach the gallium oxide epitaxial layer precursor layer 123', and one groove is in the middle position (forming a U-shaped groove), and the other groove is at the edge (forming an L-shaped groove), thereby obtaining the gallium oxide current blocking layer 13 and the highly doped gallium oxide N + Region 14 and gallium oxide epitaxial layer 123 .

[0099] In this step, the highly doped gallium oxide N + After the region precursor layer 14' is etched, a highly doped gallium oxide N + In region 14, after the gallium oxide current blocking layer precursor layer 13' is etched, the gallium oxide current blocking layer 13 is formed, and after the gallium oxide epitaxial layer precursor layer 123' is etched, the gallium oxide epitaxial layer 123 is formed. + After the grooves are etched, the remaining parts of the region precursor layer 14', the gallium oxide current blocking layer precursor layer 13' and the gallium oxide epitaxial layer precursor layer 123' are respectively highly doped gallium oxide N + region 14 , the gallium oxide current blocking layer 13 and the gallium oxide epitaxial layer 123 .

[0100] S6, such as Figure 2 As shown in (f), a p-type semiconductor is deposited on the upper surface of the device obtained in step S5 (such as by magnetron sputtering deposition, pulsed laser deposition, MOCVD, metal thermal oxidation, etc.), and then stripped or etched to pattern it to form a p-type semiconductor layer 126.

[0101] In this step, the selection of the p-type semiconductor refers to the selection of the material of the first p-type semiconductor buried layer. The thickness of the p-type semiconductor layer refers to the thickness of the first p-type semiconductor buried layer.

[0102] When the p-type semiconductor is p-type NiO, the p-type NiO can be prepared by a Ni metal thermal oxidation method.

[0103] S7, such as Figure 3 As shown in (a) in FIG. 1 , a photoresist is coated (e.g., spin-coated) on the upper surface of the device obtained in step S6, and a flood exposure is performed to form a soft mask 127 (the upper surface of the soft mask 127 is not higher than the upper surface of the highest point of the gallium oxide epitaxial layer 123. This step is performed in order to subsequently form a first p-type semiconductor buried layer and a second p-type semiconductor buried layer. Because the height of the portion of the first p-type semiconductor buried layer located on the side wall of the groove is not higher than the lower surface of the gallium oxide current blocking layer, it is required that the upper surface of the soft mask 127 is not higher than the upper surface of the highest point of the gallium oxide epitaxial layer 123).

[0104] S8, such as Figure 3As shown in (b), the p-type semiconductor layer 126 is etched (eg, using a hydrochloric acid solution to etch the p-type semiconductor layer) to obtain a first p-type semiconductor buried layer 15 and a second p-type semiconductor buried layer 25.

[0105] S9, such as Figure 3 As shown in (c) in FIG. 1 , a gate dielectric layer precursor layer 16 ′ and a gate metal layer precursor layer 17 ′ are sequentially formed on the upper surface of the device obtained in step S8 .

[0106] The selection of materials and thicknesses of the gate dielectric layer precursor layer and the gate metal layer precursor layer refer to the selection of the gate dielectric layer and the gate metal layer mentioned above, respectively.

[0107] S10, such as Figure 3 As shown in (d) , the gate dielectric layer precursor layer 16 ′ and the gate metal layer precursor layer 17 ′ are patterned (may be performed by a dry-wet combined etching process) to obtain the gate dielectric layer 16 and the gate metal layer 17 .

[0108] In this step, after etching the gate dielectric layer precursor layer 16 ′, the remaining portion is the gate dielectric layer 16 . Similarly, after etching the gate metal layer precursor layer 17 ′, the remaining portion is the gate metal layer 17 .

[0109] S11, such as Figure 4 As shown in (a) of FIG. 1 , an interlayer dielectric layer precursor layer 128 is formed on the upper surface of the device obtained in step S10 .

[0110] In this step, the material and thickness of the interlayer dielectric layer precursor layer refer to the material and thickness of the first interlayer dielectric layer mentioned above.

[0111] S12, such as Figure 4 As shown in (b) of FIG. 1 , the interlayer dielectric layer precursor layer 128 is opened by using a dry-wet combined etching process to obtain a first interlayer dielectric layer 18 and a second interlayer dielectric layer 28 .

[0112] S13, such as Figure 4 As shown in (c), between the first interlayer dielectric layer 18 and the highly doped gallium oxide N + A source metal layer 19 is formed on the surface of region 14 (this can be accomplished by depositing a gate metal by electron beam evaporation or magnetron sputtering).

[0113] In this step, the material and thickness of the source metal layer are as described above.

[0114] S14, such as Figure 4As shown in (d), a polyimide passivation layer is formed on a portion of the surface of the source metal layer 19 and the surface of the second interlayer dielectric layer 28 by using a standard polyimide photolithography process; the wafer is flipped over, and after removing the back protection layer 120, a drain metal is deposited on the back of the device (i.e., on the side of the gallium oxide substrate 122 away from the gallium oxide epitaxial layer 123) to form a drain metal layer 121 (including a first drain metal layer 10 and a second drain metal layer 20). More specifically, at least one metal selected from Ti, Ni and Ag can be deposited on the surface of the device by electron beam evaporation or magnetron sputtering to form a drain metal layer.

[0115] The present invention will be further described below by means of specific examples.

[0116] Example 1

[0117] This embodiment provides a gallium oxide-based MOSFET device, wherein: Figure 1 As shown (but with Figure 1 The device shown in the figure is different in that: the gallium oxide-based MOSFET device in this embodiment does not contain a passivation layer 3), and the gallium oxide-based MOSFET device includes a conductive region 1 and an edge terminal region 2 connected to the conductive region 1; the conductive region 1 includes a first drain metal layer 10, a first gallium oxide substrate 11, a first gallium oxide epitaxial layer 12, a gallium oxide current blocking layer 13 and a highly doped gallium oxide N + Region 14 and the highly doped gallium oxide N + A groove on the surface of the region 14 is sunken toward the first gallium oxide substrate 11 , and the bottom of the groove reaches the first gallium oxide epitaxial layer 12 ;

[0118] The first drain metal layer includes a Ti layer (100 nm thick), a Ni layer (300 nm thick) and an Ag layer (1 μm thick) stacked in sequence, and the Ti layer is attached to the first gallium oxide substrate; the first gallium oxide substrate is 500 μm thick, and the first gallium oxide substrate is a Sn-doped β-Ga2O3 substrate with an electron concentration of 10 20 cm -3 The thickness of the first gallium oxide epitaxial layer is 10 μm. The first gallium oxide epitaxial layer is a Si-doped β-Ga2O3 epitaxial layer with an electron concentration of 10 16 cm -3 The thickness of the gallium oxide current blocking layer is 2 μm. The gallium oxide current blocking layer is a nitrogen-doped β-Ga2O3 layer (prepared by MOCVD method, with N2O as the doping reaction gas, argon as the carrier gas, TEGa as the gallium source, N2O flow rate of 10000 sccm, TEGa flow rate of 100 sccm, growth temperature of 1000 ° C, and growth pressure of 100 mbar.), and the nitrogen doping concentration is 1018 cm -3 Highly doped gallium oxide N + The thickness of the region is 200nm, and the material is a nitrogen-doped β-Ga2O3 layer injected with Si ions, with an electron concentration of 10 20 cm -3 , the nitrogen doping concentration is 10 18 cm -3 The depth of the groove is 3.2 μm.

[0119] The conductive area 1 further comprises:

[0120] The first p-type semiconductor buried layer 15 is located at the bottom and sidewalls of the groove; the thickness of the first p-type semiconductor buried layer is 300nm, the material is p-type NiO, and the hole concentration is 10 18 cm -3 ; The height of the first p-type semiconductor buried layer on the sidewall of the groove is 600nm;

[0121] The gate dielectric layer 16 is located on the surface of the first p-type semiconductor buried layer 15, the sidewall of the groove and the highly doped gallium oxide N + The thickness of the gate dielectric layer is 100 nm, and the material of the gate dielectric layer is Al2O3;

[0122] A gate metal layer 17 is located on the surface of the gate dielectric layer 16; the gate metal layer has a thickness of 200 nm and is made of nickel;

[0123] A first interlayer dielectric layer 18 covers the surface and side surfaces of the gate metal layer 17 and the side surfaces of the gate dielectric layer 16; the thickness of the first interlayer dielectric layer is 1 μm, and the material of the first interlayer dielectric layer is silicon oxide;

[0124] The source metal layer 19 is located between the first interlayer dielectric layer 18 and the highly doped gallium oxide N + On the surface of region 14, the source metal layer includes a Ti layer (100 nm thick) and an Al layer (3 μm thick) stacked in sequence, wherein the Ti layer is disposed on the side of the first interlayer dielectric layer.

[0125] The edge termination region 2 includes a second drain metal layer 20, a second gallium oxide substrate 21, and a second gallium oxide epitaxial layer 22 which are stacked in sequence; the material and thickness of the second drain metal layer are the same as those of the first drain metal layer, and the material and thickness of the second gallium oxide substrate are the same as those of the first gallium oxide substrate. The material of the second gallium oxide epitaxial layer is the same as that of the first gallium oxide epitaxial layer, and the thickness of the second gallium oxide epitaxial layer is less than that of the first gallium oxide epitaxial layer, that is, the thickness of the second gallium oxide epitaxial layer is 5 μm;

[0126] The second drain metal layer 20 is connected to the first drain metal layer 10 (the second drain metal layer and the first drain metal layer are connected together to form a drain metal layer 121), the second gallium oxide substrate 21 is connected to the first gallium oxide substrate 11 (the second gallium oxide substrate and the first gallium oxide substrate are connected together to form a gallium oxide substrate 122), and the second gallium oxide epitaxial layer 22 is connected to the first gallium oxide epitaxial layer 12 (the second gallium oxide epitaxial layer and the first gallium oxide epitaxial layer are connected together to form a gallium oxide epitaxial layer 123).

[0127] The edge terminal area 2 also includes:

[0128] A second p-type semiconductor buried layer 25 is located on the surface of the second gallium oxide epitaxial layer 22 and on the sidewall of the first gallium oxide epitaxial layer 12; the material and thickness of the second p-type semiconductor buried layer are the same as those of the first p-type semiconductor buried layer; the height of the second p-type semiconductor buried layer on the sidewall of the first gallium oxide outer layer is 4.6 μm;

[0129] The second interlayer dielectric layer 28, the surface of the second gallium oxide epitaxial layer 22, the surface of the second p-type semiconductor buried layer 25, the side surface of the first gallium oxide epitaxial layer 12, the side surface of the gallium oxide current blocking layer 13, the highly doped gallium oxide N + The side of region 14 and the highly doped gallium oxide N + On a partial surface of the region 14 , the material and thickness of the second interlayer dielectric layer are the same as those of the first interlayer dielectric layer.

[0130] The simulated electric field distribution diagrams of the conventional gate structure gallium oxide based MOSFET (the difference from the device in Example 1 is that it does not contain the first p-type semiconductor buried layer and the second p-type semiconductor buried layer) and the gate structure gallium oxide based MOSFET device with a p-type nickel oxide buried layer in Example 1 under a bias voltage of 3 kV are shown in FIG. Figure 6 As shown. Figure 6 As can be seen from (a) in the figure, the conventional gate structure has a significant electric field concentration phenomenon at the corner, resulting in an ultra-high electric field of more than 15MV / cm in the gate dielectric layer. In practical applications, this electric field strength will induce the gate dielectric layer to break down prematurely, thereby reducing the breakdown voltage of the device. Figure 6 It can be seen from (b) that the electric field concentration phenomenon at the gate corner in the device of Example 1 is significantly suppressed by the p-type nickel oxide buried layer (i.e., the first p-type semiconductor buried layer), and the electric field peak is also reduced from 15.3MV / cm of the conventional gate structure to 6.8MV / cm. Therefore, by setting the p-type semiconductor buried layer, the gate dielectric layer can be effectively prevented from breaking down prematurely, thereby greatly improving the voltage resistance of the device.

[0131] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A gallium oxide-based MOSFET device, characterized in that: The gallium oxide-based MOSFET device comprises a conductive region and an edge terminal region connected to the conductive region; the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current blocking layer and a highly doped gallium oxide N + The highly doped gallium oxide N + A groove on the surface of the region is sunken toward the first gallium oxide substrate, and the bottom of the groove reaches the first gallium oxide epitaxial layer; The conductive area further comprises: A first p-type semiconductor buried layer is located on the bottom and sidewalls of the groove; The gate dielectric layer is located on the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + on the surface of the area; A gate metal layer, located on the surface of the gate dielectric layer; A first interlayer dielectric layer covers the surface and side surfaces of the gate metal layer and the side surfaces of the gate dielectric layer; The source metal layer is located between the first interlayer dielectric layer and the highly doped gallium oxide N + on the surface of the area.

2. The gallium oxide-based MOSFET device according to claim 1, characterized in that: The edge termination region includes a second drain metal layer, a second gallium oxide substrate, and a second gallium oxide epitaxial layer which are stacked in sequence; The second drain metal layer is connected to the first drain metal layer, the second gallium oxide substrate is connected to the first gallium oxide substrate, the second gallium oxide epitaxial layer is connected to the first gallium oxide epitaxial layer, and the thickness of the second gallium oxide epitaxial layer is less than the thickness of the first gallium oxide epitaxial layer, and the edge termination region further includes: a second p-type semiconductor buried layer, located on the surface of the second gallium oxide epitaxial layer and on the sidewall of the first gallium oxide epitaxial layer; The second interlayer dielectric layer is located on the surface of the second gallium oxide epitaxial layer and the surface of the second p-type semiconductor buried layer, and the second interlayer dielectric layer extends upward to the source metal layer and covers a portion of the highly doped gallium oxide N + Area surface.

3. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The thickness of the first gallium oxide substrate is 50 to 650 μm. The first gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 The thickness of the second gallium oxide substrate is 50 to 650 μm, and the second gallium oxide substrate is a highly doped n-type gallium oxide substrate with a doping concentration of 10 18 ~10 20 cm -3 .

4. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The thickness of the first gallium oxide epitaxial layer is 2 to 20 μm; The first gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 ; The second gallium oxide epitaxial layer is a low-doped n-type gallium oxide epitaxial layer with a doping concentration of 10 15 ~10 17 cm -3 .

5. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The gallium oxide current blocking layer has a thickness of 500 nm to 3 μm, and the gallium oxide current blocking layer includes nitrogen-doped gallium oxide with a nitrogen doping concentration of 10 17 ~10 19 cm -3 ; The highly doped gallium oxide N + The thickness of the region is 100 to 300 nm, and the doping concentration is 10 18 ~10 20 cm -3 .

6. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The thickness of the first p-type semiconductor buried layer is 100-600 nm, and the hole concentration of the first p-type semiconductor buried layer is 10 16 ~10 19 cm -3 , the first p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide; The height of the portion of the first p-type semiconductor buried layer located on the sidewall of the groove is not higher than the lower surface of the gallium oxide current blocking layer; The thickness of the second p-type semiconductor buried layer is 100-600 nm, and the hole concentration of the second p-type semiconductor buried layer is 10 16 ~10 19 cm -3 The second p-type semiconductor buried layer includes at least one of p-type NiO, p-type diamond and p-type gallium oxide.

7. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The gate dielectric layer has a thickness of 10-100 nm, and includes at least one of silicon oxide, silicon nitride, aluminum oxide and hafnium dioxide.

8. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The gate metal layer has a thickness of 50-300 nm; the gate metal layer includes at least one of chromium, nickel, gold, polysilicon and aluminum.

9. The gallium oxide-based MOSFET device according to claim 2, characterized in that: The thickness of the first interlayer dielectric layer is 500nm-1.5μm, and the thickness of the second interlayer dielectric layer is 500nm-1.5μm; The gallium oxide-based MOSFET device further includes a passivation layer, which is located on a portion of the surface of the source metal layer and on a surface of the second interlayer dielectric layer.

10. A method for preparing a gallium oxide-based MOSFET device, characterized in that: The steps include: A first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current blocking layer and a highly doped gallium oxide N are sequentially formed on the first drain metal layer. + district; In the highly doped gallium oxide N + A groove is formed on the surface of the region and is recessed toward the first gallium oxide substrate, and the bottom of the groove reaches the first gallium oxide epitaxial layer; forming a first p-type semiconductor buried layer on the bottom and sidewalls of the groove; On the surface of the first p-type semiconductor buried layer, the sidewall of the groove and the highly doped gallium oxide N + forming a gate dielectric layer on the surface of the region; forming a gate metal layer on the surface of the gate dielectric layer; forming a first interlayer dielectric layer on the surface and side surfaces of the gate metal layer and the side surfaces of the gate dielectric layer; The first interlayer dielectric layer and the highly doped gallium oxide N + forming a drain metal layer on the surface of the region to obtain a conductive region; The conductive region is connected to the edge terminal region to obtain the gallium oxide-based MOSFET device.

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