Page table virtual address conversion method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a page table virtual address conversion method and device, equipment and a storage medium, and relates to the technical field of financial science and technology and artificial intelligence. The method comprises the steps that a page table virtual address is obtained, the page table virtual address comprises first address information and offset, then the first address information is input into an address index model to execute an address query process, a regression function is selected from a tree structure to serve as a target function, a predicted page table entry address of the first address information is calculated according to the target function, and the predicted page table entry address is obtained. Calculating according to the first address information and the predicted page table entry address to obtain second address information; and performing address offset based on the second address information and the offset to obtain a physical address of the page table virtual address. According to the embodiment of the invention, the address index model is utilized to predict the page table entry address corresponding to the first address information, step-by-step searching according to the stage number of the page table is not needed, the delay of searching the page table entry address can be reduced, and the conversion efficiency from the virtual address to the physical address is accelerated.

Description

Technical Field

[0001] The present invention relates to the fields of financial technology and artificial intelligence technology, and in particular to a page table virtual address conversion method, device, equipment and storage medium. Background Art

[0002] As the amount of data in the financial industry continues to grow, financial institutions need to carry more data, which makes cloud storage increasingly important as a way of information management. By using cloud storage technology, financial institutions can store large amounts of data in the cloud at a low cost, while allowing users to access and process data anytime and anywhere. Cloud storage technology allocates virtual memory to each process through the operating system. When a certain space is used, the data is stored in the real physical memory through address conversion. Since the physical address is the real physical memory access address, when allocating memory to the process, the virtual address needs to be mapped to the physical address. The conversion between virtual addresses and physical addresses is achieved through the paging mechanism. In cloud storage, page table virtual address conversion is usually used for file retrieval and access.

[0003] In the related art, the operating system uses a multi-level page table to search for page table entries. When searching, it first searches from each level of the page table one by one until the address of the page table entry is located, and then finds the final physical address through the page offset. However, this page search method is time-consuming, resulting in a low efficiency in the virtual address translation process, and is not suitable for scenarios that require fast access to processes. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a page table virtual address conversion method, device, equipment and storage medium to improve the efficiency of virtual address conversion.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a page table virtual address conversion method, which is applied to an address index model, wherein the address index model is a tree structure, and the address index model includes at least one original node, and the original node is a regression function; the method comprises:

[0006] Obtaining a page table virtual address, the page table virtual address comprising: first address information and an offset, the first address information comprising a page global directory address, a page upper directory address, and a page intermediate directory address;

[0007] Performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result;

[0008] Acquire the first address information according to the target function to obtain a predicted page table entry address;

[0009] Performing address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain second address information;

[0010] An address offset is performed based on the second address information and the offset to obtain a physical address of the page table virtual address.

[0011] In some embodiments, the original node includes a parent node and a child node, the parent node includes a root node, and the child node includes a leaf node; performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result, includes:

[0012] Acquire a target node according to the root node; wherein the target node includes child nodes, and an initial value of the target node is the root node;

[0013] Filtering a query node from the child nodes according to the first address information;

[0014] Determine whether the query node is the leaf node; if the query node is not the leaf node, take the query node as the target node and repeat the address query process until the query node is a leaf node;

[0015] The regression function of the leaf node is obtained as the objective function.

[0016] In some embodiments, filtering out a query node from the child nodes according to the first address information includes:

[0017] Obtaining the input data range of each of the child nodes to obtain the target data range;

[0018] If the first address information is found within the target data range, the child node is used as the query node.

[0019] In some embodiments, acquiring the first address information according to the target function to obtain the predicted page table entry address includes:

[0020] Obtaining a plurality of address prediction values ​​according to an output data range of the objective function;

[0021] Obtaining an output address corresponding to the first address information in the target function;

[0022] Subtracting the address prediction value from the output address to obtain an address difference value;

[0023] The address prediction value corresponding to the minimum value of the address difference is selected as the predicted page table entry address.

[0024] In some embodiments, before performing address query processing on the first address information by using the address index model, the method further includes:

[0025] Constructing a plurality of training address information, wherein the training address information is generated according to a page global directory address, a page upper directory address, and a page intermediate directory address;

[0026] Sorting the training address information to obtain a first address value and a second address value, and generating a first input range according to the first address value and the second address value, and sorting the destination page table entry address to obtain a first page table entry address and a second page table entry address, and generating a first output range according to the first page table entry address and the second page table entry address;

[0027] The original node differentiation step is executed to construct the address index model, and the original node differentiation step includes:

[0028] Generate an input data range and an output data range of a training parent node, and generate a regression function of the training parent node by fitting according to the input data range and the output data range; the initial value of the training parent node is a root node; the input data range of the root node includes the first input range, and the output data range of the root node includes the first output range;

[0029] Dividing the input data range of the training parent node into a plurality of sub-input ranges according to the number of training child nodes, and dividing the output data range into sub-output ranges corresponding to the sub-input ranges, wherein the number of the training child nodes is a first number; the first number is an integer greater than or equal to 1;

[0030] The regression function of the training child node is generated by fitting according to the sub-input range and the sub-output range; the sub-input range of the training child node constitutes the input data range of the training parent node, and the sub-output range of the training child node constitutes the output data range of the training parent node;

[0031] The training child node is used as the next training parent node, and the original node differentiation step is repeated until each training address information corresponds to a leaf node as the target training node, thereby obtaining the address index model.

[0032] In some embodiments, the training address information further includes a page table tag, and the page table tag is a destination page table entry address of the training address information; until each of the training address information corresponds to a leaf node as a target training node, the address index model is obtained, including:

[0033] Obtaining a training page table entry address corresponding to the training address information in the regression function of the leaf node;

[0034] Calculating the loss value between the training page table entry address and the destination page table entry address;

[0035] If the loss value is less than a preset threshold, the leaf node is determined to be the target training node.

[0036] In some embodiments, before calculating the second address information according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address, the method further includes:

[0037] Obtaining a flag bit of the predicted page table entry address;

[0038] The predicted page table entry address is checked for validity using the flag bit. If the flag bit indicates that the predicted page table entry address exists in the physical memory, the validity check passes.

[0039] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application proposes a page table virtual address conversion device, which is applied to an address index model, wherein the address index model is a tree structure, and the address index model includes at least one original node, and the original node is a regression function; the device includes:

[0040] A page table virtual address acquisition module, used to acquire a page table virtual address, wherein the page table virtual address includes: first address information and an offset, wherein the first address information includes a page global directory address, a page upper directory address, and a page intermediate directory address;

[0041] an objective function selection module, configured to perform address query processing on the first address information through the address index model to obtain a query result, and select an objective function from the regression function according to the query result;

[0042] A prediction module, used for acquiring the first address information according to the target function to obtain a predicted page table entry address;

[0043] A second address calculation module is used to perform address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain a second address information;

[0044] A physical address calculation module is used to perform address offset based on the second address information and the offset to obtain the physical address of the page table virtual address.

[0045] To achieve the above objectives, a third aspect of an embodiment of the present application proposes an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the method described in the first aspect is implemented.

[0046] To achieve the above-mentioned purpose, the fourth aspect of an embodiment of the present application proposes a storage medium, which is a computer-readable storage medium, and the storage medium stores a computer program. When the computer program is executed by a processor, the method described in the first aspect is implemented.

[0047] The page table virtual address conversion method, device, equipment and storage medium proposed in the embodiments of the present application, wherein the page table virtual address conversion method obtains the page table virtual address, wherein the page table virtual address includes: first address information and offset, and then the first address information is input into the address index model to perform the address query process, and the regression function is selected from the tree structure as the target function, and the predicted page table item address of the first address information is calculated according to the target function, and then the second address information is calculated according to the first address information and the predicted page table item address; and then the address is offset based on the second address information and the offset to obtain the physical address of the page table virtual address. The embodiments of the present application use the address index model to predict the page table item address corresponding to the first address information, without the need to search level by level according to the number of levels of the page table, which can reduce the delay in searching the page table item address and accelerate the conversion efficiency of the virtual address to the physical address. Thereby optimizing cloud storage and improving the data processing efficiency of financial institutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 The present invention provides a flowchart of a method for converting a page table virtual address.

[0049] Figure 2a It is a schematic diagram of a multi-level page table structure in the related art.

[0050] Figure 2b It is a schematic diagram of the principle of the page table virtual address conversion method provided by an embodiment of the present invention.

[0051] Figure 3 It is a structural schematic diagram of an address index model of a page table virtual address conversion method provided by another embodiment of the present invention.

[0052] Figure 4 It is a flowchart of constructing and training an address index model of a page table virtual address conversion method provided by another embodiment of the present invention.

[0053] Figure 5 yes Figure 4 Flowchart of step S430 in .

[0054] Figure 6It is a schematic diagram of a linear function of a root node in an address index model of a page table virtual address conversion method provided by another embodiment of the present invention.

[0055] Figure 7 It is a flow chart of the end conditions of the original node differentiation step of the page table virtual address conversion method provided by another embodiment of the present invention.

[0056] Figure 8 yes Figure 1 Flowchart of step S120 in .

[0057] Fig. 9 yes Figure 8 Flowchart of step S1220 in .

[0058] Fig.10 yes Figure 1 Flowchart of step S130 in .

[0059] Fig.11 It is a structural schematic diagram of an address index model of a page table virtual address conversion method provided by another embodiment of the present invention.

[0060] Fig.12 yes Fig.11 Schematic diagram of a linear function of the original node in the address index model.

[0061] Fig.13 It is a flow chart of a page table virtual address conversion method provided by another embodiment of the present invention.

[0062] Fig.14 It is a structural block diagram of a page table virtual address conversion device provided by another embodiment of the present invention.

[0063] Fig.15 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0065] It should be noted that although the functional modules are divided in the device schematic and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0067] First, several nouns involved in the present invention are analyzed:

[0068] Artificial intelligence (AI) is a new technical science that studies and develops theories, methods, technologies and application systems for simulating, extending and expanding human intelligence. AI is a branch of computer science that attempts to understand the essence of intelligence and produce a new type of intelligent machine that can respond in a similar way to human intelligence. Research in this field includes robotics, speech recognition, image recognition, natural language processing and expert systems. AI can simulate the information process of human consciousness and thinking. AI is also a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0069] Physical Address: Information is stored in bytes in memory. To store or retrieve information correctly, each byte unit is given a unique memory address, called a physical address, also called an actual address or an absolute address. Physical addresses are numbered starting from 0 and are incremented by 1 sequentially, so the physical address space of the memory grows linearly. The physical address is represented by a binary number, an unsigned integer, written in hexadecimal format, and is the address signal for addressing physical memory that appears on the CPU's external address bus. The physical address exists in electronic form on the address bus, allowing the data bus to access the memory address of a specific storage unit in the main memory.

[0070] Virtual Address: The main memory of a computer system is mostly composed of semiconductor memory. Due to process and cost reasons, the capacity of the main memory is subject to certain restrictions. However, the functions of computer system software and application software are constantly enhanced, the program scale is rapidly expanding, and the demand for main memory capacity is increasing. In order to provide convenience for large programs and free them from the limitation of main memory capacity, the operating system manages the two-level storage systems of main memory and auxiliary memory to achieve automatic overwriting. For example, when a process is executed, part of its address space is in the main memory and the other part is in the auxiliary memory. When the accessed information is not in the main memory, the operating system arranges I / O instructions to transfer the information from the auxiliary memory to the main memory. In effect, it seems that a memory with a storage capacity much larger than the actual main memory is provided. The user does not need to consider whether the compiled program can be placed in the main memory or where to place it. This kind of memory is called virtual memory. When the program is running, the CPU accesses the main memory with a virtual address, and the auxiliary hardware finds the correspondence between the virtual address and the actual address, and determines whether the content of the storage unit indicated by this virtual address has been loaded into the main memory. If it is already in the main memory, the CPU can directly access the actual unit of the main memory through address conversion; if it is not in the main memory, a storage block containing this word is loaded into the main memory and then accessed by the CPU. If the main memory is full, the replacement algorithm will load a temporarily unused block from the main memory back to the external memory, and then load a new block from the external memory to the main memory.

[0071] As the amount of data in the financial industry continues to grow, financial institutions need to carry more data, which makes cloud storage increasingly important as a way of information management. By using cloud storage technology, financial institutions can store large amounts of data in the cloud at a low cost, while allowing users to access and process data anytime and anywhere. Cloud storage technology allocates virtual memory to each process through the operating system. When a certain space is used, the data is stored in the real physical memory through address conversion. Since the physical address is the real physical memory access address, when allocating memory to the process, the virtual address needs to be mapped to the physical address. The conversion between virtual addresses and physical addresses is achieved through the paging mechanism. In cloud storage, page table virtual address conversion is usually used for file retrieval and access. The operating system allocates virtual memory to each process. Since the physical address is the real physical memory access address, when allocating memory to the process, the virtual address needs to be mapped to the physical address. When a certain space is used, the data is stored in the real physical memory through address conversion. The conversion between virtual addresses and physical addresses is achieved through the paging mechanism.

[0072] In the related art, the operating system uses a multi-level page table to search for page table entries. When searching, it first searches from each level of the page table one by one until the address of the page table entry is located, and then finds the final physical address through the page offset. This page search method is time-consuming, resulting in a low efficiency in the virtual address translation process, and is not suitable for scenarios that require fast access to processes.

[0073] Based on this, an embodiment of the present invention provides a page table virtual address conversion method, device, equipment and storage medium, which uses an address index model to predict the page table entry address corresponding to the first address information, without the need to search level by level according to the number of page tables. It can reduce the delay in searching the page table entry address and accelerate the conversion efficiency of the virtual address to the physical address.

[0074] The embodiments of the present invention provide a page table virtual address conversion method, apparatus, device and storage medium, which are specifically described through the following embodiments. First, the page table virtual address conversion method in the embodiments of the present invention is described.

[0075] The embodiments of the present invention can acquire and process relevant data based on artificial intelligence technology. Among them, artificial intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines so that the machines have the functions of perception, reasoning and decision-making.

[0076] Artificial intelligence technology is a comprehensive discipline that covers a wide range of fields, including both hardware-level and software-level technologies. The basic technologies of artificial intelligence generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, mechatronics and other technologies. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0077] The page table virtual address conversion method provided by the embodiment of the present invention relates to the field of artificial intelligence technology, and in particular to the field of data mining technology. The page table virtual address conversion method provided by the embodiment of the present invention can be applied to a terminal, can also be applied to a server side, and can also be a computer program running in a terminal or a server side. For example, the computer program can be a native program or software module in an operating system; it can be a local (Native) application (APP, Application), that is, a program that needs to be installed in the operating system to run, such as a client that supports page table virtual address conversion, or it can be a small program, that is, a program that can be run only by downloading it to a browser environment; it can also be a small program that can be embedded in any APP. In short, the above-mentioned computer program can be an application, module or plug-in in any form. Among them, the terminal communicates with the server through a network. The page table virtual address conversion method can be executed by a terminal or a server, or by a terminal and a server in collaboration.

[0078] In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer or a smart watch. The server can be an independent server, or it can be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms; it can also be a service original node in a blockchain system, and each service original node in the blockchain system forms a peer-to-peer (P2P, Peer To Peer) network. The P2P protocol is an application layer protocol running on the transmission control protocol (TCP, Transmission Control Protocol) protocol. The server can be installed with a server end of a page table virtual address conversion system, through which the server end can interact with the terminal, for example, the corresponding software is installed on the server end, and the software can be an application that implements a page table virtual address conversion method, etc., but is not limited to the above form. The terminal and the server can be connected through communication connection methods such as Bluetooth, USB (Universal Serial Bus) or network, and this embodiment is not limited here.

[0079] The present invention can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present invention can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present invention can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0080] It should be noted that in each specific implementation of the present application, when it comes to the need to perform relevant processing based on data related to user identity or characteristics such as user information, user behavior data, user historical data, and user location information, the user's permission or consent will be obtained first, and the collection, use, and processing of these data will comply with the relevant laws, regulations, and standards of the relevant countries and regions. In addition, when the embodiment of the present application needs to obtain the user's sensitive personal information, the user's separate permission or consent will be obtained through a pop-up window or by jumping to a confirmation page. After clearly obtaining the user's separate permission or consent, the necessary user-related data for the normal operation of the embodiment of the present application will be obtained.

[0081] In cloud storage, page table virtual address conversion is usually used for file retrieval and access. Most cloud storage service providers use virtualization technology to manage storage resources and use page table virtual address conversion to map stored data to the virtual address space of user programs. The embodiment of the present application can be used in cloud storage service optimization scenarios for financial cloud computing. For example, the storage method of financial data adopts the mode of nearline storage (Nearline Storage), which can achieve fast, low-cost, and highly reliable storage of infrequently accessed data backups and archives. These backup and archive data can be accessed and managed by the page table virtual address conversion method of the embodiment of the present application. When the user needs to restore data, the cloud storage service uses the page table virtual address conversion to map the physical address of the backup and archive data to the virtual address of the user program. In addition, the cloud storage service can also use a distributed database management system (DBMS) combined with page table virtual address conversion to achieve efficient data retrieval and storage. In this way, even if the data accessed by the user is stored in different physical locations, it can be regarded as a continuous memory space through virtual address conversion, which is convenient for retrieval and call. By using cloud storage technology, financial institutions can store a large amount of data in the cloud at a low cost, while allowing users to access and process data anytime and anywhere. Cloud storage optimization can also improve the efficiency of data processing by financial institutions. Cloud storage platforms are usually highly available, scalable, and powerful, and can support multiple users to access and process data simultaneously. At the same time, cloud storage platforms are also equipped with data analysis tools and machine learning algorithms to accelerate the data analysis and decision-making process of financial institutions.

[0082] The following describes a page table virtual address conversion method in an embodiment of the present invention.

[0083] Figure 1 is an optional flow chart of a page table virtual address conversion method provided by an embodiment of the present invention. Figure 1 The method in the embodiment may include but is not limited to steps S110 to S150. Figure 1 The order of step S110 to step S150 is not specifically limited, and the order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0084] Step S110: Obtain the page table virtual address.

[0085] In one embodiment, referring to Figure 2a , which is a schematic diagram of a multi-level page table structure in the related art.

[0086] In this embodiment, the multi-level page table structure is a four-level mapped page table structure. For a virtual address, its address structure includes five parts, namely, a global directory address, an upper directory address, an intermediate directory address, a table address and an offset. Figure 2a There are 5 page table directories in the system, namely Page Global Directory (PGD), Page Upper Directory (PUD), Page Middle Directory (PMD), Page Table Entry (PTE) and Physical Page Frame (Page).

[0087] For x86 64-bit systems, virtual addresses can be represented by 48-bit binary numbers. The size of each page table directory in the page table structure is 4kb. The address of the next level page table is stored in the page table directory. Since the number of bytes in the 64-bit system byte addressing is 64 bits, and 64 bits is 8b, 4kb / 8b=2 9 , that is to say, each page table has 2 9 entries, so the index of the page table is set to 9 bits. Due to the four-level mapping structure, 4*9=36 bits are needed for indexing. The upper 36 bits of the virtual address are used to store the page table directory, of which the global directory, parent directory, intermediate directory and table all occupy 9 bits. The lower 12 bits of the virtual address represent the offset. The physical address of the virtual address can be obtained through the page table information and the offset.

[0088] When converting a virtual address to a physical address, first obtain the PGD base address from the Cr3 register, and then find the page table where the PGD is located based on the PGD base address and the global directory address in the virtual address; then obtain the PUD base address in the PGD page table, and then find the page table where the PUD is located based on the PUD base address and the upper directory address in the virtual address; then obtain the PMD base address in the PUD page table, and then find the page table where the PMD is located based on the PMD base address and the intermediate directory address in the virtual address; then obtain the PTE base address in the PMD page table, and then find the page table where the PTE is located based on the PTE base address and the table address in the virtual address; then obtain the Page base address in the PTE page table, and then find the physical address based on the Page base address and the offset in the virtual address.

[0089] It can be seen that the method of searching the page table directory level by level is time-consuming, so refer to Figure 2b In the embodiment of the present application, the first address information composed of the global directory address + the upper directory address + the intermediate directory address is used to predict the page table of the PTE through the address index model to improve the conversion efficiency of the virtual address to the physical address. In one embodiment, the address index model is a pre-built and trained learning index model, which is constructed according to the recursive model index.

[0090] In one embodiment, referring to Figure 3 , which is a structural diagram of the address index model in the embodiment of the present application. In this embodiment, the address index model is a tree structure, including multiple original nodes, and the original nodes are divided into two categories, one is the parent node, and the other is the child node of the parent node. Among them, the root node located at the bottom of the tree structure belongs to a type of parent node, and the leaf node located at the outermost layer of the tree structure belongs to a type of child node. In this embodiment, each original node in the tree structure is a regression function, for example, it can be a linear function, and the linear function can be expressed as: y=f(x)=ax+b, where a and b are constants, and the linear function can obtain a determined output based on the input. In this embodiment, the parameters of the regression function of the original nodes at different positions may be the same or different. In this embodiment, the parameters of the regression function are determined through a training process.

[0091] The following describes the construction and training process of the address index model of the embodiment of the present application. Figure 4 , a flowchart for building and training an address index model, including the following steps:

[0092] Step S410: construct multiple training address information.

[0093] In one embodiment, each training address information and its corresponding page table tag constitute a training sample, and multiple training samples constitute a training sample set. This embodiment intends to predict the address information of the corresponding PTE through the address information of PGD, PUD and PMD, so the training address information is a 27-bit address data composed of the page global directory address, the page upper directory address and the page middle directory address. The page table tag of each training address information is its corresponding 9-bit PTE page table entry address, which is called the destination page table entry address. It can be understood that, assuming that there are M training samples, the training samples are represented as: [27-bit address information, page table tag], then the training sample set can be represented as {[27-bit address information 1, page table tag 1], [27-bit address information 2, page table tag 2], ..., [27-bit address information M, page table tag M]}, where M is an integer greater than 1.

[0094] Step S420: sort the training address information to obtain a first address value and a second address value, and generate a first input range based on the first address value and the second address value, and sort the destination page table entry address to obtain a first page table entry address and a second page table entry address, and generate a first output range based on the first page table entry address and the second page table entry address.

[0095] In one embodiment, all training samples in the training sample set are analyzed, and each training sample can be understood as a one-to-one relationship between training address information and page table labels, and both training address information and page table labels can be represented as numerical values. Therefore, the training address information in all training samples is sorted by size, and the maximum and minimum values ​​of the training address information can be obtained. The maximum value is used as the second address value, and the minimum value is used as the first address value. A first input range is generated based on the first address value and the second address value. The first input range is represented as: [first address value, second address value]. Similarly, the destination page table entry addresses in all training samples are sorted by size, and the maximum and minimum values ​​of the destination page table entry addresses are obtained. The maximum value is used as the second page table entry address, and the minimum value is used as the first page table entry address. A first output range is generated based on the first page table entry address and the second page table entry address. The first output range is represented as: [first page table entry address, second page table entry address].

[0096] The address index model of this embodiment is composed of multiple linear linear functions. The purpose of address sorting is to make the input range of all linear functions cover the first input range. Similarly, the output range of all linear functions can cover the first output range. In this way, it can be ensured that each training sample has a corresponding linear function, and the training address information in the training sample is input into the linear function to obtain the output value that is the same as the destination page table entry address or the closest to the error requirement.

[0097] Step S430: Execute the original node differentiation step to construct an address index model.

[0098] In one embodiment, referring to Figure 5 , the original node differentiation step includes the following steps:

[0099] Step S431: Generate an input data range and an output data range for training the parent node, and generate a regression function for training the parent node by fitting the input data range and the output data range.

[0100] In one embodiment, when constructing the tree structure of the address index model, the levels of the tree structure and the number of original nodes in each layer are unknown, and this information is obtained through calculations on training samples. When constructing, child nodes are constructed one by one starting from the parent node, and then the child nodes are used as parent nodes to construct corresponding child nodes until the end condition is reached. This is the training process, and the parent node of the training process is called the training parent node, and the child node is called the training child node. Since the tree structure starts from the root node to the child node, the initial value of the training parent node is the root node, that is, when constructing the address index model in this embodiment, a root node is first constructed, and the root node here is a linear function. Refer to Figure 6, the root node is a fitted linear function, whose input data range and output data range have the same number of values ​​and one-to-one correspondence, that is, each input value in the input data range corresponds to an output value in the output data range, and the input value and the output value form a coordinate pair (illustrated in the form of scattered points in the figure), each coordinate pair corresponds to a training sample, the horizontal coordinate of the coordinate pair is the 27-bit address information of the training sample, and the vertical coordinate is the page table label of the training sample, and then all the coordinate pairs in the data range are fitted to obtain a linear function, which constitutes the root node. The parameters of the corresponding linear function f(x) only need to satisfy that its input data range can cover the first input range and its output data range can cover the first output range. The coverage here means that the upper limit a2 of the input data range of the root node is greater than or equal to the second address value b2, the lower limit a1 of the input data range is less than or equal to the first address value b1, the upper limit c2 of the output data range of the root node is greater than or equal to the second page table entry address d2, and the lower limit c1 of the input data range is less than or equal to the first page table entry address c1.

[0101] Step S432: Divide the input data range of the training parent node into a plurality of sub-input ranges according to the number of training child nodes, and divide the output data range into sub-output ranges corresponding to the sub-input ranges.

[0102] Step S433: Generate a regression function for training the sub-node by fitting according to the sub-input range and the sub-output range.

[0103] In one embodiment, the input data range of the training parent node is divided into a first number of input sub-ranges, and the output data range of the training parent node is divided into a first number of output sub-ranges that is consistent with the number of input sub-ranges. The input sub-ranges and the output sub-ranges are matched one by one in order to obtain the first number of child node ranges, and a linear function is generated for each child node range. With reference to the root node, the input data range of the linear function is the input sub-range, and the output data range is the output sub-range, which is obtained by fitting multiple coordinate pairs consisting of different training samples. It can be understood that the parameters of the first number and the linear function of each child node range are adjusted according to the training samples.

[0104] In the above embodiment, the input data ranges of the first number of training child nodes constitute the input data range of the training parent node, and the output data ranges of the first number of training child nodes constitute the output data range of the training parent node, wherein the first number is an integer greater than or equal to 1.

[0105] It can be understood that since the values ​​in the input data range and the output data range can be mapped one-to-one to coordinate points, whether it is training a parent node or a child node, its linear function is a function obtained by fitting the coordinate points within its input data range, and the fitting function is used to cover the corresponding data range.

[0106] Step S434: Use the training child node as the training parent node for the next original node differentiation step, and repeat the original node differentiation step until each training address information corresponds to a leaf node as the target training node, thereby obtaining an address index model.

[0107] In one embodiment, each training child node is used as the training parent node of the next original node differentiation step, and the original node differentiation step is repeated multiple times. The termination condition of the original node differentiation step is that each training sample can have a leaf node as its target training node, that is, if each training sample can correspond to a leaf node, the generated tree structure is the address index model of the embodiment of the present application.

[0108] In one embodiment, referring to Figure 7 , the end condition of the above original node differentiation step can be divided into the following judgment steps:

[0109] Step S710: Obtain the training page table entry address corresponding to the training address information in the regression function of the leaf node.

[0110] Step S720: Calculate the loss value between the training page table entry address and the destination page table entry address.

[0111] Step S730: If the loss value is less than the preset threshold, the leaf node is determined to be a target training node.

[0112] In one embodiment, after each original node differentiation step is executed, a corresponding target training node is selected for each training sample in the current leaf node. The selection process is to input the training address information of the training sample into the leaf node. Since the leaf node is also a linear function, the training address information is used as an independent variable to obtain the dependent variable of the linear function. This dependent variable is used as the training page table item address, and then the similarity between the training page table item address and the destination page table item address is compared. The similarity is expressed by calculating the loss value of the training page table item address and the destination page table item address. If the two are closer, the loss value will be less than the preset threshold value. At this time, the leaf node can be judged as the target training node. If there is a situation where the target training node cannot be found, the parameters of the linear function of all the original nodes in the currently constructed tree structure are adjusted, or the original node structure in the currently constructed tree structure is adjusted, or the original node differentiation step is continued to generate a new training child node. The selection of these measures is not limited in this embodiment, and can be determined by the model according to the training situation. It can be understood that if the corresponding target training node can be found for each training sample, it means that the training process is over and the address index model is constructed.

[0113] In one embodiment, the training of the address index model may be a time-consuming task. In order to improve the learning efficiency, the following improvements are made: First, the structure of the address index model is fixed for the same processor, which means that only the parameters of the specific original node need to be determined when the program is running. Second, server applications usually run for a long time and their memory usage is also stable; therefore, the training time can be amortized over the life cycle of the application. For example, a daemon thread is written in the program to check the CPU usage of the program regularly (for example, 2 minutes). If the CPU usage is very small, the training of the address index model is triggered; or the address index model can be directly trained regularly without judging the CPU load. The method for triggering training here can be selected according to actual needs. In addition, the training does not need to be performed immediately when the application is started; instead, it can be performed as a background task or when the load on the server is idle. Before the address index model is trained, the traditional multi-level page table lookup can be used to solve the problem of missing page table entries. In addition, large memory applications often allocate memory at startup and then manage it internally; therefore, the frequency of retraining the address index model is very low.

[0114] The address index model in the embodiment of the present application can be obtained through the above process. The following describes how to use the address index model to perform page table virtual address conversion.

[0115] In one embodiment, the page table virtual address that needs to be converted includes: first address information and an offset, wherein the first address information includes a page global directory address, a page upper directory address, and a page intermediate directory address.

[0116] Step S120: performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result.

[0117] In one embodiment, referring to Figure 8 , performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result includes the following steps:

[0118] Step S1210: Obtain the target node according to the root node.

[0119] In one embodiment, the target node includes child nodes, and the initial value of the target node is a root node.

[0120] Step S1220: Filter out query nodes from the child nodes according to the first address information.

[0121] In one embodiment, the initial value of the target node is the root node, and all child nodes of the target node are used as candidate nodes. For example, when querying for the first time, the query starts from the root node, all child nodes of the root node are determined as candidate nodes, and then a query node is selected from the candidate nodes.

[0122] In one embodiment, referring to Fig. 9 , filtering out query nodes from child nodes according to the first address information comprises the following steps:

[0123] Step S1221: Obtain the input data range of each child node to obtain the target data range.

[0124] In one embodiment, according to the construction process of the address index model in the above embodiment, the input data ranges of all candidate nodes can constitute the input data range of the corresponding target node, and the input data range of the candidate node is obtained by dividing the input data range of the target node. The input data range of each candidate node is called the target data range.

[0125] Step S1222: If the first address information is found within the target data range, the child node is used as the query node.

[0126] In one embodiment, if the target data range of the candidate node includes the first address information, it indicates that the predicted page table entry address corresponding to the page table virtual address can be obtained through the relevant child nodes of the candidate node.

[0127] Step S1230: Determine whether the query node is a leaf node; if the query node is not a leaf node, take the query node as the target node and repeat the address query process until the query node is a leaf node.

[0128] Step S1240: Obtain the regression function of the leaf node as the objective function.

[0129] In one embodiment, if it is found that the query node is a leaf node, the linear function of the query node is used as the target function. If the query node is not a leaf node, it means that the query node also has its corresponding child node as a parent node, and its input data range is composed of the input data ranges of all its child nodes. It is necessary to further select the original node that can match the first address information from its child nodes.

[0130] Step S130: acquiring the first address information according to the target function to obtain a predicted page table entry address.

[0131] In one embodiment, after obtaining the target function, the predicted page table entry address can be calculated according to the target function. Fig.10 , acquiring the first address information according to the target function to obtain the predicted page table entry address includes the following steps:

[0132] Step S1010: obtaining multiple address prediction values ​​according to the output data range of the objective function.

[0133] In one embodiment, since the objective function is a linear function and a linear function is a continuous function, when the input data of the objective function is a numerical range, its output data is also a numerical range, and the page table entry address cannot be a decimal, it is an integer, so each integer value in the numerical range of the output data is obtained, and the integer value is used as a series of address prediction values.

[0134] Step S1020: Obtain the output address corresponding to the first address information in the target function.

[0135] In one embodiment, the first address information is input into the target function for calculation to obtain a corresponding output value.

[0136] Step S1030: Subtract the address prediction value from the output address to obtain an address difference value.

[0137] Step S1040: selecting the address prediction value corresponding to the minimum value of the address difference as the predicted page table entry address.

[0138] In one embodiment, since the idea of ​​this embodiment is to use a linear function to fit the relationship between the first address information and the predicted page table entry address, but the fitting function cannot guarantee that the output value of each first address information is exactly the predicted page table entry address, that is, the fitting function only represents the general trend of the data points, and cannot guarantee that each point is on the fitting function. Therefore, after obtaining the fitting function of the leaf node, this embodiment calculates the output value corresponding to the first address information according to the fitting function, and the output value may be a decimal. Then, the output value is compared with a series of address prediction values ​​obtained in the above steps, and the address prediction value closest to the output value is selected as the predicted page table entry address. The closest means that the difference between the two is the smallest.

[0139] The following is an explanation using a specific example.

[0140] In one embodiment, referring to Fig.11 , assuming that the tree structure of the address index model contains 4 layers, the first layer is the root node, its linear function is expressed as F(x), the root node contains 6 child nodes, and its linear functions are: F 1 (x), F 2 (x), F 3 (x), F 4 (x), F 5 (x) and F 6 (x), each child node as a parent node contains multiple child nodes (not all original nodes are shown in the figure), among which the child node F 1 (x) contains two child nodes, namely: F 11 (x) and F 12 (x), child node F 6 (x) contains two child nodes, namely F 61 (x), … and F 62 (x), child node F 11 (x) contains two child nodes, namely: F 111 (x) and F 112 (x).

[0141] Reference Fig.11 , assuming that in one embodiment, for the first address information x, the process of selecting a query node during the address query process is as follows:

[0142] The first address query process:

[0143] The root node F(x) is used as the target node, and the query node selected from its candidate nodes is F 1 (x), due to F 1 (x) is not a leaf node, so the second address query process is performed.

[0144] The second address query process:

[0145] Original node F 1 (x) is the target node, and the query node selected from its candidate nodes is F 11 (x), due to F 11 (x) is not a leaf node, so the third address query process is performed.

[0146] The third address query process:

[0147] Original node F 11 (x) is the target node, and the query node selected from its candidate nodes is F 111 (x), due to F 111 (x) is a leaf node, so the address query process ends and F 111 A linear function of (x) is used as the objective function of the first address information.

[0148] Then input the first address data x into F 111 (x) to get the output value y', in F 111 The address prediction value y closest to the output value y' is selected from the multiple address prediction values ​​of (x), and the address prediction value y is used as the predicted page table entry address.

[0149] Fig.12 for Fig.11 Schematic diagram of the linear function of each original node in .

[0150] Reference Fig.12 , the linear function of each original node is a monotonically increasing function. The input data range of F(x) is [A1, A2], the output data range is [B1, B2], and the first address data is located at [A1, A2].

[0151] The input data range [A1, A2] and output data range [B1, B2] of F(x) are split to obtain the child nodes of F(x). The data ranges are:

[0152] F 1 The input data range of (x) is [A1,A11], and the output data range is [B1,B11];

[0153] F 2 The input data range of (x) is [A11, A12], and the output data range is [B11, B12];

[0154] F 3 The input data range of (x) is [A12, A13], and the output data range is [B12, B13];

[0155] F 4The input data range of (x) is [A13, A14], and the output data range is [B13, B14];

[0156] F 5 The input data range of (x) is [A14, A15], and the output data range is [B14, B15];

[0157] F 6 The input data range of (x) is [A15,A2], and the output data range is [B15,B2];

[0158] The first address query process finds that the first address data is located at [A1, A11], F 1 (x) is the query node, and F 1 (x) is not a leaf node, so continue to query F 1 (x) is a child node of

[0159] F 1 The input data range [A1, A11] and output data range [B1, B11] of (x) are split to obtain F 1 The child nodes of (x) have the following data ranges:

[0160] F 11 The input data range of (x) is [A1,C1], and the output data range is [B1,D1];

[0161] F 12 The input data range of (x) is [C1,A11], and the output data range is [D1,B11];

[0162] The second address query process finds that the first address data is located at [A1, C1], F 11 (x) is the query node, and F 11 (x) is not a leaf node, so continue to query F 11 (x) is a child node of

[0163] F 11 The input data range [A1, C1] and output data range [B1, D1] of (x) are split to obtain F 11 The child nodes of (x) have the following data ranges:

[0164] F 111 The input data range of (x) is [A1,C11], and the output data range is [B1,D11];

[0165] F 112 The input data range of (x) is [C11, C1], and the output data range is [D11, D1];

[0166] The third address query process finds that the first address data is located at [A1, C11], F 111 (x) is the query node, and F 111 (x) is a leaf node, so F 111 (x) is used as the objective function.

[0167] Then input the first address data x into F 111 (x) to get the output value y', in F 111 The address prediction value y closest to the output value y' is selected from the multiple address prediction values ​​of (x), and the address prediction value y is used as the predicted page table entry address.

[0168] It can be seen from the above steps that the embodiment of the present application predicts the first address information through the address index model to obtain the predicted page table entry address.

[0169] Step S140: performing address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain second address information.

[0170] Step S150: performing address offset based on the second address information and the offset to obtain the physical address of the page table virtual address.

[0171] In one embodiment, in combination Figure 2a , the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address are combined to obtain the second address information in the PTE page, and then the final physical address is located according to the 12-bit offset.

[0172] The page table virtual address translation method based on the address index model in the embodiment of the present application can bypass the search of all levels except the last level in the multi-level page table, effectively accelerate the virtual address translation in the operating system, and use the address index model to replace the page table search, thereby greatly reducing the delay of the search page. For programs that require large memory capacity, it can effectively speed up their running speed.

[0173] In one embodiment, considering that there may be errors in the prediction, before using the predicted page table entry address for address conversion, it is necessary to perform a validity check on the predicted page table address, referring to Fig.13 , the specific verification process includes the following steps:

[0174] Step S1310: Obtain the flag bit of the predicted page table entry address.

[0175] Step S1310: Use the flag bit to perform a validity check on the predicted page table entry address. If the flag bit indicates that the predicted page table entry address exists in the physical memory, the validity check passes.

[0176] In one embodiment, the validity check process is performed by the operating system kernel. There are some flags in each page table entry information, which indicate whether this virtual page exists in the physical memory. If the page table entry flag indicates that this virtual page is invalid, the operating system will report a page error. If it exists, the validity check passes, and the predicted page table entry address can be used to convert the virtual address to the physical address. At the same time, the operating system will perform an address check on the final physical address to check whether the physical address is valid and legal to ensure that the physical page is accessible and the operating system has the authority to access the page. If the physical address is invalid or invalid, the operating system will report an access error.

[0177] In the above embodiment, the operating system is used to check whether the page table index is valid, whether the page table entry is valid, and whether the physical address is valid and legal. These steps help the operating system to ensure that the virtual page is accessed correctly and protect the system from illegal access and errors, and also bring robustness to the page table virtual address conversion method based on the address index model for memory management optimization in the embodiment of the present application.

[0178] The technical solution provided by the embodiment of the present invention obtains the page table virtual address, wherein the page table virtual address includes: first address information and an offset, and then the first address information is input into the address index model to perform the address query process, a regression function is selected from the tree structure as the target function, and the predicted page table item address of the first address information is calculated according to the target function, and then the second address information is calculated according to the first address information and the predicted page table item address; and then the address is offset based on the second address information and the offset to obtain the physical address of the page table virtual address. The embodiment of the present application uses the address index model to predict the page table item address corresponding to the first address information, without searching level by level according to the number of levels of the page table, which can reduce the delay of searching the page table item address and accelerate the conversion efficiency of the virtual address to the physical address.

[0179] The embodiment of the present invention also provides a page table virtual address conversion device, which can implement the above-mentioned page table virtual address conversion method, referring to Fig.14 , applied to an address index model, the address index model is a tree structure, the tree structure includes at least one original node, and the original node is a regression function; the device includes:

[0180] The page table virtual address acquisition module 1410 is used to acquire the page table virtual address, wherein the page table virtual address includes: first address information and an offset, wherein the first address information includes a page global directory address, a page upper directory address, and a page intermediate directory address.

[0181] The target function selection module 1420 is used to perform address query processing on the first address information through the address index model to obtain a query result, and filter out a target function from the regression function according to the query result.

[0182] The prediction module 1430 is used to obtain the address of the first address information according to the target function to obtain the predicted page table entry address.

[0183] The second address calculation module 1440 is used to perform address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain second address information.

[0184] The physical address calculation module 1450 is used to perform address offset based on the second address information and the offset to obtain the physical address of the page table virtual address.

[0185] The specific implementation of the page table virtual address conversion device of this embodiment is basically consistent with the specific implementation of the page table virtual address conversion method described above, and will not be repeated here.

[0186] An embodiment of the present invention further provides an electronic device, including:

[0187] at least one memory;

[0188] at least one processor;

[0189] at least one program;

[0190] The program is stored in the memory, and the processor executes the at least one program to implement the page table virtual address conversion method of the present invention. The electronic device can be any intelligent terminal including a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc.

[0191] See also Fig.15 , Fig.15 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0192] The processor 1501 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention;

[0193] The memory 1502 can be implemented in the form of ROM (Read Only Memory), static storage device, dynamic storage device or RAM (Random Access Memory). The memory 1502 can store operating systems and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1502, and the processor 1501 calls and executes the page table virtual address conversion method of the embodiment of the present invention;

[0194] Input / output interface 1503, used to implement information input and output;

[0195] Communication interface 1504, used to realize communication interaction between the device and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.); and

[0196] A bus 1505 that transmits information between the various components of the device (e.g., the processor 1501, the memory 1502, the input / output interface 1503, and the communication interface 1504);

[0197] The processor 1501 , the memory 1502 , the input / output interface 1503 and the communication interface 1504 are connected to each other in communication within the device via the bus 1505 .

[0198] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned page table virtual address conversion method is implemented.

[0199] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0200] The page table virtual address conversion method, page table virtual address conversion device, electronic device, and storage medium proposed in the embodiments of the present invention have a technical solution and beneficial effects.

[0201] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0202] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0203] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0204] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0205] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0206] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0207] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0208] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0209] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0210] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0211] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A page table virtual address translation method, characterized in that: Applied to an address index model, the address index model is a tree structure, the address index model includes at least one original node, and the original node is a regression function; the method includes: Obtaining a page table virtual address, the page table virtual address comprising: first address information and an offset, the first address information comprising a page global directory address, a page upper directory address, and a page intermediate directory address; Performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result; Acquire the first address information according to the target function to obtain a predicted page table entry address; Performing address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain second address information; An address offset is performed based on the second address information and the offset to obtain a physical address of the page table virtual address.

2. The page table virtual address conversion method according to claim 1, characterized in that: The original node includes a parent node and a child node, the parent node includes a root node, and the child node includes a leaf node; performing address query processing on the first address information through the address index model to obtain a query result, and filtering out a target function from the regression function according to the query result, including: Acquire a target node according to the root node; wherein the target node includes child nodes, and an initial value of the target node is the root node; Filtering a query node from the child nodes according to the first address information; Determine whether the query node is the leaf node; if the query node is not the leaf node, take the query node as the target node and repeat the address query process until the query node is a leaf node; The regression function of the leaf node is obtained as the objective function.

3. The page table virtual address conversion method according to claim 2, characterized in that: The step of filtering out a query node from the child nodes according to the first address information includes: Obtaining the input data range of each of the child nodes to obtain the target data range; If the first address information is found within the target data range, the child node is used as the query node.

4. The page table virtual address conversion method according to claim 2, characterized in that: The acquiring the first address information according to the target function to obtain a predicted page table entry address includes: Obtaining a plurality of address prediction values ​​according to an output data range of the objective function; Obtaining an output address corresponding to the first address information in the target function; Subtracting the address prediction value from the output address to obtain an address difference value; The address prediction value corresponding to the minimum value of the address difference is selected as the predicted page table entry address.

5. The page table virtual address conversion method according to claim 1, characterized in that: Before performing address query processing on the first address information by using the address index model, the method further includes: Constructing a plurality of training address information, wherein the training address information is generated according to a page global directory address, a page upper directory address, and a page intermediate directory address; Sorting the training address information to obtain a first address value and a second address value, and generating a first input range according to the first address value and the second address value, and sorting the destination page table entry address to obtain a first page table entry address and a second page table entry address, and generating a first output range according to the first page table entry address and the second page table entry address; The original node differentiation step is executed to construct the address index model, and the original node differentiation step includes: Generate an input data range and an output data range of a training parent node, and generate a regression function of the training parent node by fitting according to the input data range and the output data range; the initial value of the training parent node is a root node; the input data range of the root node includes the first input range, and the output data range of the root node includes the first output range; Dividing the input data range of the training parent node into a plurality of sub-input ranges according to the number of training child nodes, and dividing the output data range into sub-output ranges corresponding to the sub-input ranges, wherein the number of the training child nodes is a first number; the first number is an integer greater than or equal to 1; The regression function of the training child node is generated by fitting according to the sub-input range and the sub-output range; the sub-input range of the training child node constitutes the input data range of the training parent node, and the sub-output range of the training child node constitutes the output data range of the training parent node; The training child node is used as the next training parent node, and the original node differentiation step is repeated until each training address information corresponds to a leaf node as the target training node, thereby obtaining the address index model.

6. The page table virtual address conversion method according to claim 5, characterized in that: The training address information also includes a page table tag, which is a destination page table entry address of the training address information; until each of the training address information corresponds to a leaf node as a target training node, the address index model is obtained, including: Obtaining a training page table entry address corresponding to the training address information in the regression function of the leaf node; Calculating a loss value between the training page table entry address and the destination page table entry address; If the loss value is less than a preset threshold, the leaf node is determined to be the target training node.

7. The page table virtual address conversion method according to any one of claims 1 to 6, characterized in that: Before calculating the second address information according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address, the method further includes: Obtaining a flag bit of the predicted page table entry address; The predicted page table entry address is checked for validity using the flag bit. If the flag bit indicates that the predicted page table entry address exists in the physical memory, the validity check passes.

8. A page table virtual address translation device, characterized in that: include: Applied to an address index model, the address index model is a tree structure, the address index model includes at least one original node, and the original node is a regression function; The device comprises: The page table virtual address acquisition module is used to acquire the page table virtual address, and the page table virtual address includes: first address information and an offset, wherein the first address information includes a page global directory address, a page upper directory address, and a page intermediate directory address; An objective function selection module, configured to perform address query processing on the first address information through the address index model to obtain a query result, and select an objective function from the regression function according to the query result; A prediction module, used for acquiring the first address information according to the target function to obtain a predicted page table entry address; A second address calculation module, configured to perform address calculation according to the page global directory address, the page upper directory address, the page intermediate directory address and the predicted page table entry address to obtain second address information; A physical address calculation module is used to perform address offset based on the second address information and the offset to obtain the physical address of the page table virtual address.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the page table virtual address conversion method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the page table virtual address conversion method according to any one of claims 1 to 7 is implemented.

Images