Lower pole plate sampling successive approximation type analog-to-digital converter and switching method thereof

Abstract

The invention relates to a lower pole plate sampling successive approximation type analog-to-digital converter, which comprises a comparator, a DAC capacitor array and a control logic circuit, the output end of the comparator is connected to the control logic circuit, the DAC capacitor array comprises a forward capacitor array connected with the positive input end of the comparator, and the forward capacitor array is connected with the negative input end of the comparator. The reverse capacitor array is connected with the negative input end of the comparator; the invention further provides a switching method of the lower polar plate sampling successive approximation type analog-to-digital converter. The capacitor array switch energy consumption is reduced, and the capacitor array area is reduced.

Description

Technical Field

[0001] The invention relates to the field of analog-digital mixed signal integrated circuits, and in particular to a bottom plate sampling successive approximation analog-to-digital converter and a switching method thereof. Background Art

[0002] The successive approximation analog-to-digital converter has a simple structure, low power consumption and small area, and is widely used in wearable devices, CMOS image sensors and other fields with high power consumption and speed requirements. The DAC capacitor array occupies a large area and consumes a lot of energy in the successive approximation analog-to-digital converter, so it is necessary to reduce the switching energy consumption of the capacitor array, reduce the area of ​​the DAC capacitor array, reduce the chip manufacturing cost, and improve economic benefits.

[0003] The existing methods generally reduce the area of ​​the capacitor array by reducing the physical size of the capacitor unit. However, reducing the capacitance value will increase the capacitor matching error and thermal noise, thus affecting the linearity and accuracy of the ADC; or adopt improved switching circuits and charge redistribution technology to reduce the energy loss during the charging and discharging of the capacitor. However, these methods often require more complex circuit design and may still have limitations in high-resolution or high-speed applications. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a bottom plate sampling successive approximation analog-to-digital converter and a switching method thereof.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: a bottom plate sampling successive approximation analog-to-digital converter, comprising a comparator, a DAC capacitor array and a control logic circuit, wherein the output end of the comparator is connected to the control logic circuit; The DAC capacitor array includes two parts: one is a forward capacitor array connected to the positive input terminal of the comparator, the maximum capacitance of which is composed of a binary weight sub-capacitor array, called the MSB capacitor array, and the remaining capacitor array is called the LSB capacitor array; The second is a reverse capacitor array connected to the negative input terminal of the comparator, whose maximum capacitance is composed of a binary weighted sub-capacitor array, called the MSB capacitor array, and the remaining capacitor array is called the LSB capacitor array; The upper plate of the positive capacitor array is connected through the switch S P Connected to gnd, the lower plate of the MSB capacitor array in the forward capacitor array is connected to V INP 、V CM , Vaq, gnd are connected, and the lower plate of the LSB capacitor array in the forward capacitor array is connected to V CM , Vaq, gnd are connected; the upper plate of the reverse capacitor array is connected through the switch S NConnected to gnd, the lower plate of the MSB capacitor array in the reverse capacitor array is connected to V through the selection switch INN 、V CM , Vaq, gnd are connected, and the lower plate of the LSB capacitor array in the reverse capacitor array is connected to V CM , Vaq, and gnd are connected.

[0006] Furthermore, the MSB capacitor array and the LSB capacitor array of the forward capacitor array include 2 N-2 The unit capacitors are two bits less than the successive approximation analog-to-digital converter’s accuracy N bits; the MSB capacitor array and the LSB capacitor array of the reverse capacitor array contain a total of 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

[0007] Furthermore, Vaq is equal to V REF / 4.

[0008] The present invention provides a switching method for a lower plate sampling successive approximation analog-to-digital converter, which is specifically implemented as follows: Sampling phase: Positive input voltage V INP The sampling switch is turned on to connect to the lower plate of the MSB capacitor array in the positive capacitor array, the lower plate of the LSB capacitor array in the positive capacitor array is connected to gnd, and the upper plate of the positive capacitor array is connected to gnd; the negative input voltage V INN The sampling switch is turned on to connect to the lower plate of the MSB capacitor array in the reverse capacitor array, the lower plate of the LSB capacitor array in the reverse capacitor array is connected to gnd, and the upper plate of the reverse capacitor array is connected to gnd; Comparison phase: First, S P , S N Disconnect, connect the lower plate of the MSB capacitor array in the forward capacitor array and the reverse capacitor array to gnd, and keep the lower plate connection of the LSB capacitor array unchanged, start the first comparison, and get the MSB; if V INP Greater than V INN , then the lower plates of all capacitors in the forward capacitor array are connected to Vaq, and the comparator positive input voltage V DACP Increased V REF / 4, the lower plates of all capacitors in the reverse capacitor array remain connected unchanged; conversely, the lower plates of all capacitors in the reverse capacitor array are connected to Vaq, and the negative input voltage of the comparator V DACN Increased V REF / 4, the connection of the lower plates of all capacitors in the forward capacitor array remains unchanged; Then start the second comparison; if V INP Greater than (VINN + V REF / 2), the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the forward capacitor array remains unchanged, V DACP Increased V REF / 8, the lower plate connections of all capacitors in the reverse capacitor array remain unchanged; if V INP Less than or equal to (V INN +V REF / 2) and greater than V INN , then all capacitor connections in the forward capacitor array remain unchanged, the lower plate connection of the MSB capacitor array in the reverse capacitor array is switched from gnd to Vaq, and the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACN Increased V REF / 8; if V INP Greater than (V INN -V REF / 2) and less than or equal to V INN , then the lower plate connections of all capacitors in the reverse capacitor array remain unchanged, and the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACP Increased V REF / 8; if V INP Less than or equal to (V INN -V REF / 2), the connection of the bottom plates of all capacitors in the forward capacitor array remains unchanged, and the connection of the bottom plate of the MSB capacitor array in the reverse capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACN Increased V REF / 8; Then the third comparison is performed; if V INP Greater than (V INN + (3 / 4)V REF ), then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the LSB capacitor array in the forward capacitor array switches from Vaq to V CM , V DACP Increased V REF / 16, the lower plate connections of other capacitors in the forward capacitor array remain unchanged; if V INP Less than or equal to (V INN + (3 / 4)V REF ) and greater than (V INN + (1 / 2)V REF), then the lower plate voltage of the capacitor corresponding to the MSB capacitor array (i.e. the maximum capacitor) in the forward capacitor array changes from V CM Switch to Vaq, V DACP Reduced V REF / 16, the lower plate connections of other capacitors in the forward capacitor array remain unchanged; if V INP Greater than (V INN + (1 / 4)V REF ) and less than or equal to (V INN + (1 / 2)V REF ), then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the MSB capacitor array in the reverse capacitor array switches from Vaq to gnd, and the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Reduced V REF / 16, the voltage on the lower plate of the forward capacitor array remains unchanged; if V INP Less than or equal to (V INN + (1 / 4)V REF ) and is greater than V INN , then the lower plate voltage of the capacitor corresponding to the LSB capacitor array (i.e., the maximum capacitor) in the reverse capacitor array switches from gnd to Vaq, and the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V INP Greater than (V INN - (1 / 4)V REF ) and V INP Less than or equal to V INN , then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the LSB capacitor array in the forward capacitor array switches from gnd to Vaq, and the other capacitor connections in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Less than or equal to (V INN - (1 / 4)V REF ) and greater than (V INN - (1 / 2)V REF ), the lower plate voltage of the capacitor corresponding to the MSB capacitor array (i.e., the maximum capacitor) in the forward capacitor array switches from Vaq to gnd, and the other capacitor connections in the forward capacitor array remain unchanged, V DACP Reduced V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Greater than (V INN - (3 / 4)V REF ) and less than or equal to (V INN- (1 / 2)V REF ), then the lower plate of the corresponding capacitor (i.e. the maximum capacitor) in the MSB capacitor array in the reverse capacitor array changes from V CM Switch to Vaq, the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Reduced V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V INP Less than or equal to (V INN - (3 / 4)V REF ), the lower plate voltage of the LSB capacitor array corresponding to the capacitor (i.e. the maximum capacitor) in the reverse capacitor array switches from Vaq to V CM , the other capacitor bottom plates of the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; Next, the fourth comparison is performed, and the switching process is similar to the third one, until the LSB is obtained and the analog-to-digital conversion is completed. Beneficial Effects

[0009] Compared with the prior art, it has the following beneficial effects: The present invention introduces V CM , Vaq (equal to V REF / 4) and gnd three reference voltages, the DAC capacitor area is reduced by 75% compared with the traditional structure; by switching V CM And the energy-efficient unilateral switching algorithm consumes 99.51% less switching energy than the traditional structure, while the reset energy consumption is 0. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural schematic diagram of a 10-bit successive approximation analog-to-digital converter; Figure 2 The schematic diagram of the DAC capacitor array switch switching operation of the sampling phase and the first and second comparisons of a four-bit successive approximation analog-to-digital converter is shown; Figure 3 The working principle diagram of the DAC capacitor array switch switching of the third and fourth comparisons of a four-bit successive approximation analog-to-digital converter (D3=1); Figure 4 The working principle diagram of the DAC capacitor array switch switching of the third and fourth comparisons of a four-bit successive approximation analog-to-digital converter (D3=0); Figure 5 This is a MATLAB simulation result diagram of the switching power consumption changing with the output code during the conversion process of the ten-bit successive approximation analog-to-digital converter in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example

[0012] like Figure 1 As shown in the figure, taking an N-bit successive approximation analog-to-digital converter as an example, it includes a comparator, a control logic circuit and a DAC capacitor array, wherein the DAC capacitor array includes a positive capacitor array connected to the positive input of the comparator and a reverse capacitor array connected to the negative input of the comparator. The maximum capacitance is composed of a binary weighted sub-capacitor array, which is called the MSB (MostSignificant Bit) capacitor array, and the remaining capacitor array is called the LSB (Least Significant Bit) capacitor array; the maximum capacitance increases exponentially with the increase of the accuracy of the analog-to-digital converter, which is 2 N-4 C, such as Figure 1 When N=10, the maximum capacitance is 64C. For simplicity, a 4-bit successive approximation analog-to-digital converter is used as an example. The switching method of the converter is:

[0013] Sampling stage like Figure 2 As shown in (a), the sampling switch is turned on and the input signal V INP 、V INN The MSB capacitor array lower plates in the forward capacitor array and the reverse capacitor array are sampled respectively, and at the same time, the LSB capacitor array lower plates in the forward capacitor array and the reverse capacitor array are connected to gnd; all the capacitor upper plates in the forward capacitor array and the reverse capacitor array are connected to gnd; Comparison Phase After sampling, the upper plate switch S P , S N When it is turned on, the lower plate of the MSB capacitor array in the forward capacitor array and the reverse capacitor array is disconnected from the input signal and switched to gnd. The switching energy consumed in this process is 0, as shown in Figure 2 (b) Start the first comparison, if V INP -V INN is greater than 0, the output digital code D3 is 1; if V INP -V INN If it is less than or equal to 0, the output digital code D3 is 0; like Figure 2As shown in (c), if D3 is 1, all lower plates in the forward capacitor array switch from gnd to V aq , the reverse capacitor array remains unchanged, and the switching energy consumed in this process is 0; if V INP -V INN If it is less than or equal to 0, the output digital code D3 is 0, and at the same time, all the lower plates in the reverse capacitor array are switched from gnd to V aq , the forward capacitance array remains unchanged, and the switching energy consumed in this process is 0; Next, the second comparison is performed to obtain the output digital code D2. When D3 = 1, if V INP -V INN Greater than V REF / 2, the output digital code D2 = 1; when D3 = 1, if V INP -V INN Less than or equal to V REF / 2, the output digital code D2 = 0; when D3 = 0, if V INP -V INN Greater than -V REF / 2, the output digital code D2 = 1; when D3 = 0, if V INP -V INN Less than or equal to -V REF / 2, the output digital code D2 = 0; like Figure 3 As shown in (a), when D3D2 = 11, the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the forward capacitor array remains unchanged, and the lower plate connections of all capacitors in the reverse capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; When D3D2 = 10, the lower plate connection of the MSB capacitor array in the reverse capacitor array is switched from gnd to Vaq, the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, and the lower plate connections of all capacitors in the forward capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16V REF 2 ; like Figure 4 As shown in (a), when D3D2 = 01, the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from gnd to Vaq, the lower plate connection of the LSB capacitor array in the forward capacitor array remains unchanged, and the lower plate connections of the MSB capacitor array and the LSB capacitor array in the reverse capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2; When D3D2 = 00, the lower plate connection of the MSB capacitor array in the reverse capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from gnd to Vaq, and the lower plate connections of all capacitors in the forward capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16 V REF 2 ; Next, the third comparison is performed to obtain D1. When D3D2 = 11, if V INP -V INN Greater than (3 / 4) V REF , then the output digital code D1 = 1; when D3D2 = 11, if V INP -V INN Less than or equal to (3 / 4) V REF , then the output digital code D1 = 0; when D3D2 = 10, if V INP -V INN Greater than (1 / 4) V REF , then the output digital code D1 = 1; when D3D2 = 10, if V INP -V INN Less than or equal to (1 / 4) V REF , then the output digital code D1 = 0; when D3D2 = 01, if V INP -V INN Greater than (-1 / 4) V REF , then the output digital code D1 = 1; when D3D2 = 01, if V INP -V INN Less than or equal to (-1 / 4) V REF , then the output digital code D1 = 0; when D3D2 = 00, if V INP -V INN Greater than (-3 / 4) V REF , then the output digital code D1 = 1; when D3D2 = 00, if V INP -V INN Less than or equal to (-3 / 4) V REF , then the output digital code D1 = 0; like Figure 3 As shown in (b), when D3D2D1 = 111, the lower plate of the capacitor (maximum capacitor C) corresponding to the LSB capacitor array in the forward capacitor array changes from V aq Switch to V CM , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CVREF 2 ; When D3D2D1 = 110, the lower plate of the corresponding capacitor (maximum capacitor C) in the MSB capacitor array in the forward capacitor array changes from V CM Switch to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 101, the lower plate of the corresponding capacitor (maximum capacitor C) in the MSB capacitor array in the reverse capacitor array changes from V aq Switch to gnd, the connection of the lower plates of the remaining capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=100, the lower plate of the corresponding capacitor (maximum capacitor C) in the LSB capacitor array in the reverse capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; like Figure 4 As shown in (b), when D3D2D1 = 011, the lower plate of the corresponding capacitor (maximum capacitor C) in the LSB capacitor array in the forward capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 010, the lower plate of the corresponding capacitor (maximum capacitor C) in the MSB capacitor array in the forward capacitor array is connected from V aq Switch to gnd, the connection of the lower plates of the remaining capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 001, the lower plate of the corresponding capacitor (maximum capacitor C) in the MSB capacitor array in the reverse capacitor array is connected from V CM Switch to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=000, the lower plate of the corresponding capacitor in the LSB capacitor array in the reverse capacitor array changes from V aq Switch to V CM , the lower plates of the other capacitors remain unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; Next, the fourth comparison is performed to obtain D0. When D3D2D1 = 111, if V INP -V INN Greater than (7 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 111, if V INP -V INN Less than or equal to (7 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 110, if V INP -V INN Greater than (5 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 110, if V INP -V INN Less than or equal to (5 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 101, if V INP -V INN Greater than (3 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 101, if V INP -V INN Less than or equal to (3 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 100, if V INP -V INN Greater than (1 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 100, if V INP -V INN Less than or equal to (1 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 011, if V INP -V INN Greater than (-1 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 011, if V INP -V INN Less than or equal to (-1 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 010, if V INP -V INN Greater than (-3 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 010, if V INP -V INN Less than or equal to (-3 / 8) VREF , then the output digital code D0 = 0; when D3D2D1 = 001, if V INP -V INN Greater than (-5 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 001, if V INP -V INN Less than or equal to (-5 / 8) V REF , then the output digital code D0 = 0; when D3D2D1 = 000, if V INP -V INN Greater than (-7 / 8) V REF , then the output digital code D0 = 1; when D3D2D1 = 000, if V INP -V INN Less than or equal to (-7 / 8) V REF , then the output digital code D0 = 0; like Figure 5 As shown, taking a 10-bit successive approximation analog-to-digital converter as an example, the MATLAB simulation result diagram of the switching energy consumption changing with the digital output code during the conversion process.

[0014] The switching method proposed in the present invention has very low energy consumption. Compared with the traditional structure, the DAC capacitor area is reduced by 75% and the switching energy consumed is reduced by 99.51% compared with the traditional structure, while the reset energy consumption is 0.

[0015] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0016] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A bottom plate sampling successive approximation analog-to-digital converter, comprising a comparator, a DAC capacitor array and a control logic circuit, characterized in that: The comparator output is connected to a control logic circuit, The DAC capacitor array includes two parts: one is a forward capacitor array connected to the positive input terminal of the comparator, the maximum capacitance of which is composed of a binary weight sub-capacitor array, called the MSB capacitor array, and the remaining capacitor array is called the LSB capacitor array; The second is a reverse capacitor array connected to the negative input terminal of the comparator, whose maximum capacitance is composed of a binary weighted sub-capacitor array, called the MSB capacitor array, and the remaining capacitor array is called the LSB capacitor array; The upper plate of the positive capacitor array is connected through the switch S P Connected to gnd, the lower plate of the MSB capacitor array in the forward capacitor array is connected to V INP 、V CM , Vaq, gnd are connected, and the lower plate of the LSB capacitor array in the forward capacitor array is connected to V CM , Vaq, gnd are connected; the upper plate of the reverse capacitor array is connected through the switch S N Connected to gnd, the lower plate of the MSB capacitor array in the reverse capacitor array is connected to V through the selection switch INN 、V CM , Vaq, gnd are connected, and the lower plate of the LSB capacitor array in the reverse capacitor array is connected to V CM , Vaq, and gnd are connected.

2. A lower plate sampling successive approximation analog-to-digital converter according to claim 1, characterized in that: The MSB capacitor array and the LSB capacitor array of the forward capacitor array include a total of 2 N-2 The unit capacitors are two bits less than the successive approximation analog-to-digital converter’s accuracy N bits; the MSB capacitor array and the LSB capacitor array of the reverse capacitor array contain a total of 2 N-2 The unit capacitance is two bits less than the N bits of accuracy of the successive approximation analog-to-digital converter.

3. A bottom plate sampling successive approximation analog-to-digital converter according to claim 1, characterized in that: The Vaq is equal to V REF / 4.

4. A switching method for a lower plate sampling successive approximation analog-to-digital converter, characterized in that: The specific implementation is: Sampling phase: Positive input voltage V INP The sampling switch is turned on to connect to the lower plate of the MSB capacitor array in the positive capacitor array, the lower plate of the LSB capacitor array in the positive capacitor array is connected to gnd, and the upper plate of the positive capacitor array is connected to gnd; the negative input voltage V INN The sampling switch is turned on to connect to the lower plate of the MSB capacitor array in the reverse capacitor array, the lower plate of the LSB capacitor array in the reverse capacitor array is connected to gnd, and the upper plate of the reverse capacitor array is connected to gnd; Comparison phase: First, S P , S N Disconnect, connect the lower plate of the MSB capacitor array in the forward capacitor array and the reverse capacitor array to gnd, and keep the lower plate connection of the LSB capacitor array unchanged, start the first comparison, and get the MSB; if V INP Greater than V INN , then the lower plates of all capacitors in the forward capacitor array are connected to Vaq, and the comparator positive input voltage V DACP Increased V REF / 4, the lower plates of all capacitors in the reverse capacitor array remain connected unchanged; conversely, the lower plates of all capacitors in the reverse capacitor array are connected to Vaq, and the negative input voltage of the comparator V DACN Increased V REF / 4, the connection of the lower plates of all capacitors in the forward capacitor array remains unchanged; Then start the second comparison; if V INP Greater than (V INN + V REF / 2), the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the forward capacitor array remains unchanged, V DACP Increased V REF / 8, the lower plate connections of all capacitors in the reverse capacitor array remain unchanged; if V INP Less than or equal to (V INN +V REF / 2) and greater than V INN , then all capacitor connections in the forward capacitor array remain unchanged, the lower plate connection of the MSB capacitor array in the reverse capacitor array is switched from gnd to Vaq, and the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACN Increased V REF / 8; if V INP Greater than (V INN -V REF / 2) and less than or equal to V INN , then the lower plate connections of all capacitors in the reverse capacitor array remain unchanged, and the lower plate connection of the MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACP Increased V REF / 8; if V INP Less than or equal to (V INN -V REF / 2), the connection of the bottom plates of all capacitors in the forward capacitor array remains unchanged, and the connection of the bottom plate of the MSB capacitor array in the reverse capacitor array is switched from Vaq to V CM , the lower plate connection of the LSB capacitor array in the reverse capacitor array remains unchanged, V DACN Increased V REF / 8; Then the third comparison is performed; if V INP Greater than (V INN + (3 / 4)V REF ), then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the LSB capacitor array in the forward capacitor array switches from Vaq to V CM , V DACP Increased V REF / 16, the lower plate connections of other capacitors in the forward capacitor array remain unchanged; if V INP Less than or equal to (V INN + (3 / 4)V REF ) and greater than (V INN + (1 / 2)V REF ), then the lower plate voltage of the capacitor corresponding to the MSB capacitor array (i.e. the maximum capacitor) in the forward capacitor array changes from V CM Switch to Vaq, V DACP Reduced V REF / 16, the lower plate connections of other capacitors in the forward capacitor array remain unchanged; if V INP Greater than (V INN + (1 / 4)V REF ) and less than or equal to (V INN + (1 / 2)V REF ), then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the MSB capacitor array in the reverse capacitor array switches from Vaq to gnd, and the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Reduced V REF / 16, the voltage on the lower plate of the forward capacitor array remains unchanged; if V INP Less than or equal to (V INN + (1 / 4)V REF ) and is greater than V INN , then the lower plate voltage of the capacitor corresponding to the LSB capacitor array (i.e., the maximum capacitor) in the reverse capacitor array switches from gnd to Vaq, and the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V INP Greater than (V INN - (1 / 4)V REF ) and V INP Less than or equal to V INN , then the lower plate of the corresponding capacitor (i.e., the maximum capacitor) in the LSB capacitor array in the forward capacitor array switches from gnd to Vaq, and the connections of other capacitors in the forward capacitor array remain unchanged, V DACP Increased V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Less than or equal to (V INN - (1 / 4)V REF ) and greater than (V INN - (1 / 2)V REF ), the lower plate voltage of the capacitor corresponding to the MSB capacitor array (i.e., the maximum capacitor) in the forward capacitor array switches from Vaq to gnd, and the other capacitor connections in the forward capacitor array remain unchanged, V DACP Reduced V REF / 16, the lower plate connection of the reverse capacitor array remains unchanged; if V INP Greater than (V INN - (3 / 4)V REF ) and less than or equal to (V INN - (1 / 2)V REF ), then the lower plate of the corresponding capacitor (i.e. the maximum capacitor) in the MSB capacitor array in the reverse capacitor array changes from V CM Switch to Vaq, the other capacitor connections in the reverse capacitor array remain unchanged, V DACN Reduced V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; if V INP Less than or equal to (V INN - (3 / 4)V REF ), the lower plate voltage of the LSB capacitor array corresponding to the capacitor (i.e. the maximum capacitor) in the reverse capacitor array switches from Vaq to V CM , the other capacitor bottom plates of the reverse capacitor array remain connected unchanged, V DACN Increased V REF / 16, the lower plate connection of the forward capacitor array remains unchanged; Next, the fourth comparison is performed, and the switching process is similar to the third one, until the LSB is obtained and the analog-to-digital conversion is completed.

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