Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method thereof and electronic equipment, and is suitable for the technical field of semiconductors, and the chip packaging structure comprises a first wafer, a first dielectric layer, a second dielectric layer, a second wafer and a conductive structure. The first dielectric layer is arranged on the first wafer, the second dielectric layer is arranged on the side, away from the first wafer, of the first dielectric layer, a conductive layer is arranged in the second dielectric layer, the second wafer is arranged on the side, away from the first wafer, of the second dielectric layer, and the second wafer comprises a first surface close to the second dielectric layer. The first surface is provided with a shallow trench isolation structure, the shallow trench isolation structure extends into the second wafer from the first surface, and the conductive structure penetrates through the second wafer and is electrically connected with the conductive layer in the second dielectric layer. Wherein the orthographic projection of the shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface. According to the technical scheme, the preparation precision and the overall performance of the chip packaging structure are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] At present, advanced packaging processes all require the use of Through Silicon Via (TSV) to achieve electrical interconnection between stacked chips, so TSV is a key structure in advanced packaging.

[0003] However, TSV has a high aspect ratio and a small process window, which increases the difficulty of etching (ETCH), physical vapor deposition (PVD), electrochemical plating (ECP) and other processes in the process of preparing chip packaging structures. There are problems such as reduced preparation accuracy and lateral notching at the bottom of the wafer due to silicon over-etching. These problems have an adverse effect on the performance of the chip packaging structure. Summary of the invention

[0004] The present application provides a chip packaging structure and a preparation method thereof, and an electronic device, aiming to improve the preparation accuracy and overall performance of the chip packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions: On the one hand, a chip packaging structure is provided, which includes a first wafer, a first dielectric layer, a second dielectric layer, a second wafer and a conductive structure. The first dielectric layer is arranged on the first wafer, the second dielectric layer is arranged on a side of the first dielectric layer away from the first wafer, a conductive layer is arranged in the second dielectric layer, the second wafer is arranged on a side of the second dielectric layer away from the first wafer, the second wafer includes a first surface close to the second dielectric layer, a shallow trench isolation structure is arranged on the first surface, the shallow trench isolation structure extends from the first surface to the second wafer, the conductive structure passes through the second wafer, and is electrically connected to the conductive layer in the second dielectric layer. The orthographic projection of the shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface.

[0006] The chip packaging structure provided in the embodiment of the present application has a first dielectric layer, a second dielectric layer, a second wafer and a conductive structure arranged on the first wafer in sequence. A shallow trench isolation structure extending from the first surface to the inside of the second wafer is arranged on the first surface of the second wafer near the second dielectric layer, and the shallow trench isolation structure protects the portion of the second wafer near the first surface from being over-etched. The conductive structure runs through the second wafer and is electrically connected to the conductive layer in the second dielectric layer. The orthographic projection of the shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface. It can be understood that the shallow trench isolation structure is arranged around the conductive structure near the first surface to protect the second wafer and prevent the second wafer from having side-digging morphological defects, thereby improving the reliability of the chip packaging structure formed by stacking the first wafer and the second wafer.

[0007] In some embodiments, the etching selectivity of the shallow trench isolation structure is different from the etching selectivity of the second wafer and is different from the etching selectivity of the second dielectric layer.

[0008] In some embodiments, the density of the shallow trench isolation structure is greater than the density of the second dielectric layer.

[0009] In some embodiments, the material of the shallow trench isolation structure includes at least one of silicon oxide, silicon nitride, or silicon carbon nitride.

[0010] In some embodiments, the orthographic projection of the conductive structure on the first surface is a circle, and the orthographic projection of the shallow trench isolation structure on the first surface is a ring.

[0011] In some embodiments, the inner diameter of the annular shape is greater than or equal to the outer diameter of the circular shape.

[0012] On the other hand, a method for preparing a chip packaging structure is also provided, the method for preparing the chip packaging structure comprising: forming a first dielectric layer on a first wafer to obtain a first bonding structure, forming a second wafer, the second wafer comprising a first surface and a second surface opposite to each other, the first surface being provided with a first shallow trench isolation structure, the first shallow trench isolation structure extending from the first surface into the second wafer, forming a second dielectric layer on the first surface of the second wafer to obtain a second bonding structure, a conductive layer being provided in the second dielectric layer, bonding the first bonding structure to the second bonding structure, connecting the surface of the first dielectric layer away from the first wafer to the surface of the second dielectric layer away from the second wafer, forming a conductive structure penetrating the second wafer, and the conductive structure being electrically connected to the conductive layer in the second dielectric layer. The orthographic projection of the first shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface.

[0013] The preparation method provided in the embodiment of the present application is to set a first shallow trench isolation structure on the first surface of the second wafer, and the shallow trench isolation structure protects the portion of the second wafer close to the first surface from being over-etched. The conductive structure runs through the second wafer, and the conductive structure is electrically connected to the conductive layer in the second dielectric layer. The orthographic projection of the first shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface. It can be understood that the shallow trench isolation structure is set around the conductive structure close to the first surface to protect the second wafer and prevent the second wafer from having side-digging morphological defects, thereby improving the reliability of the chip packaging structure formed by stacking the first wafer and the second wafer.

[0014] In some embodiments, the first surface is further provided with a plurality of transistors and a second shallow trench isolation structure located between the plurality of transistors. During the process of forming the second shallow trench isolation structure, the first shallow trench isolation structure is simultaneously formed.

[0015] In some embodiments, the second surface is also provided with a plurality of transistors and a second shallow trench isolation structure between the plurality of transistors. Forming the first shallow trench isolation structure includes etching the first surface using a photolithography process to form a shallow trench, and forming the first shallow trench isolation structure in the shallow trench.

[0016] On the other hand, an electronic device is provided. The electronic device includes the above-mentioned and a circuit board, wherein the chip packaging structure is arranged on the circuit board and is electrically connected to the circuit board.

[0017] The electronic device provided in the embodiment of the present application has an improved overall performance of the chip packaging structure, so that the preparation accuracy and overall performance of the chip packaging structure are improved, thereby also improving the reliability of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 2 for Figure 1 A partial cross-sectional view of the chip package structure along the section line AA'; Figure 3 A preparation flow chart of a chip packaging structure provided in an embodiment of the present application; Figure 4~Figure 7 for Figure 3 A diagram of each step of the preparation process; Figure 8 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0020] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0021] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0022] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0023] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0024] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0025] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0026] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0027] In the common through silicon via loop technology (TSV Loop), during the etching process, not only does the aspect ratio of TSV ETCH become large, but the film layers to be etched are also very complex. According to the process before and after, the film layers to be etched are the top dielectric layer, silicon, the bottom dielectric layer, the insulating oxide layer (there may also be a residual dielectric layer at this time), and finally stop at the metal conductive structure set in the dielectric layer, and then electrical connection can be achieved. The above problems make the TSV ETCH process more difficult, which reduces the precision of the TSV formed, and then reduces the overall performance of the chip packaging structure.

[0028] After the TSV silicon through hole is completed, TSV bottom oxide nitride etching (Bottom ONO ETCH) is required. Before TSV Bottom ONO ETCH, it is necessary to ensure that Si is just etched. However, in the actual preparation process, due to the difference in the thickness of the Si to be etched and the difference in wafer temperature at different positions during the low-temperature etching of the stacked wafers, the position of the Si through hole is not completely etched or is over-etched.

[0029] When Si is not completely etched, the subsequent ONO ETCH has a slow etching rate on Si. After ONO ETCH has completed Si etching, when ONO ETCH is performed again, the etching depth of ONO ETCH is insufficient, and ultimately the overall TSVETCH does not stop on the metal, resulting in a short circuit in the chip.

[0030] When Si is over-etched, since the overall etching process parameters (recipe) have almost no etching rate for the dielectric layer, only the lateral Si can be etched, resulting in a Notching bottom side morphology, affecting the overall performance of the chip.

[0031] To solve at least one of the above problems, the embodiments of the present application provide the following technical solutions: Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 2 for Figure 1 A partial cross-sectional view of the chip package structure along the section line AA'.

[0032] On the one hand, the embodiments of the present application provide a chip packaging structure, such as Figure 1As shown, the chip packaging structure 1 includes a first wafer 10, a first dielectric layer 11, a second dielectric layer 12, a second wafer 13 and a conductive structure 14. Exemplarily, it also includes a mask layer 16 arranged on the second wafer 13 away from the first wafer 10, and a seed layer 17 and a barrier layer 18 arranged around the conductive structure 14 in sequence, and an insulating layer is also arranged between the barrier layer 18 and the second wafer 13, and the barrier layer 18 and the insulating layer are used to prevent copper ions in the conductive structure 14 from diffusing into the second wafer 13.

[0033] The first dielectric layer 11 is disposed on the first wafer 10, the second dielectric layer 12 is disposed on the side of the first dielectric layer 11 away from the first wafer 10, and a conductive layer 121 is disposed in the second dielectric layer 12 to achieve electrical connection between the first wafer 10 and the second wafer 13. The second wafer 13 is disposed on the side of the second dielectric layer 12 away from the first wafer 10, and the second wafer 13 includes a first surface 131 close to the second dielectric layer 12, and a shallow trench isolation structure 15 is disposed on the first surface 131. The shallow trench isolation structure (STI) 15 extends from the first surface 131 into the second wafer 13 to prevent over-etching of silicon on the side of the through hole when the second wafer 13 forms a through hole, that is, the shallow trench isolation structure 15 can prevent the generation of the defect morphology of Notching. The conductive structure 14 penetrates the second wafer 13 and is electrically connected to the conductive layer 121 in the second dielectric layer 12. The conductive structure 14 is a conductive material in TSV.

[0034] Among them, Figure 2 As shown, the orthographic projection of the shallow trench isolation structure 15 on the first surface 131 surrounds the orthographic projection of the conductive structure 14 on the first surface 131. It can be understood that the shallow trench isolation structure 15 is arranged around the conductive structure 14 to protect the second wafer 13 from being over-etched.

[0035] In the chip packaging structure 1 provided in the embodiment of the present application, a first dielectric layer 11, a second dielectric layer 12, a second wafer 1 and a conductive structure 14 are sequentially arranged on the first wafer 10. A shallow trench isolation structure 15 extending from the first surface 131 to the inside of the second wafer 13 is arranged on the first surface 131 of the second wafer 13 near the second dielectric layer 12, and the shallow trench isolation structure 15 protects the portion of the second wafer 13 near the first surface 131 from being over-etched. The conductive structure 14 penetrates the second wafer 13 and is electrically connected to the conductive layer 121 in the second dielectric layer 12. The orthographic projection of the shallow trench isolation structure 15 on the first surface 131 surrounds the orthographic projection of the conductive structure 14 on the first surface 131. It can be understood that the shallow trench isolation structure 15 is arranged around the conductive structure 14 near the first surface 131 to protect the second wafer 13 and prevent the second wafer 13 from having a side-digging morphological defect, thereby improving the reliability of the chip packaging structure 1 formed by stacking the first wafer 10 and the second wafer 13.

[0036] In some embodiments, Figure 2 As shown, the etching selectivity of the shallow trench isolation structure 15 is different from the etching selectivity of the second wafer 13 and the etching selectivity of the second dielectric layer 12. In the related art, when the TSV with a fast etching progress reaches the bottom, since the etching selectivity of the bottom dielectric layer is greater than that of silicon, the etching ions will etch the Si in the surrounding side directions, resulting in the above-mentioned bottom side Notching defect morphology.

[0037] In the embodiment of the present application, during the process of etching to form TSV, after the silicon etching at the TSV opening position is completed, the second wafer 13 near the first surface 131 is surrounded by a shallow trench isolation structure 15, and the bottom is a second dielectric layer 12. Since the etching selectivity of the shallow trench isolation structure 15 is different from the etching selectivity of the second wafer 13 and the second dielectric layer 12, the recipe for etching Si at this time has almost no etching rate for the second wafer 13 and the second dielectric layer 12, and even if the etching continues, the morphology of Si remains unchanged. If the area that has been partially etched to the bottom continues to be etched, no lateral Notching morphology will appear, thereby ensuring the improvement of the reliability of the internal structure of the second wafer 13.

[0038] In some embodiments, the density of the shallow trench isolation structure 15 is greater than the density of the second dielectric layer 12. The shallow trench isolation structure 15 is usually filled with an oxide material. Exemplarily, the material of the shallow trench isolation structure 15 includes at least one of dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN) or silicon carbonitride (SiCN), which does not affect the electrical performance of the TSV. The second dielectric layer 12 is a back-end metal layer, and its material is a low dielectric constant material (Low k), which has a lower density and is more easily etched. At the same time, the shallow trench isolation structure 15 provided in the present application is located in a lateral position, and the plasma mainly etches the material in the vertical direction. Therefore, the shallow trench isolation structure 15 is almost not consumed by etching and can be completely retained without changing the original vertical morphology of the TSV.

[0039] In some embodiments, Figure 2 As shown, the orthographic projection of the conductive structure 14 on the first surface 131 is a circle, and the orthographic projection of the shallow trench isolation structure 15 on the first surface is a ring. Exemplarily, with the center of the conductive structure 14 as a reference point, the inner edge of the shallow trench isolation structure 15 has the same shape as the outer edge of the conductive structure 14, for example, the inner edge of the shallow trench isolation structure 15 and the outer edge of the conductive structure 14 are both circular. With the center of the conductive structure 14 as a reference point, the shape of the outer edge of the shallow trench isolation structure 15 is not limited, and can be circular, square, irregular, etc. For example, the outer edge of the shallow trench isolation structure 15 is a circle with a larger radius.

[0040] In some embodiments, Figure 2 As shown, the inner diameter of the shallow trench isolation structure 15 is greater than or equal to the outer diameter of the circle of the conductive structure 14. The present application takes the example that the inner diameter of the shallow trench isolation structure 15 is greater than the outer diameter of the circle of the conductive structure 14. It can be understood that a seed layer 17 and a barrier layer 18 are provided between the inner diameter of the ring and the outer diameter of the circle, the shallow trench isolation structure 15 is adjacent to the barrier layer 18, and the conductive structure 14 is adjacent to the seed layer 17, so that the shallow trench isolation structure 15 better fits the circular morphology of the conductive structure 14, so that there is no gap between the shallow trench isolation structure 15 and the conductive structure 14, thereby further enhancing the protection of the structure in the second wafer 13.

[0041] On the other hand, a method for preparing a chip packaging structure is also provided. Figure 3 A preparation flow chart of a chip packaging structure provided in an embodiment of the present application; Figure 4~Figure 7 for Figure 3 The steps of the preparation process are shown in Figure 2. Figure 3 As shown, the method for preparing the chip packaging structure includes the following steps S1 to S5: Step S1: forming a first dielectric layer 11 on a first wafer 10 to obtain a first bonding structure.

[0042] Step S2 : forming a second wafer 13 , the second wafer 13 comprising a first surface 131 and a second surface 132 opposite to each other, the first surface 131 being provided with a first shallow trench isolation structure 15 , the first shallow trench isolation structure 15 extending from the first surface 131 into the second wafer 13 .

[0043] In some embodiments, the first surface 131 is also provided with a plurality of transistors, and a second shallow trench isolation structure located between the plurality of transistors. In the process of forming the second shallow trench isolation structure, the first shallow trench isolation structure 15 is formed simultaneously. In the embodiment provided in the present application, the first wafer 10 and the second wafer 13 adopt a face-to-face (F2F) bonding process, and the graphics of the first shallow trench isolation structure 15 and the second shallow trench isolation structure can be integrated into the STI mask, and the process can also be consistent with the original STI Loop (AA Loop), that is, the first shallow trench isolation structure 15 and the second shallow trench isolation structure are formed in the same process step, and the same mask can be used, without adding additional process steps, and the original process recipe and flow almost do not need to be adjusted, and the preparation cost is not increased.

[0044] In some embodiments, the second surface 132 is also provided with a plurality of transistors, and a second shallow trench isolation structure located between the plurality of transistors. The first shallow trench isolation structure 15 is formed, including etching the first surface using a photolithography process to form a shallow trench, and forming the first shallow trench isolation structure 15 in the shallow trench. It is understandable that, in the case where the first wafer 10 and the second wafer 13 are bonded in a back-to-face bonding process, it is only necessary to add a photomask to form the first shallow trench isolation structure 15 during the process of the second shallow trench isolation structure. The process parameters of this process are consistent with the conventional STI Loop (AA Loop), which is simple and easy to implement, and improves the process feasibility of the preparation method provided in the present application.

[0045] Step S3 : forming a second dielectric layer 12 on the first surface 131 of the second wafer 13 to obtain a second bonding structure, wherein the second dielectric layer 12 is provided with a conductive layer 121 .

[0046] Step S4: Figure 4 As shown, the first bonding structure is bonded to the second bonding structure, and the surface of the first dielectric layer 11 away from the first wafer 10 is electrically connected to the surface of the second dielectric layer 12 away from the second wafer 13 .

[0047] Step S5: Figure 5~Figure 7As shown, a conductive structure 14 is formed penetrating the second wafer 13 and electrically connected to the conductive layer 121 in the second dielectric layer 12. The orthographic projection of the first shallow trench isolation structure 15 on the first surface 131 surrounds the orthographic projection of the conductive structure 14 on the first surface 131.

[0048] Specifically, before forming the conductive structure 14, as Figure 5 As shown, a mask layer 16 having an opening is formed on the second surface 132 of the second wafer 13 away from the second dielectric layer 12, and the second wafer 13 is etched through the opening of the mask layer 16. Due to the presence of the first shallow trench isolation structure 15, no lateral Notching morphology defects are generated when etching the second wafer 13, so as to obtain a vertical through hole 160, and then the etching selectivity is changed, and the second dielectric layer 12 is continuously etched through the opening of the mask layer 16 until the conductive layer 121 is exposed. Then, as shown in FIG. Figure 6 As shown, an insulating layer 18, a barrier layer 17 and a seed layer are sequentially formed in the through hole 160, and then Figure 7 As shown, copper electroplating is performed, and finally the copper located on the side of the mask layer 16 away from the second wafer 13 is chemically mechanically polished, and after the entire structure is annealed, the mask layer 16 is chemically mechanically polished on the side away from the second wafer 13 to obtain Figure 1 The chip packaging structure 1 is shown.

[0049] The preparation method provided in the embodiment of the present application is to set a first shallow trench isolation structure 15 on the first surface 131 of the second wafer 13, and the shallow trench isolation structure 15 protects the portion of the second wafer 13 close to the first surface 131 from being over-etched. The conductive structure 14 runs through the second wafer 13, and the conductive structure 14 is electrically connected to the conductive layer 121 in the second dielectric layer 12. The orthographic projection of the first shallow trench isolation structure 15 on the first surface 131 surrounds the orthographic projection of the conductive structure 14 on the first surface 131. It can be understood that the shallow trench isolation structure 15 is set around the conductive structure 14 close to the first surface 131 to protect the second wafer 13 and prevent the second wafer 13 from having a side-digging morphological defect, thereby improving the reliability of the chip packaging structure 1 formed by stacking the first wafer 10 and the second wafer 13.

[0050] On the other hand, the present application also provides an electronic device, Figure 8 A schematic diagram of an electronic device provided in an embodiment of the present application, such as Figure 8As shown, the electronic device 2 includes the chip packaging structure 1 mentioned above, and a circuit board 21. The chip packaging structure 1 is arranged on the circuit board 21 and is electrically connected to the circuit board 21. Exemplarily, the chip packaging structure 1 is electrically connected to the circuit board 21 through a solder ball 20. In the electronic device 2 provided in the embodiment of the present application, the preparation accuracy and overall performance of the chip packaging structure 1 are improved, thereby also improving the reliability of the electronic device 2.

[0051] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: First Wafer; A first dielectric layer is disposed on the first wafer; a second dielectric layer, disposed on a side of the first dielectric layer away from the first wafer, wherein a conductive layer is disposed in the second dielectric layer; A second wafer is arranged on a side of the second dielectric layer away from the first wafer; the second wafer comprises a first surface close to the second dielectric layer, the first surface is provided with a shallow trench isolation structure, and the shallow trench isolation structure extends from the first surface into the second wafer; a conductive structure, penetrating the second wafer and electrically connected to the conductive layer in the second dielectric layer; The orthographic projection of the shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface.

2. The chip packaging structure according to claim 1, characterized in that: The etching selectivity of the shallow trench isolation structure is different from the etching selectivity of the second wafer and the etching selectivity of the second dielectric layer.

3. The chip packaging structure according to claim 1, characterized in that: The density of the shallow trench isolation structure is greater than the density of the second dielectric layer.

4. The chip packaging structure according to claim 1, characterized in that: The material of the shallow trench isolation structure includes at least one of silicon oxide, silicon nitride or silicon carbon nitride.

5. The chip packaging structure according to claim 1, characterized in that: The orthographic projection of the conductive structure on the first surface is a circle; The orthographic projection of the shallow trench isolation structure on the first surface is a ring.

6. The chip packaging structure according to claim 5, characterized in that: The inner diameter of the ring is greater than or equal to the outer diameter of the circle.

7. A method for preparing a chip packaging structure, characterized in that: include: forming a first dielectric layer on a first wafer to obtain a first bonding structure; forming a second wafer, the second wafer comprising a first surface and a second surface opposite to each other, the first surface being provided with a first shallow trench isolation structure, the first shallow trench isolation structure extending from the first surface into the second wafer; forming a second dielectric layer on the first surface of the second wafer to obtain a second bonding structure, wherein a conductive layer is disposed in the second dielectric layer; Bonding the first bonding structure to the second bonding structure, so that a surface of the first dielectric layer away from the first wafer is connected to a surface of the second dielectric layer away from the second wafer; forming a conductive structure penetrating the second wafer, wherein the conductive structure is electrically connected to the conductive layer in the second dielectric layer; The orthographic projection of the first shallow trench isolation structure on the first surface surrounds the orthographic projection of the conductive structure on the first surface.

8. The preparation method according to claim 7, characterized in that: The first surface is also provided with a plurality of transistors, and a second shallow trench isolation structure located between the plurality of transistors; During the process of forming the second shallow trench isolation structure, the first shallow trench isolation structure is formed simultaneously.

9. The preparation method according to claim 7, characterized in that: The second surface is also provided with a plurality of transistors, and a second shallow trench isolation structure located between the plurality of transistors; The first shallow trench isolation structure is formed, comprising: Using a photolithography process, etching the first surface to form a shallow groove; The first shallow trench isolation structure is formed in the shallow trench.

10. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 6; A circuit board, the chip packaging structure is arranged on the circuit board and is electrically connected to the circuit board.

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