LDMOS device and electronic equipment

Abstract

The utility model provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and electronic equipment. The LDMOS device comprises a substrate; the gate structure is located on the surface of the substrate; the source region and the drain region extend into the substrate from the surface of the substrate and are located on the two sides of the gate structure; the field oxide layer covers at least part of the surface of the drain region and extends to cover part of the surface, close to the drain region, of the gate structure; the at least one string of field plate structure is located on the field oxide layer and is arranged between the gate structure and the drain region, each string of field plate structure comprises a plurality of conductive contact field plate holes, and the plurality of conductive contact field plate holes are arranged in a string in a plane parallel to the surface of the substrate; and in the length extension direction of at least one string of field plate structures, a gap exists between the adjacent conductive contact field plate holes.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to an LDMOS device and an electronic device. Background Art

[0002] With the continuous development of integrated circuits, in order to save area, multiple devices are often prepared on the same substrate at the same time. For example, in the BCD (Bipolar-CMOS-DMOS) process, bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and diffused metal oxide semiconductors (DMOS) can be prepared on the same substrate. The BCD process is widely used in power management, display drive, electrode drive, automotive electronics, industrial control and other fields, and is mainly developed in the direction of high voltage, high power and high density.

[0003] In the manufacturing process of the BCD process, it is often necessary to add a field plate technology at the drain end to improve the breakdown voltage of the laterally diffused metal oxide semiconductor (LDMOS) device. In order to save process time and process cost, in the related technology, the field plate structure and the metal contact hole (such as the gate metal contact hole, the drain metal contact hole and the source metal contact hole) are formed simultaneously. However, since the field plate structure is a long strip and the metal contact hole is a hole-shaped structure, due to the pattern density effect, it is difficult to achieve the target value for the size / morphology of the field plate structure. Utility Model Content

[0004] A series of simplified concepts are introduced in the utility model content section, which will be further described in detail in the detailed implementation section. The utility model content section of the utility model does not mean to attempt to define the key features and essential technical features of the technical solution claimed for protection, nor does it mean to attempt to determine the scope of protection of the technical solution claimed for protection.

[0005] In view of the existing problems, the utility model provides an LDMOS device, which is characterized by comprising:

[0006] substrate;

[0007] A gate structure located on the surface of the substrate;

[0008] A source region and a drain region extending from the surface of the substrate into the substrate and located on both sides of the gate structure;

[0009] A field oxide layer, covering at least a portion of the surface of the drain region and extending to cover a portion of the surface of the gate structure near the drain region;

[0010] At least one string of field plate structures, at least one string of the field plate structures is located on the field oxide layer and is arranged between the gate structure and the drain region, each string of the field plate structures includes a plurality of conductive contact field plate holes, the plurality of conductive contact field plate holes are arranged in a string in a plane parallel to the surface of the substrate, and there are gaps between adjacent conductive contact field plate holes in the length extension direction of at least one string of the field plate structures.

[0011] Exemplarily, at least two strings of field plate structures are included, and at least two strings of the field plate structures are arranged along a first direction, wherein the first direction is a direction from the drain region to the source region and is parallel to the surface of the substrate.

[0012] Exemplarily, each string of the field plate structures is arranged in any one of the following shapes: a straight line, a curve, or a broken line.

[0013] Exemplarily, at least one string of the field plate structures has a first projection in a plane parallel to the surface of the substrate, and the gate structure has a second projection in a plane parallel to the surface of the substrate, and the first projection and the second projection are adjacent, or there is a gap between the first projection and the second projection.

[0014] Exemplarily, the multiple conductive contact field plate holes included in at least one string of the field plate structures have the same size in a first direction, or, at least some of the multiple conductive contact field plate holes included in at least one string of the field plate structures have different sizes in the first direction, and the first direction is the direction from the drain region to the source region and is parallel to the surface of the substrate.

[0015] Exemplarily, the projection shape of the plurality of conductive contact field plate holes in a plane parallel to the surface of the substrate is a combination of one or more of a circle, an ellipse, and a rectangle.

[0016] Exemplarily, it also includes a gate conductive contact hole, a drain region conductive contact hole and a source region conductive contact hole, the gate conductive contact hole is electrically connected to the gate structure, the drain region conductive contact hole is electrically connected to the drain region, and the source region conductive contact hole is electrically connected to the source region, wherein:

[0017] The aperture of the conductive contact field plate hole is greater than or equal to the aperture of the gate conductive contact hole,

[0018] The aperture of the conductive contact field plate hole is greater than or equal to the aperture of the drain region conductive contact hole.

[0019] The diameter of the conductive contact field plate hole is greater than or equal to the diameter of the source region conductive contact hole.

[0020] Exemplarily, the LDMOS device includes at least two series of field plate structures, wherein the aperture of the conductive contact field plate hole close to the gate structure is larger than the aperture of the conductive contact field plate hole far from the gate structure.

[0021] Exemplarily, when the LDMOS device includes at least two strings of field plate structures, there is a gap between the field plate structures of adjacent strings.

[0022] Exemplarily, at least two strings of the field plate structures include a first string of field plate structures, a second string of field plate structures and a third string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes, the second string of field plate structures includes a plurality of second conductive contact field plate holes, and the third string of field plate structures includes a plurality of third conductive contact field plate holes, wherein the plurality of first conductive contact field plate holes and the plurality of second conductive contact field plate holes are arranged one-to-one in the first direction, and in the length extension direction of the first string of field plate structures and the second string of field plate structures, there is a first interval between adjacent first conductive contact field plate holes and a second interval between adjacent second conductive contact field plate holes, the first interval and the second interval adjacent to each other in the first direction constitute a third interval, and one or more third conductive contact field plate holes are arranged in each of the third intervals.

[0023] Exemplarily, a size of the third conductive contact field plate hole in the first direction is larger than a size of the first conductive contact field plate hole, and a size of the third conductive contact field plate hole in the first direction is larger than a size of the second conductive contact field plate hole.

[0024] Exemplarily, a size of the third conductive contact field plate hole in the first direction is greater than a size in a second direction, wherein the second direction is perpendicular to the first direction and the second direction is parallel to the surface of the substrate.

[0025] Exemplarily, at least two strings of the field plate structures include a first string of field plate structures and a second string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes, the second string of field plate structures includes a plurality of second conductive contact field plate holes, and the plurality of first conductive contact field plate holes and the plurality of second conductive contact field plate holes are alternately arranged in the first direction.

[0026] Exemplarily, it also includes:

[0027] a barrier layer, the barrier layer covering the field oxide layer;

[0028] An interlayer dielectric layer covers the surface of the substrate and the barrier layer, wherein a plurality of the conductive contact field plate holes penetrate the interlayer dielectric layer and the barrier layer.

[0029] In yet another aspect, the present application provides an electronic device, comprising the aforementioned LDMOS device.

[0030] The LDMOS device of the embodiment of the utility model includes at least one string of field plate structures, each string of field plate structures includes a plurality of conductive contact field plate holes. Since the conductive contact field plate holes are a hole-shaped structure, the morphology / size of the conductive contact holes (used to electrically connect to, for example, the drain region, the source region and the gate structure, respectively) are similar, so that the field plate structure and the conductive contact holes can be formed simultaneously during the preparation of the LDMOS device, and the size / morphology of the field plate structure can be made easier to reach the target value, thereby ensuring the operating voltage and withstand voltage performance of the device and improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The following drawings of the present invention are used as a part of the present invention for understanding the present invention. The drawings show the embodiments of the present invention and their descriptions, and are used to explain the principle of the present invention.

[0032] In the attached figure:

[0033] Figure 1A A schematic top view of an LDMOS device in the related art is shown;

[0034] Figure 1B A cross-sectional schematic diagram of an LDMOS device in the related art is shown;

[0035] Figure 2 A schematic top view of an LDMOS device according to a specific embodiment of the present utility model is shown;

[0036] Figure 3 A cross-sectional schematic diagram of an LDMOS device according to a specific embodiment of the utility model is shown.

[0037] Figure 4 A schematic top view of an LDMOS device according to another specific embodiment of the present invention is shown;

[0038] Figure 5 A schematic top view of an LDMOS device according to another specific embodiment of the present invention is shown;

[0039] Figure 6 A schematic top view of an LDMOS device according to another specific embodiment of the present invention is shown;

[0040] Figure 7 A schematic top view of an LDMOS device according to another specific embodiment of the present invention is shown;

[0041] Figure 8 A schematic top view of an LDMOS device according to another specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] Next, the utility model will be described more completely in conjunction with the accompanying drawings, in which embodiments of the utility model are shown. However, the utility model can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and fully convey the scope of the utility model to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0043] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0044] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms "a", "an" and " / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the utility model are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the utility model. In this way, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the utility model should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the utility model.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field of the utility model. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have the same meaning as they have in the context of the relevant field and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0048] In order to thoroughly understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0049] In related technologies, the field plate structure refers to an oxide layer and a field plate covering the planar junction interface. The field plate is generally made of metal. By applying a bias voltage to the field plate, the average electric field in the drift region is increased, thereby reducing the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and increasing the breakdown voltage.

[0050] In the BCD process, it is often necessary to form a field plate structure at the drain end of the LDMOS to increase the breakdown voltage of the LDMOS. At the same time, a contact hole needs to be formed in the LDMOS to lead out the source and drain regions. Generally speaking, the target critical dimensions of the field plate and the contact hole are different. The bottom width of the field plate is larger than the bottom width of the contact hole. For example, the bottom width of the field plate ranges from 220nm to 260nm. For example, the bottom width of the field plate can be 220nm, 230nm, 240nm, 245nm, 250nm, 260nm, etc., while the bottom width of the contact hole ranges from 160nm to 185nm. For example, the bottom width of the contact hole can be 160nm, 170nm, 180nm, 185nm, etc.

[0051] In the related art, in order to save process time and process cost, the field plate structure and the conductive contact hole, such as the metal contact hole, are usually formed simultaneously, that is, the two share the same photomask layer, the same patterning structure, and are patterned (such as photolithography, etching, wet cleaning) simultaneously. Figure 1A and Figure 1B As shown, because the field plate structure 140 located outside the gate structure 150 is in the shape of an elongated strip, the conductive contact holes (such as the drain conductive contact hole 130, the source conductive contact hole 120 and the gate conductive contact hole 110) are hole-like structures, due to the pattern density effect, the size / morphology of the field plate structure is difficult to reach the target value, and it is difficult to ensure the operating voltage and withstand voltage performance of the device, resulting in a reduction in the device yield.

[0052] Therefore, in view of the existence of the above-mentioned technical problems, the utility model proposes an LDMOS device, comprising:

[0053] substrate;

[0054] A gate structure is located on the surface of the substrate;

[0055] The source region and the drain region extend from the surface of the substrate into the substrate and are located on both sides of the gate structure;

[0056] A field oxide layer extending from at least a portion of the surface of the drain region to cover a portion of the surface of the gate structure near the drain region;

[0057] At least one string of field plate structures, at least one string of field plate structures is located on the field oxide layer and is arranged between the gate structure and the drain region, each string of field plate structures includes a plurality of conductive contact field plate holes, the plurality of conductive contact field plate holes are arranged in a string in a plane parallel to the surface of the substrate, and there is a gap between adjacent conductive contact field plate holes in the length extension direction of at least one string of field plate structures.

[0058] The LDMOS device of the embodiment of the utility model includes at least one string of field plate structures, each string of field plate structures includes a plurality of conductive contact field plate holes. Since the conductive contact field plate holes are a hole-shaped structure, they are similar in shape / size to the conductive contact holes used to electrically connect to, for example, the drain region, the source region and the gate structure, so that the field plate structure and the conductive contact holes can be formed simultaneously when the LDMOS device is prepared, so that the size / morphology of the field plate structure can be more easily reached to the target value, thereby ensuring the operating voltage and withstand voltage performance of the device and improving the yield of the device.

[0059] Next, we will refer to Figures 2 to 8 The LDMOS device of the present invention is described in detail. Under the premise of no conflict, the technical features in various embodiments of the present application can be combined with each other.

[0060] As an example, Figure 3 As shown, the LDMOS device of the present application includes a substrate 200. In one example, the substrate 200 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 200 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present invention.

[0061] Exemplarily, the substrate 200 includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Optionally, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Exemplarily, the semiconductor substrate and the epitaxial layer may have different doping concentrations, for example, the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor substrate. Optionally, the epitaxial layer may serve as a drift region of the LDMOS device of the utility model. The presence of the drift region can provide a breakdown voltage of the device and play a buffering role, while reducing the parasitic capacitance between the source and the drain.

[0062] Specifically, Figure 3 As shown, a gate structure 201 is formed on the surface of a substrate 200 , and a source region 202 and a drain region 203 extending from the surface of the substrate 200 to the substrate 200 are formed in the substrate 200 . The source region 202 and the drain region 203 are respectively located on both sides of the gate structure 201 .

[0063] By way of example, the gate structure 201 may include a gate layer and a gate oxide layer located below the gate layer, wherein the gate oxide layer is formed on the surface of the substrate 200 to isolate the gate structure 201 .

[0064] In one example, the source region 202 and the drain region 203 may be formed by an ion implantation process. Exemplarily, the source region 202 and the drain region 203 have the same conductivity type, and have a different conductivity type from the substrate 200, for example, the substrate 200 is a P-type conductivity type, and the source region 202 and the drain region 203 are an N-type conductivity type; or, the substrate 200 is an N-type conductivity type, and the source region 202 and the drain region 203 are a P-type conductivity type.

[0065] In one example, if Figure 3 As shown, the gate structure 201 also includes sidewalls located on both sides of the gate layer. Exemplarily, the gate layer is composed of polysilicon material, and metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. Exemplarily, the material of the sidewall includes insulating materials such as silicon nitride, silicon oxide or silicon oxynitride. As the device size becomes smaller and smaller, the channel length of the device becomes smaller and smaller. The role of the sidewall is to increase the channel length of the formed transistor and reduce the short channel effect and the hot carrier effect caused by the short channel effect. Exemplarily, the sidewall can be a single-layer structure or a multi-layer structure. For example, the sidewall can be a single-layer silicon dioxide structure, a double-layer structure of silicon dioxide and silicon nitride, or a three-layer structure of double-layer silicon dioxide and single-layer silicon nitride. This application does not limit this. Various deposition methods commonly used in the art can be used to form the sidewalls located on both sides of the gate layer, for example, the sidewalls can be formed by chemical vapor deposition (CVD).

[0066] In one example, if Figure 3 As shown, the field oxide layer 204 may cover at least a portion of the surface of the drain region 203 and extend to cover a portion of the surface of the gate structure 201 close to the drain region 203 .

[0067] In some embodiments, continue to refer to Figure 3 The field oxide layer 204 is also covered with a barrier layer 205. In one example, the barrier layer 205 is made of a nitride layer, such as a silicon nitride layer, silicon oxynitride, silicon carbide or other suitable materials.

[0068] Furthermore, the LDMOS device of the present application also includes an interlayer dielectric layer 206, which covers the surface of the substrate and the barrier layer. The interlayer dielectric layer can use, for example, SiO2, fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or silicon carbonitride (SiCN). Alternatively, a film having a SiCN film formed on a fluorocarbon (CF) can also be used. Fluorocarbons have fluorine (F) and carbon (C) as main components. Fluorocarbons can also use substances with a non-crystalline (non-crystalline) structure. The interlayer dielectric layer can also use a porous structure such as carbon-doped silicon oxide (SiOC).

[0069] In some embodiments, an etch stop layer is further formed below the interlayer dielectric layer 206 and above the barrier layer 205, as an etch stop layer when etching the interlayer dielectric layer 206 to form a through hole. The etch stop layer can use the same material as the aforementioned barrier layer or a different material. Optionally, the material of the etch stop layer may include at least one of SiCN, SiN, SiC, SiOF, SiON, etc., or other suitable materials.

[0070] Exemplarily, various deposition methods commonly used in the art can be used to form the interlayer dielectric layer 206, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Exemplarily, the material of the etch stop layer includes a nitride layer. Exemplarily, the etch stop layer has the same material as the barrier layer 205. When the etch stop layer is formed, the barrier layer 205 and the etch stop layer thereon can act as a barrier layer together.

[0071] Further, if Figure 2 and Figure 3 As shown, the LDMOS device of the present application further includes at least one string of field plate structures, at least one string of field plate structures is located on the field oxide layer and is disposed between the gate structure 201 and the drain region, each string of field plate structures includes a plurality of conductive contact field plate holes 209, and the plurality of conductive contact field plate holes 209 are arranged in a string in a plane parallel to the surface of the substrate, and there are intervals between adjacent conductive contact field plate holes 209 in the length extension direction of at least one string of field plate structures. Since the conductive contact field plate holes 209 are a hole-shaped structure, the morphology / size of the conductive contact holes (used to be electrically connected to, for example, the drain region, the source region, and the gate structure 201, respectively) are similar, so that the field plate structure and the conductive contact hole can be formed simultaneously during the preparation of the LDMOS device, and the size / morphology of the field plate structure can be made easier to reach the target value, thereby ensuring the operating voltage and withstand voltage performance of the device and improving the yield of the device.

[0072] The number of strings of the field plate structure can be reasonably set according to actual needs, for example, it can be 1, 2, 3 or more strings.

[0073] like Figure 4 and Figure 5 As shown, the LDMOS device of the present application may include a series of field plate structures, which include a plurality of conductive contact field plate holes 209, which are arranged in series, wherein the size of the conductive contact field plate hole 209 in the first direction is larger than the size of the gate conductive contact hole 212, such as the aperture, the size of the conductive contact field plate hole in the first direction is larger than the size of the drain region conductive contact hole 213, such as the aperture, and the size of the conductive contact field plate hole 209 in the first direction is larger than the size of the source region conductive contact hole 211, such as the aperture, and the size of the conductive contact field plate hole 209 meets the target value, thereby ensuring the operating voltage and withstand voltage performance of the device.

[0074] For example, Figure 2 , Figures 6 to 8 As shown, the LDMOS device of the present application includes at least two strings of field plate structures, and the at least two strings of field plate structures are arranged along a first direction, wherein the first direction D1 is a direction from the drain region to the source region and is parallel to the surface of the substrate. When each string of field plate structures is arranged in a straight line, the length extension direction of each string of field plate structures can be a second direction D2 that is substantially perpendicular to the first direction D1, and the second direction D2 is parallel to the surface of the substrate.

[0075] Optionally, each string of field plate structures is arranged in any of the following shapes: straight line, curved line, broken line, which may refer to the general shape of the projection of each string of field plate structures on a plane parallel to the surface of the substrate, that is, the general shape of the projection of multiple conductive contact field plate holes included in a string of field plate structures on a plane parallel to the surface of the substrate. Optionally, the curved line may be a wavy line or other types of curves. This application mainly takes the field plate structure generally arranged in a straight line as an example, but this does not constitute a limitation to this application.

[0076] In some embodiments, at least one series of field plate structures has a first projection in a plane parallel to the surface of the substrate, and the gate structure 201 has a second projection in a plane parallel to the surface of the substrate, and the first projection and the second projection are adjacent, such as Figure 2 , Figures 4 to 8 As shown, the adjacency may refer to the field plate structure being adjacent to, for example, the sidewall of the gate structure 201, or there being a gap between the first projection and the second projection, such as Figure 5 As shown, for example, the field plate structure is at a predetermined distance from the gate structure 201 , for example, the sidewall thereof, in a first direction ( D1 ).

[0077] Optionally, a projection shape of the plurality of conductive contact field plate holes in a plane parallel to the surface of the substrate is a combination of one or more of a circle, an ellipse, and a rectangle.

[0078] The size and shape of the conductive contact field plate hole can also be reasonably designed according to actual device requirements. In some embodiments, the plurality of conductive contact field plate holes included in at least one string of field plate structures have the same size in the first direction, for example, Figure 2 , Figure 3 , Figure 6 and Figure 7 As shown, multiple conductive contact field plate holes of the field plate structure in the same string have the same size in the first direction. For example, when the conductive contact field plate hole is a cylindrical hole, the size of the conductive contact field plate hole in the first direction may refer to the aperture of the conductive contact field plate hole. It is worth mentioning that the sizes and / or shapes of the conductive contact field plate holes of the field plate structures in different strings may be different or the same.

[0079] In some embodiments, at least some of the multiple conductive contact field plate holes included in at least one string of field plate structures have different sizes in the first direction. For example, some of the multiple conductive contact field plate holes in the field plate structures located in the same string have a first size, while another part of the conductive contact field plate holes have a second size, and the first size and the second size are different.

[0080] In some embodiments, Figures 3 to 8 As shown, the LDMOS device of the present application also includes a gate conductive contact hole 212, a drain region conductive contact hole 213 and a source region conductive contact hole 211, the gate conductive contact hole 212 is electrically connected to the gate structure 201, the drain region conductive contact hole 213 is electrically connected to the drain region, and the source region conductive contact hole 211 is electrically connected to the source region, wherein the aperture of the conductive contact field plate hole is greater than or equal to the aperture of the gate conductive contact hole 212, the aperture of the conductive contact field plate hole is greater than or equal to the aperture of the drain region conductive contact hole 213, and the aperture of the conductive contact field plate hole is greater than or equal to the aperture of the source region conductive contact hole 211. Through such an arrangement, the aperture of the conductive contact field plate hole can be close to the gate conductive contact hole 212, the drain region conductive contact hole 213 and the source region conductive contact, so that the aperture of the conductive contact field plate hole can be made equal to or larger than the size of the conductive contact hole, so that the field plate structure and the conductive contact hole can be formed simultaneously during the preparation of the LDMOS device, so that the size / morphology of the field plate structure can be more easily achieved to the target value, thereby ensuring the operating voltage and withstand voltage performance of the device and improving the yield of the device.

[0081] In some embodiments, the LDMOS device includes at least two series of field plate structures, wherein the aperture of the conductive contact field plate hole close to the gate structure 201 is larger than the aperture of the conductive contact field plate hole away from the gate structure 201, or, in other embodiments, the aperture of the conductive contact field plate hole close to the gate structure 201 is equal to the aperture of the conductive contact field plate hole away from the gate structure 201.

[0082] It is worth mentioning that when the top-view shape of the conductive contact field plate hole is an ellipse, that is, an elliptical cylinder, the aperture may refer to the size of the major axis of the ellipse, and when the top-view shape of the conductive contact field plate hole is a rectangle, the aperture may refer to the size in the first direction D1, for example, the size of the side length of the rectangle in the first direction.

[0083] In some embodiments, when the LDMOS device includes at least two strings of field plate structures, there are gaps between the field plate structures of adjacent strings, for example, Figure 2 As shown, the conductive contact field plate holes of the two series of field plate structures adjacent to each other in the first direction are spaced apart, and the spacing can be reasonably set according to actual needs.

[0084] In some other embodiments, when the LDMOS device includes at least two series of field plate structures, such as Figure 6 As shown, a series of field plate structures have multiple first conductive contact field plate holes 2091, and another series of field plate structures have multiple second conductive contact field plate holes 2092. The multiple first conductive contact field plate holes 2091 and the multiple second conductive contact field plate holes 2092 correspond one to one, and adjacent first conductive contact field plate holes 2091 and second conductive contact field plate holes 2092 are spaced apart from each other.

[0085] In some embodiments, Figure 7 As shown, at least two strings of field plate structures include a first string of field plate structures and a second string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes 2091, the second string of field plate structures includes a plurality of second conductive contact field plate holes 2092, and the plurality of first conductive contact field plate holes 2091 and the plurality of second conductive contact field plate holes 2092 are alternately arranged in the first direction.

[0086] In some embodiments, Figure 8 As shown, at least two strings of field plate structures include a first string of field plate structures, a second string of field plate structures and a third string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes 2091, the second string of field plate structures includes a plurality of second conductive contact field plate holes 2092, and the third string of field plate structures includes a plurality of third conductive contact field plate holes 2093, wherein the plurality of first conductive contact field plate holes 2091 and the plurality of second conductive contact field plate holes 2092 are arranged one-to-one in the first direction, and in the length extension direction of the first string of field plate structures and the second string of field plate structures, there is a first interval between adjacent first conductive contact field plate holes 2091 and a second interval between adjacent second conductive contact field plate holes 2092, the first interval and the second interval adjacent to each other in the first direction constitute a third interval, and one or more third conductive contact field plate holes 2093 are arranged in each third interval.

[0087] Optionally, the size of the third conductive contact field plate hole 2093 in the first direction is greater than the size of the first conductive contact field plate hole 2091, and the size of the third conductive contact field plate hole 2093 in the first direction is greater than the size of the second conductive contact field plate hole 2092. For example, the top-view shape of the conductive contact field plate hole is an ellipse or a circle or a rectangle, wherein when the top-view shape of the conductive contact field plate hole is an ellipse, the size in the first direction is the size of the major axis of the ellipse, that is, the major axis of the ellipse is parallel to the first direction D1, and when the top-view shape of the conductive contact field plate hole is a circle, the size in the first direction is the diameter of the circle, and when the top-view shape of the conductive contact field plate hole is a rectangle, the size in the first direction is the side length of the rectangle.

[0088] Optionally, a size of the third conductive contact field plate hole 2093 in the first direction is larger than a size in the second direction, wherein the second direction is perpendicular to the first direction and the second direction is parallel to the surface of the substrate.

[0089] It is worth mentioning that the aforementioned plurality of conductive contact field plate holes penetrate the interlayer dielectric layer and the barrier layer and are located on the field oxide layer.

[0090] The conductive contact field plate hole includes a conductive material, which may include a metal material or any other conductive material, and the metal material may include one or more of the following metal materials: W, Cu, Ag, Pt, Al, or other suitable metal materials. In some embodiments, the metal material includes W.

[0091] The gate conductive contact hole 212, the drain conductive contact hole 213, and the source conductive contact hole 211 also include conductive materials, which may include metal materials, or any other conductive materials, and the metal materials may include one or more of the following metal materials: W, Cu, Ag, Pt, Al, or other suitable metal materials. In some embodiments, the metal material includes W. It may be the same material as the conductive contact field plate hole, or a different material.

[0092] The description of some structures of the LDMOS device of the present invention has been completed so far. A complete LDMOS device may also include other structures, which will not be described one by one here.

[0093] In summary, the LDMOS device of the embodiment of the utility model includes at least one string of field plate structures, each string of field plate structures includes a plurality of conductive contact field plate holes. Since the conductive contact field plate holes are a hole-like structure, the morphology / size of the conductive contact holes (used to electrically connect to, for example, the drain region, the source region and the gate structure, respectively) are similar, so that the field plate structure and the conductive contact holes can be formed simultaneously during the preparation of the LDMOS device, and the size / morphology of the field plate structure can be made easier to reach the target value, thereby ensuring the operating voltage and withstand voltage performance of the device and improving the yield of the device.

[0094] Embodiment 2

[0095] Another embodiment of the present invention provides an electronic device, comprising the aforementioned LDMOS device.

[0096] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the semiconductor device. The electronic device of the embodiment of the utility model has better performance due to the use of the semiconductor device.

[0097] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present utility model. More particularly, within the scope of the present utility model disclosure, the accompanying drawings, and the appended claims, various modifications and changes may be made in the arrangement and / or components of the combined arrangement of the subject matter. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious choice for those skilled in the art.

Claims

1. An LDMOS device, characterized in that: include: substrate; A gate structure located on the surface of the substrate; A source region and a drain region extending from the surface of the substrate into the substrate and located on both sides of the gate structure; A field oxide layer, covering at least a portion of the surface of the drain region and extending to cover a portion of the surface of the gate structure near the drain region; At least one string of field plate structures, at least one string of the field plate structures is located on the field oxide layer and is arranged between the gate structure and the drain region, each string of the field plate structures includes a plurality of conductive contact field plate holes, the plurality of conductive contact field plate holes are arranged in a string in a plane parallel to the surface of the substrate, and there are gaps between adjacent conductive contact field plate holes in the length extension direction of at least one string of the field plate structures.

2. The LDMOS device according to claim 1, characterized in that It comprises at least two strings of field plate structures, and the at least two strings of the field plate structures are arranged along a first direction, wherein the first direction is a direction from the drain region to the source region and is parallel to the surface of the substrate.

3. The LDMOS device according to claim 1, characterized in that: Each string of field plate structures is arranged in any of the following shapes: straight line, curved line, or broken line.

4. The LDMOS device according to claim 1, wherein: At least one string of the field plate structures has a first projection in a plane parallel to the surface of the substrate, and the gate structure has a second projection in a plane parallel to the surface of the substrate, and the first projection and the second projection are adjacent, or there is a gap between the first projection and the second projection.

5. The LDMOS device according to claim 1, wherein: The multiple conductive contact field plate holes included in at least one string of the field plate structures have the same size in a first direction, or at least some of the multiple conductive contact field plate holes included in at least one string of the field plate structures have different sizes in the first direction, and the first direction is the direction from the drain region to the source region and is parallel to the surface of the substrate.

6. The LDMOS device according to claim 1, wherein: The projection shape of the plurality of conductive contact field plate holes in a plane parallel to the surface of the substrate is a combination of one or more of a circle, an ellipse and a rectangle.

7. The LDMOS device according to claim 1, characterized in that: It also includes a gate conductive contact hole, a drain region conductive contact hole and a source region conductive contact hole, wherein the gate conductive contact hole is electrically connected to the gate structure, the drain region conductive contact hole is electrically connected to the drain region, and the source region conductive contact hole is electrically connected to the source region, wherein: The aperture of the conductive contact field plate hole is greater than or equal to the aperture of the gate conductive contact hole, The aperture of the conductive contact field plate hole is greater than or equal to the aperture of the drain region conductive contact hole. The diameter of the conductive contact field plate hole is greater than or equal to the diameter of the source region conductive contact hole.

8. The LDMOS device according to claim 1, wherein: The LDMOS device includes at least two series of field plate structures, wherein the aperture of the conductive contact field plate hole close to the gate structure is larger than the aperture of the conductive contact field plate hole far from the gate structure.

9. The LDMOS device according to claim 1, wherein: When the LDMOS device includes at least two strings of field plate structures, there is a gap between the field plate structures of adjacent strings.

10. The LDMOS device according to claim 2, wherein: At least two strings of field plate structures include a first string of field plate structures, a second string of field plate structures and a third string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes, the second string of field plate structures includes a plurality of second conductive contact field plate holes, and the third string of field plate structures includes a plurality of third conductive contact field plate holes, wherein the plurality of first conductive contact field plate holes and the plurality of second conductive contact field plate holes are arranged one-to-one in the first direction, and in the length extension direction of the first string of field plate structures and the second string of field plate structures, there is a first interval between adjacent first conductive contact field plate holes and a second interval between adjacent second conductive contact field plate holes, the first interval and the second interval adjacent to each other in the first direction constitute a third interval, and one or more third conductive contact field plate holes are arranged in each of the third intervals.

11. The LDMOS device according to claim 10, characterized in that: The size of the third conductive contact field plate hole in the first direction is larger than that of the first conductive contact field plate hole, and the size of the third conductive contact field plate hole in the first direction is larger than that of the second conductive contact field plate hole.

12. The LDMOS device according to claim 10, wherein: The size of the third conductive contact field plate hole in the first direction is greater than that in a second direction, wherein the second direction is perpendicular to the first direction and the second direction is parallel to the surface of the substrate.

13. The LDMOS device according to claim 2, wherein: At least two strings of the field plate structures include a first string of field plate structures and a second string of field plate structures, the first string of field plate structures includes a plurality of first conductive contact field plate holes, the second string of field plate structures includes a plurality of second conductive contact field plate holes, and the plurality of first conductive contact field plate holes and the plurality of second conductive contact field plate holes are alternately arranged in the first direction.

14. The LDMOS device according to claim 1, wherein: Also includes: a barrier layer, the barrier layer covering the field oxide layer; An interlayer dielectric layer covers the surface of the substrate and the barrier layer, wherein a plurality of the conductive contact field plate holes penetrate the interlayer dielectric layer and the barrier layer.

15. An electronic device, characterized in that: The invention comprises the LDMOS device according to any one of claims 1 to 14.

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