Electronic ink screen, display substrate and electronic equipment

Abstract

The embodiment of the utility model provides an electronic ink screen, a display substrate and electronic equipment. The electronic ink screen comprises a first metal layer, a substrate layer, a second metal layer, a third metal layer and a driving chip, the first metal layer is located on one side of the substrate layer, and the second metal layer and the third metal layer are located on the other side of the substrate layer; the first metal layer comprises a plurality of first gate signal lines, the second metal layer comprises a plurality of second gate signal lines, and the third metal layer comprises a plurality of active signal lines; the substrate layer comprises a plurality of through holes, and each second gate signal line is connected with at least one first gate signal line through the through hole; the first grid signal line is connected with a grid signal end of the driving chip, and the active signal line is connected with an active signal end of the driving chip. Coupling pulling of the first grid signal line to the active signal line can be reduced, and the situation of diagonal bright lines is finally relieved.

Description

Technical Field

[0001] The utility model relates to the technical field of display equipment, in particular to an electronic ink screen, a display substrate and an electronic device. Background Art

[0002] With the gradual development of display device technology, ESL (Electronic Shelf Label) products are gradually occupying the mainstream display market. Among them, Reader products (electronic ink screen readers, referred to as Reader products) are narrow-border, high PPI (Pixels Per Inch) design products with huge potential market power.

[0003] In order to enhance the user's reading experience, today's electronic ink screens usually adopt a narrow frame and high pixel design. In order to achieve the narrow frame of the electronic ink screen, in the prior art, the electronic ink screen usually adopts DIA (Date fan-out In Active area) or GIA (Gate fan-out In Active area) wiring, and the integrated circuit data line lead-out end in the electronic ink screen adopts a fan-shaped wiring method, specifically as follows Figure 1 As shown in the figure: the gate signal line and the active signal line are fan-shaped, and the distance between the gate signal line and the active signal line is small, resulting in the active signal line being coupled and pulled by the gate signal line, resulting in the appearance of diagonal bright lines on the electronic ink screen, for example Figure 2 and Figure 3 As shown, the display effect of the electronic ink screen is poor. Utility Model Content

[0004] The purpose of the embodiment of the utility model is to provide an electronic ink screen, a display substrate and an electronic device to alleviate the situation of diagonal bright lines and improve the display effect of the electronic ink screen. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the utility model provides an electronic ink screen, comprising:

[0006] A first metal layer, a base layer, a second metal layer, a third metal layer and a driving chip;

[0007] The first metal layer is located on one side of the base layer, and the second metal layer and the third metal layer are located on the other side of the base layer;

[0008] The first metal layer includes a plurality of first gate signal lines, the second metal layer includes a plurality of second gate signal lines, and the third metal layer includes a plurality of active signal lines;

[0009] The base layer comprises a plurality of through holes, and each of the second gate signal lines is connected to at least one first gate signal line through the through holes;

[0010] The first gate signal line is connected to the gate signal terminal of the driving chip, and the active signal line is connected to the active signal terminal of the driving chip.

[0011] In a possible implementation, the base layer is a glass base layer, the through hole is filled with gate metal or source and drain metal, and the first gate signal line and the second gate signal line are arranged vertically.

[0012] In a possible implementation, the electronic ink screen further includes: a first insulating layer and a second insulating layer;

[0013] The first insulating layer is disposed between the first metal layer and the base layer, and the first insulating layer does not affect the connection between the first gate signal line and the second gate signal line;

[0014] The second insulating layer is disposed on a side of the second metal layer away from the base layer.

[0015] In a possible implementation, the electronic ink screen further includes: a first passivation layer and a second passivation layer;

[0016] The first passivation layer is disposed on a side of the first metal layer away from the base layer, and the second passivation layer is disposed on a side of the second insulating layer away from the base layer.

[0017] In a possible implementation, the electronic ink screen further includes: a first protective film layer, wherein the first protective film layer is disposed on a side of the first passivation layer away from the base layer.

[0018] In a possible implementation manner, the first gate signal line is arranged between the through hole and a gate signal terminal of the driving chip.

[0019] In a possible implementation, each of the first gate signal lines in the fan-out region is connected to the gate signal terminal of the driver chip by right-angle wiring, and each of the active signal lines in the fan-out region is connected to the active signal terminal of the driver chip by fan-shaped wiring.

[0020] In a possible implementation, each of the first gate signal lines in the fan-out region is connected to the gate signal terminal of the driver chip by fan-shaped wiring, and each of the active signal lines in the fan-out region is connected to the active signal terminal of the driver chip by right-angle wiring.

[0021] In a possible embodiment, the driving chip includes a first driving chip and a second driving chip, the first driving chip is arranged on a first edge side of the electronic ink screen, the second driving chip is arranged on a second edge side of the electronic ink screen, a first distance between the first driving chip and the first edge side is less than half of a third distance, a second distance between the second driving chip and the second edge side is less than half of the third distance, and the third distance is the distance between the first driving chip and the second driving chip.

[0022] In a possible implementation, along the signal transmission direction of the first gate signal line, after the first gate signal line passes through the through hole, the first gate signal line is broken.

[0023] In a second aspect, an embodiment of the utility model provides a display substrate, comprising:

[0024] A first metal layer, a base layer, a second metal layer, and a third metal layer;

[0025] The first metal layer is located on one side of the base layer, and the second metal layer and the third metal layer are located on the other side of the base layer;

[0026] The first metal layer includes a plurality of first gate signal lines, the second metal layer includes a plurality of second gate signal lines, and the third metal layer includes a plurality of active signal lines;

[0027] The base layer comprises a plurality of through holes, and each of the second gate signal lines is connected to at least one first gate signal line through the through holes;

[0028] The first gate signal line is used to connect to the gate signal terminal of the driving chip, and the active signal line is used to connect to the active signal terminal of the driving chip.

[0029] In a possible implementation, the base layer is a glass base layer, the through hole is filled with gate metal or source and drain metal, and the first gate signal line and the second gate signal line are arranged vertically.

[0030] In a possible implementation, the electronic ink screen further includes: a first insulating layer and a second insulating layer;

[0031] The first insulating layer is disposed between the first metal layer and the base layer, and the first insulating layer does not affect the connection between the first gate signal line and the second gate signal line;

[0032] The second insulating layer is disposed on a side of the second metal layer away from the base layer.

[0033] In a possible implementation, the electronic ink screen further includes: a first passivation layer and a second passivation layer;

[0034] The first passivation layer is disposed on a side of the first metal layer away from the base layer, and the second passivation layer is disposed on a side of the second insulating layer away from the base layer.

[0035] In a possible implementation, the electronic ink screen further includes: a first protective film layer, wherein the first protective film layer is disposed on a side of the first passivation layer away from the base layer.

[0036] In a possible implementation manner, the first gate signal line is arranged between the through hole and a gate signal terminal of the driving chip.

[0037] In a possible implementation, along the signal transmission direction of the first gate signal line, after the first gate signal line passes through the through hole, the first gate signal line is broken.

[0038] In a third aspect, an embodiment of the utility model provides an electronic device, including any electronic ink screen described in the utility model.

[0039] Beneficial effects of the embodiments of the utility model:

[0040] The embodiment of the utility model provides an electronic ink screen, a display substrate and an electronic device, wherein the electronic ink screen comprises: a first metal layer, a base layer, a second metal layer, a third metal layer and a driving chip; the first metal layer is located on one side of the base layer, and the second metal layer and the third metal layer are located on the other side of the base layer; the first metal layer comprises a plurality of first gate signal lines, the second metal layer comprises a plurality of second gate signal lines, and the third metal layer comprises a plurality of active signal lines; the base layer comprises a plurality of through holes, and each second gate signal line is connected to at least one first gate signal line through the through hole; the first gate signal line is connected to the gate signal terminal of the driving chip, and the active signal line is connected to the active signal terminal of the driving chip. The first gate signal line is connected to the second gate signal line through the through hole. Since the first gate signal line and the active signal line are wired on different sides of the base layer, the distance between the first gate signal line and the active signal line is increased, thereby reducing the coupling pull of the first gate signal line on the active signal line, and finally alleviating the diagonal bright line situation.

[0041] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0043] Figure 1 It is a wiring method of the fan-out area in the related technology;

[0044] Figure 2 A schematic diagram of diagonal bright lines of an electronic ink screen in the related art;

[0045] Figure 3 Another schematic diagram of diagonal bright lines of an electronic ink screen in the related art;

[0046] Figure 4 This is a first schematic diagram of an electronic ink screen according to an embodiment of the utility model;

[0047] Figure 5 This is a first schematic diagram of a through hole in an electronic ink screen according to an embodiment of the utility model;

[0048] Figure 6 This is a second schematic diagram of the electronic ink screen of an embodiment of the utility model;

[0049] Figure 7 This is a third schematic diagram of the electronic ink screen of an embodiment of the present utility model;

[0050] Figure 8 A second schematic diagram of a through hole in an electronic ink screen according to an embodiment of the utility model;

[0051] Fig. 9 A third schematic diagram of a through hole in an electronic ink screen according to an embodiment of the present utility model;

[0052] Fig.10 A fourth schematic diagram of a through hole in an electronic ink screen according to an embodiment of the present utility model;

[0053] Fig.11 This is a first wiring method for active signal lines and first gate signal lines in the electronic ink screen of the embodiment of the utility model;

[0054] Fig.12 This is a second wiring method for the active signal line and the first gate signal line in the electronic ink screen of the embodiment of the utility model;

[0055] Fig.13 This is a schematic diagram of the positions of the first driver chip and the second driver chip in the electronic ink screen of an embodiment of the utility model;

[0056] Fig.14 This is a fourth schematic diagram of the electronic ink screen according to an embodiment of the present utility model;

[0057] Fig.15 This is a fifth schematic diagram of the electronic ink screen according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the utility model.

[0059] The electronic ink screen is also known as electronic paper. Its display part is composed of two substrates, which are coated with an electronic ink composed of countless tiny transparent particles. The particles are formed by many different colored particles with positive and negative charges sealed in internal liquid microcapsules. Charged particles of different colors will move in different directions due to the different applied electric fields, presenting different display effects on the surface of the display.

[0060] In the related art, in order to achieve a narrow frame of the electronic ink screen, an in-plane wiring design is adopted, the data signal line and the gate signal line are connected through vias, and the vias are arranged along the diagonal direction of the pixel; the gate signal line and the active signal line connect the driver chip and the display area, see Figure 1 As shown, in the Fanout area, the gate signal lines and Source lines (active signal lines) are both fan-shaped and arranged side by side. The distance between the two is small, and the active signal lines are easily coupled and pulled by the gate signal lines. At the same time, since the vias are arranged along the diagonal direction of the pixels, diagonal bright line problems are prone to occur, that is, diagonal bright lines appear in the AA area (display area) of the electronic ink screen, affecting the user experience.

[0061] In order to reduce the generation of diagonal bright lines and improve the user experience, the embodiment of the utility model provides an electronic ink screen and a display substrate, which are described in detail below:

[0062] In the first aspect, the first schematic diagram of the electronic ink screen of the embodiment of the utility model is shown in FIG. Figure 4 , the electronic ink screen comprises:

[0063] A first metal layer 101, a base layer 102, a second metal layer 103, a third metal layer 104 and a driving chip 105;

[0064] The first metal layer 101 is located on one side of the base layer 102, and the second metal layer 103 and the third metal layer 104 are located on the other side of the base layer 102;

[0065] The first metal layer 101 includes a plurality of first gate signal lines 1011, the second metal layer 103 includes a plurality of second gate signal lines 1031, and the third metal layer 104 includes a plurality of active signal lines 1041;

[0066] The base layer 102 includes a plurality of through holes 1021 , and each of the second gate signal lines 1031 is connected to at least one first gate signal line 1011 through the through hole 1021 ;

[0067] The first gate signal line 1011 is connected to a gate signal terminal of the driving chip 105 , and the active signal line 1041 is connected to an active signal terminal of the driving chip 105 .

[0068] See also Figure 4 , is a cross-sectional schematic diagram of the electronic ink screen of an embodiment of the utility model, in which the first gate signal line 1011 and the active signal line 1041 are led out from the display area of ​​the electronic ink screen and connected to the driver chip 105 through the fan-out area. The active signal line 1041 is arranged in the third metal layer 104, but because the active signal line 1041 is not arranged directly above the cross-sectional surface of the through hole 1021, the part of the active signal line 1041 in the third metal layer 104 is not shown in the cross-sectional schematic diagram, and only the part of the active signal line 1041 in the fan-out area is illustrated. Other film layers may also be included between the second metal layer 103 and the third metal layer 104, such as an insulating layer, a planarization layer, etc., which can be specifically arranged according to actual needs. Among them, the first gate signal line 1011 and the second gate signal line 1031 are used to transmit Gate signals, and the active signal line 1041 is used to transmit Source signals.

[0069] In the embodiment of the utility model, the first gate signal line 1011 and the second gate signal line 1031 are connected through the through hole 1021 of the substrate layer 102, so that the first gate signal line 1011 transmits the Gate signal to the second gate signal line 1031 to realize the normal provision of the Gate signal. Since the first gate signal line 1011 and the active signal line 1041 are wired on different sides of the substrate layer 102, compared with the scheme in the prior art in which the gate signal and the active signal line are wired on the same side of the substrate layer, the distance between the first gate signal line 1011 and the active signal line 1041 drawn out of the fan-out area in the utility model embodiment is larger, which can reduce the coupling between the first gate signal line and the active signal line, and reduce the coupling pull of the gate signal line to the active signal line, thereby reducing the generation of diagonal bright lines. At the same time, because the first gate signal line 1011 and the active signal line 1041 are wired on different sides of the substrate layer 102, the wiring space is also larger, the wiring design becomes simpler, and the cost of the fan-out area wiring design is reduced.

[0070] The substrate layer 102 can be made of common substrate materials, such as polyimide or glass. Figure 5 , Figure 5 The schematic diagram of the partial enlargement of the through hole 1021 in the embodiment of the utility model, the substrate layer 102 is specifically a glass substrate layer, the through hole 1021 can be prepared by TGV (Through Glass Via) technology, and the through hole 1021 can be filled with gate metal or source and drain metal to realize the transmission of the gate signal between the first gate signal line 1011 and the second gate signal line 1031. Figure 5 As shown, in the embodiment of the utility model, the first gate signal line 1011 and the second gate signal line 1031 are arranged vertically, and the second gate signal line 1031 is used to provide a Gate signal for a pixel row in the electronic ink screen, so the second gate signal line 1031 can be wired along the row direction, and when the fan-out area is located on one side of the column direction, the first gate signal line 1011 needs to be wired and led out along the column direction, so the first gate signal line 1011 and the second gate signal line 1031 are arranged vertically, for example Figure 6 In other embodiments, when the fan-out region is located on one side of the row direction, the first gate signal line 1011 needs to be routed out along the row direction. In this case, the first gate signal line 1011 and the second gate signal line 1031 are arranged in the same direction, for example Figure 7 The wiring direction of the active signal line 1041 can be set according to actual requirements. Generally, the active signal line 1041 is arranged along the row direction, that is, the active signal line 1041 and the second gate signal line 1031 are arranged vertically.

[0071] In order to reduce the influence of the Gate signal in the first gate signal line 1011 and the second gate signal line 1031 on other signal lines, in a possible implementation manner, see Figure 8 , the electronic ink screen further includes: a first insulating layer 106 and a second insulating layer 107;

[0072] The first insulating layer 106 is disposed between the first metal layer 101 and the base layer 102, and the first insulating layer 106 does not affect the connection between the first gate signal line 1011 and the second gate signal line 1031;

[0073] The second insulating layer 107 is disposed on a side of the second metal layer 103 away from the base layer 102 .

[0074] In the embodiment of the utility model, the first insulating layer 106 and the second insulating layer 107 are made of insulating materials, such as polyimide, etc. The first insulating layer 106 and the second insulating layer 107 provide electrical isolation, protect the circuit, reduce circuit short circuits, and isolate the external environment from pollution and damage to the signal line.

[0075] In order to protect the first gate signal line 1011 and the second gate signal line 1031 from being corroded by water and oxygen, in a possible implementation manner, see Fig. 9 , the electronic ink screen further includes: a first passivation layer 108 and a second passivation layer 109;

[0076] The first passivation layer 108 is disposed on a side of the first metal layer 101 away from the base layer 102 , and the second passivation layer 109 is disposed on a side of the second insulating layer 107 away from the base layer 102 .

[0077] In the embodiment of the present invention, the passivation layers 108 and 109 are usually made of inorganic materials to protect the internal circuits, block the entry of water and oxygen, and prevent the oxidation of the signal lines.

[0078] In order to prevent the side of the electronic ink screen where the first gate signal line 1011 is located from being affected by collision, in a possible implementation manner, see Fig.10 The electronic ink screen further includes: a first protective film layer 110 , and the first protective film layer 110 is arranged on a side of the first passivation layer 108 away from the base layer 102 .

[0079] Fig.10This is a second schematic diagram of the electronic ink screen of the embodiment of the utility model. The bonding adhesive layer is used for bonding and assembling. The electrophoretic liquid in the transparent electrophoretic liquid layer 111 generates specific text or images according to the change of the electrical signal. Generally, the bonding adhesive and the transparent electrophoretic liquid layer 111 also include an electrode layer (not shown in the figure). The electrode layer and the transparent electrode layer 112 are used to provide the transparent electrophoretic liquid layer 111 with the voltage signal required for display. The transparent electrode layer 112 is made of a transparent conductive material, such as ITO (indium tin oxide). A protective film layer (not shown in the figure) can also be provided on the transparent electrode layer 112 to protect the transparent electrode layer 112.

[0080] In one possible implementation, see Figure 5 The first gate signal line 1011 is arranged between the through hole 1021 and the gate signal terminal of the driving chip 105 .

[0081] In the embodiment of the utility model, the first gate signal line 1011 is connected to the second gate signal line 1031 through the through hole 1021, and the Gate signal is transmitted to the second gate signal line 1031 through the through hole 1021. Therefore, the first gate signal line 1011 does not need to run through the entire display area, and is only arranged between the through hole 1021 and the gate signal terminal of the driving chip 105, thereby reducing the length of the first gate signal line 1011, saving gate metal materials, and reducing the coupling of the first gate signal line 1011 to the pixel, thereby reducing the generation of diagonal bright lines. In addition, the active signal line 1041 is located on the other side of the substrate layer 102, avoiding the coupling caused by the first gate signal line 1011 and the active signal line 1041 being too close, thereby reducing the generation of diagonal bright lines.

[0082] In addition to increasing the distance between the first gate signal line 1011 and the active signal line 1041 in a direction perpendicular to the electronic ink screen, the distance between the first gate signal line 1011 and the active signal line 1041 may also be increased in a direction parallel to the electronic ink screen. Fig.11 Each of the first gate signal lines 1011 in the fan-out area is connected to the gate signal terminal of the driver chip 105 by a right-angle wiring method, and each of the active signal lines 1041 in the fan-out area is connected to the active signal terminal of the driver chip 105 by a fan-shaped wiring method.

[0083] In the embodiment of the utility model, in the fan-out region, the first gate signal line 1011 is not Figure 1 The traditional fan-out wiring method shown in FIG. 1 is replaced by a right-angle wiring method; and the active signal line 1041 still adopts the fan-out wiring method. Figure 1The gate signal lines and active signal lines shown are all arranged in a fan-shaped manner. In the embodiment of the utility model, the wiring method of the first gate signal line 1011 and the active signal line 1041 in the fan-out area increases the distance between the first gate signal line 1011 and the active signal line 1041, thereby reducing the coupling disturbance between the first gate signal line 1011 and the active signal line 1041, and ultimately reducing the generation of diagonal bright lines.

[0084] In addition to increasing the distance between the first gate signal line 1011 and the active signal line 1041 in a direction perpendicular to the electronic ink screen, the distance between the first gate signal line 1011 and the active signal line 1041 may also be increased in a direction parallel to the electronic ink screen. Fig.12 Each of the first gate signal lines 1011 in the fan-out area is connected to the gate signal terminal of the driver chip 105 by fan-shaped wiring, and each of the active signal lines 1041 in the fan-out area is connected to the active signal terminal of the driver chip 105 by right-angle wiring.

[0085] In the embodiment of the present invention, in the fan-out region, the active signal line 1041 is not Figure 1 The conventional fan-shaped wiring method shown in FIG. 1 is replaced by a right-angle wiring method; and the first gate signal line 1011 still adopts the fan-shaped wiring method. Figure 1 The gate signal lines and active signal lines shown are all arranged in a fan-shaped manner. In the embodiment of the utility model, the wiring method of the first gate signal line 1011 and the active signal line 1041 in the fan-out area increases the distance between the first gate signal line 1011 and the active signal line 1041, thereby reducing the coupling disturbance between the first gate signal line 1011 and the active signal line 1041, and ultimately reducing the generation of diagonal bright lines.

[0086] In addition to increasing the distance between the first gate signal line 1011 and the active signal line 1041 in a direction perpendicular to the electronic ink screen, the distance between the first gate signal line 1011 and the active signal line 1041 may also be increased in a direction parallel to the electronic ink screen. Fig.13 The driving chip 105 includes a first driving chip 1051 and a second driving chip 1052. The first driving chip 1051 is arranged on a first edge side of the electronic ink screen, and the second driving chip 1052 is arranged on a second edge side of the electronic ink screen. A first distance d1 between the first driving chip 1051 and the first edge side is less than half of a third distance d3, and a second distance d2 between the second driving chip 1052 and the second edge side is less than half of the third distance d3. The third distance d3 is the distance between the first driving chip 1051 and the second driving chip 1052.

[0087] In the embodiment of the utility model, by increasing the distance between the first driver chip 1051 and the second driver chip 1052, the wiring space between the first gate signal line 1011 and the active signal line 1041 in the fan-out area is increased, so that the distance between the first gate signal line 1011 and the active signal line 1041 can be increased, thereby reducing the coupling disturbance of the first gate signal line 1011 to the active signal line 1041, thereby reducing the generation of diagonal bright lines.

[0088] In order to further reduce the coupling pull of the first gate signal line 1011 on the pixel, in a possible implementation manner, see Fig.14 , along the signal transmission direction of the first gate signal line 1011 , after the first gate signal line 1011 passes through the through hole 1021 , the first gate signal line 1011 is broken.

[0089] In the display area, the first gate signal line 1011 and the second gate signal line 1031 are overlapped through the through hole 1021. After the first gate signal line 1011 transmits the Gate signal to the second gate signal line 1031 of the corresponding row, if there is still a Gate signal remaining to continue to be transmitted along the first gate signal line 1011, the remaining Gate signal will still pull the surrounding Pixels (pixels), thereby aggravating the bright line of the object. In the embodiment of the utility model, along the transmission direction of the Gate signal of the first gate signal line 1011, after the first gate signal line 1011 passes through the through hole 1021, the first gate signal line 1011 is cut off, that is, the remaining metal routing after the through hole 1021 is overlapped is interrupted. It can not only ensure that the electronic ink screen completes the transmission of the Gate signal at the position of the through hole 1021, but also block the continued transmission of the Gate signal, so that at the same time as achieving the purpose of display, a non-penetrating Gate signal line is formed in the surface to reduce the coupling pull of the Gate signal on the Pixel, and finally reduce the generation of diagonal bright lines.

[0090] The stacking structure of the pixel area in the electronic ink screen can be customized according to actual conditions. In one example, the stacking structure diagram of the pixel area can be as follows: Fig.15 As shown, it includes: a base layer 102, a second gate signal line 1031, a second insulating layer 107, an active signal line 1041, a source-drain structure 114, a second passivation layer 109, a first electrode layer 113, a transparent electrophoretic liquid layer 111, and a transparent electrode layer 112, wherein the source-drain structure 114 can be prepared using source-drain metal, and the first electrode layer 113 can be prepared using indium tin oxide.

[0091] In a second aspect, an embodiment of the utility model further provides a display substrate, the display substrate comprising:

[0092] A first metal layer 101, a base layer 102, a second metal layer 103, and a third metal layer 104;

[0093] The first metal layer 101 is located on one side of the base layer 102, and the second metal layer 103 and the third metal layer 104 are located on the other side of the base layer 102;

[0094] The first metal layer 101 includes a plurality of first gate signal lines 1011, the second metal layer 103 includes a plurality of second gate signal lines 1031, and the third metal layer 104 includes a plurality of active signal lines 1041;

[0095] The base layer 102 includes a plurality of through holes 1021 , and each of the second gate signal lines 1031 is connected to at least one first gate signal line 1011 through the through hole 1021 ;

[0096] The first gate signal line 1011 is used to connect to the gate signal terminal of the driving chip 105 , and the active signal line 1041 is used to connect to the active signal terminal of the driving chip 105 .

[0097] In a possible implementation, the base layer 102 is a glass base layer, the through hole 1021 is filled with gate metal or source-drain metal, and the first gate signal line 1011 and the second gate signal line 1031 are arranged vertically.

[0098] In a possible implementation, the electronic ink screen further includes: a first insulating layer 106 and a second insulating layer 107;

[0099] The first insulating layer 106 is disposed between the first metal layer 101 and the base layer 102, and the first insulating layer 106 does not affect the connection between the first gate signal line 1011 and the second gate signal line 1031;

[0100] The second insulating layer 107 is disposed on a side of the second metal layer 103 away from the base layer 102 .

[0101] In a possible implementation, the electronic ink screen further includes: a first passivation layer 108 and a second passivation layer 109;

[0102] The first passivation layer 108 is disposed on a side of the first metal layer 101 away from the base layer 102 , and the second passivation layer 109 is disposed on a side of the second insulating layer 107 away from the base layer 102 .

[0103] In a possible implementation, the electronic ink screen further includes: a first protective film layer 110 , where the first protective film layer 110 is disposed on a side of the first passivation layer 108 away from the base layer 102 .

[0104] In a possible implementation manner, the first gate signal line 1011 is arranged between the through hole 1021 and the gate signal terminal of the driving chip 105 .

[0105] In a possible implementation, along the signal transmission direction of the first gate signal line 1011 , after the first gate signal line 1011 passes through the through hole 1021 , the first gate signal line 1011 is broken.

[0106] In a third aspect, an embodiment of the utility model provides an electronic device, including any electronic ink screen described in the utility model.

[0107] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0108] Each embodiment in this specification is described in a related manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. An electronic ink screen, characterized in that: include: A first metal layer, a base layer, a second metal layer, a third metal layer and a driving chip; The first metal layer is located on one side of the base layer, and the second metal layer and the third metal layer are located on the other side of the base layer; The first metal layer includes a plurality of first gate signal lines, the second metal layer includes a plurality of second gate signal lines, and the third metal layer includes a plurality of active signal lines; The base layer comprises a plurality of through holes, and each of the second gate signal lines is connected to at least one first gate signal line through the through holes; The first gate signal line is connected to the gate signal terminal of the driving chip, and the active signal line is connected to the active signal terminal of the driving chip.

2. The electronic ink screen according to claim 1, characterized in that: The base layer is a glass base layer, the through hole is filled with gate metal or source and drain metal, and the first gate signal line and the second gate signal line are arranged vertically.

3. The electronic ink screen according to claim 1, characterized in that: The electronic ink screen further includes: a first insulating layer and a second insulating layer; The first insulating layer is disposed between the first metal layer and the base layer, and the first insulating layer does not affect the connection between the first gate signal line and the second gate signal line; The second insulating layer is disposed on a side of the second metal layer away from the base layer.

4. The electronic ink screen according to claim 3, characterized in that: The electronic ink screen further includes: a first passivation layer and a second passivation layer; The first passivation layer is disposed on a side of the first metal layer away from the base layer, and the second passivation layer is disposed on a side of the second insulating layer away from the base layer.

5. The electronic ink screen according to claim 4, characterized in that: The electronic ink screen further includes: a first protective film layer, which is arranged on a side of the first passivation layer away from the base layer.

6. The electronic ink screen according to claim 1, characterized in that: The first gate signal line is arranged between the through hole and the gate signal terminal of the driving chip.

7. The electronic ink screen according to claim 1, characterized in that: Each of the first gate signal lines in the fan-out region is connected to the gate signal terminal of the driver chip by a right-angle wiring method, and each of the active signal lines in the fan-out region is connected to the active signal terminal of the driver chip by a fan-shaped wiring method.

8. The electronic ink screen according to claim 1, characterized in that: Each of the first gate signal lines in the fan-out region is connected to the gate signal terminal of the driver chip in a fan-shaped wiring manner, and each of the active signal lines in the fan-out region is connected to the active signal terminal of the driver chip in a right-angle wiring manner.

9. The electronic ink screen according to claim 1, characterized in that: The driving chip includes a first driving chip and a second driving chip, the first driving chip is arranged on a first edge side of the electronic ink screen, the second driving chip is arranged on a second edge side of the electronic ink screen, a first distance between the first driving chip and the first edge side is less than half of a third distance, a second distance between the second driving chip and the second edge side is less than half of the third distance, and the third distance is the distance between the first driving chip and the second driving chip.

10. The electronic ink screen according to claim 1, characterized in that: Along the signal transmission direction of the first gate signal line, after the first gate signal line passes through the through hole, the first gate signal line is broken.

11. A display substrate, characterized in that: include: A first metal layer, a base layer, a second metal layer, and a third metal layer; The first metal layer is located on one side of the base layer, and the second metal layer and the third metal layer are located on the other side of the base layer; The first metal layer includes a plurality of first gate signal lines, the second metal layer includes a plurality of second gate signal lines, and the third metal layer includes a plurality of active signal lines; The base layer comprises a plurality of through holes, and each of the second gate signal lines is connected to at least one first gate signal line through the through holes; The first gate signal line is used to connect to the gate signal terminal of the driving chip, and the active signal line is used to connect to the active signal terminal of the driving chip.

12. An electronic device, characterized in that: The electronic ink screen comprises any one of claims 1 to 10.

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