Semiconductor device and manufacturing method thereof

a semiconductor and film technology, applied in semiconductor devices, capacitors, electrical devices, etc., can solve the problems of reducing the reliability of the insulation film, increasing the consumption power, and increasing the consumption power of the gate insulation film

Inactive Publication Date: 2007-01-04
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, it is considered that the gate insulation film using silicon dioxide (SiO2) is limited to a film thickness of 2.0 nm or less at the cost of increasing the consumption power and lowering reliability of the insulation film due to increase a direct tunnel leakage current.
Further, since a diffusion barrier to impurities is weakened in such thin SiO2, it brings about leakage of impurities from a gate electrode.
Further, since the mobility of electrons is small which is about ¼ compared with a universal curve of an SiO2 film (general curve giving effective field effect dependence of mobility), the source-drain current upon operating FET can not be increased as expected.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

embodiment 1

[0055]FIG. 1 is a cross-sectional view of a completed semiconductor device according to a first embodiment of this invention and FIG. 12 and FIG. 13 are cross-sectional views showing the sequence of production steps thereof.

[0056] A semiconductor substrate 1 comprising single crystalline Si of crystal orientation (100), P-conductivity type and 20 cm diameter was formed with an inter-device isolation region (not illustrated) for defining an active region and applied with ion implantation of P-conductivity type ions for controlling the substrate concentration, heat treatment time, ion implantation (for controlling the threshold voltage and the source-drain activating heat treatment by known methods). Then, an Al2O3 film of 1.0 nm thick was deposited at 350° C. by an atom layer deposition CVD method (ALCVD method) using trimethyl aluminum [Al(CH3)3] as a starting material gas and H2O as an oxidizing gas. Further, an SiO2 film was formed to 0.5 nm thickness in the same apparatus by the...

embodiment 2

[0065]FIG. 2 is a cross-sectional view showing a completed field effect transistor according to a second embodiment of this invention, and FIG. 14 and FIG. 15 are schematic views for the production steps thereof. In the field effect transistor according to this Example 2, a high melting metal gate was applied instead of the polycrystalline silicon gate.

[0066] A semiconductor substrate 1 comprising single crystalline Si having crystal orientation (100), P-conductivity type and of 20 cm diameter was formed with an inter-device isolation region (not illustrated) for defining an active region and applied with implantation of P-conductivity type ions for controlling the substrate concentration, extended heat treatment time, and ion implantation for controlling the threshold voltage and activating heat treatment by known methods. Subsequently, an Al2O3 film was formed to a thickness of 1.5 nm by an ECR sputtering method. The ECR sputtering method is as shown in Example 1. However, sputte...

embodiment 3

[0071]FIG. 3 is a cross sectional view showing a completed field effect transistor in a third embodiment according to this invention and FIG. 16 to FIG. 20 are schematic views for manufacturing steps thereof. In a field effect transistor of this Embodiment 3, an activating heat treatment was applied for implanted ions before formation of the gate insulation film thereby mitigating the thermal load on a high dielectric insulation film.

[0072] A semiconductor substrate 1 comprising single crystalline Si having crystal orientation (100), P-conductivity type and of 20 cm diameter was applied with formation of the inter-device isolation region (not illustrated) for defining an active region, implantation of P-conductivity type ions for controlling the substrate concentration, heat treatment time, and ion implantation (for controlling the threshold voltage and an activating heat treatment by known methods), and then a thermal oxide film 14 was formed to 5 nm thickness. Then, after deposit...

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Abstract

In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to 1 / 100 or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Continuation application of U.S. application Ser. No. 10 / 900,430 filed Jul. 28, 2004, which is a Continuation application of U.S. application Ser. No. 10 / 216,792 filed Aug. 13, 2002. Priority is claimed based on U.S. application Ser. No. 10 / 900,430 filed Jul. 28, 2004, which claims the priority of U.S. application Ser. No. 10 / 216,792 filed Aug. 13, 2002, which claims the priority of Japanese Patent Application No. 2001-255454 filed on Aug. 27, 2001, all of which is incorporated by reference.FIELD OF THE INVENTION [0002] This invention concerns a semiconductor device and a manufacturing method thereof and, more in particular, it relates to a semiconductor device having a field effect transistor in which a high dielectric film is applied to a gate insulation film for use in a field effect transistor, as well as a manufacturing method thereof. BACKGROUND OF THE INVENTION [0003] MOS transistors as a basic constituent ci...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L29/94H01L21/02H01L21/28H01L21/316H01L21/318H01L21/336H01L29/423H01L29/43H01L29/49H01L29/51H01L29/78
CPCH01L21/0214H01L29/66545H01L21/02178H01L21/02266H01L21/02323H01L21/02329H01L21/02337H01L21/28061H01L21/28185H01L21/28194H01L21/28202H01L21/28211H01L21/3141H01L21/3143H01L21/31612H01L21/3162H01L21/31641H01L21/31645H01L28/56H01L29/4983H01L29/513H01L29/517H01L29/518H01L29/665H01L21/02164
InventorSHIMAMOTO, YASUHIROOBATA, KATSUNORITORII, KAZUYOSHIHIRATANI, MASAHIKO
OwnerRENESAS TECH CORP