Internet security and acceleration (ISA) interface internet protocol (IP) core based on processor local bus (PLB)
A bus and interface technology, applied in the field of ISA interface IP core, can solve the problems of low speed, reusable and upgradeable complex logic control, difficult implementation, etc., achieve low power consumption, free expansion of modules, and reduce operating burden Effect
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2015-03-11
Smart Images
Figure 1 Figure 2 Figure 3
Abstract
Description
technical field
[0001] The invention belongs to the field of mobile robots, in particular to an ISA interface IP core based on a PLB bus. Background technique
[0002] In the field of mobile robots, PC104 is usually used to control motors or sensors. Due to the design characteristics of PC104 itself, it cannot directly control the motor. Therefore, the information exchange between PC104 and the motor requires an intermediate link, which is the interface board. At present, the microcontroller (MCU) module is usually used as the interface board, that is, the control method of PC104+microcontroller+motor (or sensor), the problems of this control method are: 1. The programming language of MCU is mainly C language , implemented by soft logic, it implements specific functions by sequentially executing instructions, which cannot avoid the disadvantage of low speed; 2. The feature that MCU can only process one instruction at a time also affects its application, and it can only be u...
Examples
Embodiment Construction
[0024] Embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings:
[0025] A kind of ISA interface IP core based on PLB bus, such as figure 1 As shown in the figure, it includes a decoder, a dual-port RAM, a register array, a read-write state machine, a logic judgment module and a user logic module; the decoder is connected to the user logic module through a control line, and the decoder is connected to the dual port through an address line. The RAM is connected with the register array; one end of the user logic module is connected with the PLB bus, and the other end of the user logic module is connected with the dual-port RAM and the register array respectively through the bidirectional data line; the input end of the read-write state machine is connected with the ISA bus. IO read and write signal (IOR, IOW signal), DMA control signal (AEN signal), clock signal (CLK signal) are connected, and the control signal (W...