Motor control device

Abstract

The present invention provides a motor control device, which includes: a noise reduction unit, which sets a PWM count for a unit PWM cycle of a PWM cycle in such a way that, in each PWM cycle within a current control cycle, a current flowing in a frame ground due to a phase voltage of any one of three phases is offset by a current flowing in the frame ground due to a phase voltage of any one of the other two phases; and a noise elimination circuit, which is used to generate a current of an opposite phase to a current flowing in a frame ground due to a phase voltage of another phase of the other two phases in each PWM cycle within the current control cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Japanese Patent Application No. 2018-088408 filed on May 1, 2018, the entire contents of which are hereby incorporated by reference. Technical Field

[0003] The present invention relates to a motor control device for driving an electric motor using PWM (Pulse Width Modulation). Background Art

[0004] In a motor control device that performs vector control on a three-phase electric motor, a two-phase current command value is calculated for each current control cycle. A two-phase voltage command value is calculated based on the deviation between the two-phase current command value and the two-phase current detection value. The two-phase voltage command value is converted into two-phase / three-phase using the rotation angle of the electric motor. Thus, the phase voltage command values ​​(three-phase voltage command values) of the U phase, the V phase, and the W phase are calculated. A U-phase PWM signal, a V-phase PWM signal, and a W-phase PWM signal with duty ratios corresponding to the phase voltage command values ​​of the U phase, the V phase, and the W phase are generated and supplied to a three-phase inverter circuit.

[0005] The six switching elements constituting the three-phase inverter circuit are controlled by the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal. As a result, a voltage equivalent to the three-phase voltage command value is applied to the three-phase electric motor. As a result, the motor current flowing through the three-phase electric motor is controlled to be equal to the two-phase current command value. (Refer to Japanese Patent Publication No. 1-50766)

[0006] In the above-mentioned motor control device, at the rising and falling moments of the phase voltage of each phase in each PWM cycle, current flows through the parasitic capacitance between the frame ground wire connected to the negative terminal of the power supply and the three-phase electric motor. Since this current flows through the frame ground wire, there is a possibility of radiating noise from the frame ground wire. In addition, in the case of a motor control device installed on an electric power steering device (EPS) installed on a vehicle, the positive and negative power supply lines from the vehicle power supply (battery) to the EPS are relatively long. Therefore, the noise current flowing through the frame ground wire passes through the parasitic capacitance generated between the positive and negative power supply lines and the frame ground wire, and mixes into the positive and negative power supply lines near the vehicle power supply, becoming common mode noise. Summary of the invention

[0007] One of the objects of the present invention is to provide a motor control device that can effectively reduce common mode noise.

[0008] The structural feature of a motor control device according to one embodiment of the present invention is that it includes: a three-phase inverter for driving an electric motor, the electric motor having a housing connected to a frame ground wire connected to a negative terminal of a power supply; and a control unit, wherein a current control period includes a plurality of PWM periods, the control unit controls the three-phase inverter based on a PWM signal of a unit PWM period generated in each of the PWM periods, the motor control device including: a PWM count calculation unit, which calculates a PWM count of a unit current control period of each of the three phases in each of the current control periods; and a noise reduction unit, which calculates a PWM count of a unit PWM period in each of the current control periods. The total value of one phase becomes a value corresponding to the PWM count of the above-mentioned unit current control period of the corresponding phase, and the PWM count of the unit PWM period of the PWM period is set in such a manner that the current flowing in the above-mentioned frame ground due to the phase voltage of any one phase of the above-mentioned three phases is offset by the current flowing in the above-mentioned frame ground due to the phase voltage of any one phase of the other two phases in each PWM period within the above-mentioned current control period; and a noise elimination circuit is used to generate a current of an opposite phase to the current flowing in the above-mentioned frame ground due to the phase voltage of another phase of the above-mentioned other two phases in each PWM period within the above-mentioned current control period. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features and advantages of the present invention are further clarified by the following detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings.

[0010] Figure 1 1 is a schematic diagram showing a schematic configuration of an electric power steering device to which a motor control device according to an embodiment of the present invention is applied.

[0011] Figure 2 It is a block diagram showing the overall electrical structure of the ECU.

[0012] Figure 3 This is a block diagram mainly showing the functional structure of a microcomputer.

[0013] Figure 4A It is a schematic diagram showing the relationship between the period Tc of the PWM signal and the current control period Ta.

[0014] Figure 4B It is a waveform diagram showing the carrier waveform.

[0015] Figure 4C This is a schematic diagram for explaining a method of generating a PWM signal.

[0016] Figure 51 is a graph showing a setting example of the assist current value Ia* for the detected steering torque T. FIG.

[0017] Figure 6 This is an explanatory diagram for explaining the basic concept of common mode noise reduction by the common mode noise reduction unit.

[0018] Figure 7 This is a circuit diagram showing an equivalent circuit focusing on common mode noise current.

[0019] Figure 8 This is a flowchart for explaining an example of the operation of the common mode noise reduction unit.

[0020] Fig. 9 This is a schematic diagram mainly showing the relationship between the PWM count and the upper FET command and the lower FET command of each phase.

[0021] Fig. 10A This is a diagram showing a current path during a dead time period in a state where a current flows from a connection point between an upper FET and a lower FET toward the electric motor side.

[0022] Fig. 10B This is a diagram showing a current path during a dead time period in a state where a current flows from the electric motor side toward a connection point between an upper FET and a lower FET.

[0023] Fig.11A Yes means through Figure 8 FIG. 1 is a diagram showing an example of the PWM count per unit PWM period of each phase set in step S1 .

[0024] Fig. 11B Yes means through Figure 8 FIG. 1 is a diagram showing an example of the PWM count per unit PWM period of each phase set in step S2 .

[0025] Fig. 12A is a schematic diagram showing an example of two amplitude modes.

[0026] Fig. 12B Schematic diagram showing an example of the amplitude per PWM cycle of the V phase and the W phase.

[0027] Fig. 12C It is a schematic diagram showing an example of the final PWM count for each phase in each PWM cycle.

[0028] Fig.12D It means the same as Fig. 12C The diagram shown is a schematic diagram of the PWM count corresponding to the timing of the level change of each phase voltage corresponding to the final PWM count.

[0029] Fig.13A Yes means through Figure 8 FIG. 1 is a diagram showing another example of setting the PWM count per unit PWM period of each phase in step S1 .

[0030] Fig. 13B Yes means through Figure 8 FIG. 1 is a diagram showing another example of setting the PWM count per unit PWM period of each phase in step S2 .

[0031] Fig.14A is a schematic diagram showing an example of two amplitude modes.

[0032] Fig. 14B FIG. 1 is a schematic diagram showing an example of the amplitude per PWM cycle of the U-phase and the W-phase.

[0033] Fig. 14C It is a schematic diagram showing an example of the final PWM count for each phase in each PWM cycle.

[0034] Fig.14D It means the same as Fig. 14C The diagram shown is a schematic diagram of the PWM count corresponding to the timing of the level change of each phase voltage corresponding to the final PWM count.

[0035] Fig.15A This is a schematic diagram showing an example of a PWM count set by the cancelling circuit control unit when the connection point between the upper FET and the lower FET in the noise cancelling circuit is pulled down.

[0036] Fig. 15B This is a schematic diagram showing an example of a PWM count set by the noise cancelling circuit control unit when the connection point between the upper FET and the lower FET in the noise cancelling circuit is pulled up.

[0037] Fig.16 This is a timing chart for explaining the operation of the cancellation circuit control unit and the noise cancellation circuit.

[0038] Fig.17A Schematic diagram showing the path of the common mode current flowing through the frame ground when the W-phase phase voltage drops.

[0039] Fig. 17B Schematic diagram showing the path of the noise canceling current generated by the noise canceling circuit at that time.

[0040] Fig. 17C FIG. 1 is a schematic diagram showing the path of the common mode current after cancellation.

[0041] Fig.18A Schematic diagram showing the path of the common mode current flowing through the frame ground when the W-phase phase voltage rises.

[0042] Fig.18B Schematic diagram showing the path of the noise canceling current generated by the noise canceling circuit at that time.

[0043] Fig. 18C FIG. 1 is a schematic diagram showing the path of the common mode current after cancellation. DETAILED DESCRIPTION

[0044] Hereinafter, an embodiment in which the present invention is applied to an electric power steering device will be described in detail with reference to the drawings. Figure 1 1 is a schematic diagram showing a simplified structure of an electric power steering device to which a motor control device according to an embodiment of the present invention is applied. The electric power steering device (EPS) 1 includes a steering wheel 2, a steering mechanism 4, and a steering assist mechanism 5. The steering wheel 2 is a steering control component for controlling the direction of the vehicle. The steering mechanism 4 steers the steering wheel 3 in conjunction with the rotation of the steering wheel 2. The steering assist mechanism 5 assists the driver in steering. The steering wheel 2 and the steering mechanism 4 are mechanically connected via a steering shaft 6 and an intermediate shaft 7.

[0045] The steering shaft 6 includes an input shaft 8 connected to the steering wheel 2 and an output shaft 9 connected to the intermediate shaft 7. The input shaft 8 and the output shaft 9 are connected via a torsion bar 10 so as to be relatively rotatable. A torque sensor 11 is arranged near the torsion bar 10. The torque sensor 11 detects the steering torque T applied to the steering wheel 2 based on the relative rotation displacement of the input shaft 8 and the output shaft 9. In the present embodiment, the steering torque T detected by the torque sensor 11 is detected as a positive value for steering to the right and as a negative value for steering to the left, for example. The larger the absolute value, the larger the magnitude of the steering torque.

[0046] The steering mechanism 4 is composed of a rack and pinion mechanism including a pinion shaft 13 and a rack shaft 14 as a steering shaft. The steered wheels 3 are connected to the ends of the rack shaft 14 via a steering tie rod 15 and a knuckle arm (not shown). The pinion shaft 13 is connected to the intermediate shaft 7. The pinion shaft 13 rotates in conjunction with the steering operation of the steering wheel 2. Figure 1 The lower end is connected with a pinion 16.

[0047] The rack shaft 14 extends linearly in the left-right direction of the vehicle. A rack 17 meshing with the pinion 16 is formed in the axial middle portion of the rack shaft 14. The rotation of the pinion shaft 13 is converted into the axial movement of the rack shaft 14 by the pinion 16 and the rack 17. By moving the rack shaft 14 in the axial direction, the steering wheel 3 can be steered.

[0048] If the steering wheel 2 is steered (rotated), the rotation is transmitted to the pinion shaft 13 via the steering shaft 6 and the intermediate shaft 7. The rotation of the pinion shaft 13 is converted into axial movement of the rack shaft 14 through the pinion 16 and the rack 17. As a result, the steering wheel 3 is steered. The steering assist mechanism 5 includes an electric motor 18 for steering assist, and a reduction mechanism 19. The reduction mechanism 19 transmits the output torque of the electric motor 18 to the steering mechanism 4. In the present embodiment, the electric motor 18 is a three-phase brushless motor. In the electric motor 18, a rotation angle sensor 23, such as a resolver, is provided for detecting the rotation angle of the rotor of the electric motor 18. The reduction mechanism 19 is composed of a worm gear mechanism including a worm shaft 20 and a worm wheel 21 meshing with the worm shaft 20.

[0049] The worm shaft 20 is driven to rotate by the electric motor 18. In addition, the worm wheel 21 is connected so as to be able to rotate integrally with the steering shaft 6. The worm wheel 21 is driven to rotate by the worm shaft 20. If the worm shaft 20 is driven to rotate by the electric motor 18, the worm wheel 21 is driven to rotate, and the steering shaft 6 rotates. Moreover, the rotation of the steering shaft 6 is transmitted to the pinion shaft 13 via the intermediate shaft 7. The rotation of the pinion shaft 13 is converted into an axial movement of the rack shaft 14. As a result, the steering wheel 3 is steered. That is, the worm shaft 20 is driven to rotate by the electric motor 18. As a result, steering operation assistance using the electric motor 18 can be performed.

[0050] The vehicle is provided with a vehicle speed sensor 24 for detecting a vehicle speed V. The steering torque T detected by the torque sensor 11, the vehicle speed V detected by the vehicle speed sensor 24, the output signal of the rotation angle sensor 23, etc. are input to an ECU (Electronic Control Unit) 12. The ECU 12 controls the electric motor 18 based on these input signals.

[0051] Figure 2 1 is a block diagram showing the overall electrical structure of ECU 12. ECU 12 includes a motor drive circuit 31, a noise elimination circuit 32, and a microcomputer 33. The motor drive circuit 31 is a circuit for supplying power to the electric motor 18. The noise elimination circuit 32 is a circuit for suppressing common mode noise. The motor drive circuit 31 and the noise elimination circuit 32 are controlled by a microcomputer (microcomputer) 33. As described later, the motor drive circuit 31 is controlled by an inverter control unit 51. The noise elimination circuit 32 is controlled by a elimination circuit control unit 52.

[0052] The electric motor 18 is, for example, a three-phase brushless motor. The electric motor 18 includes a rotor (not shown) as a magnetic field, and stator coils 18U, 18V, and 18W including a U phase, a V phase, and a W phase (see FIG. Figure 3) stator. The motor drive circuit 31 is composed of a three-phase inverter. The motor drive circuit 31 includes a smoothing capacitor 101 connected in series with a power source (battery) 100, a plurality of switching elements 111 to 116, and a plurality of diodes 121 to 126. The smoothing capacitor 101 is connected between two terminals of the power source 100. In the present embodiment, each switching element 111 to 116 is composed of an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Hereinafter, the switching elements 111 to 116 are sometimes referred to as FETs 111 to 116.

[0053] The plurality of FETs 111 to 116 include an upper FET 111 for U phase and a lower FET 112 for U phase connected in series therewith, an upper FET 113 for V phase and a lower FET 114 for V phase connected in series therewith, and an upper FET 115 for W phase and a lower FET 116 for W phase connected in series therewith. Each of the switching elements 111 to 116 is connected in anti-parallel to diodes 121 to 126, respectively.

[0054] The drains of the upper FETs 111, 113, and 115 are connected to the positive terminal of the smoothing capacitor 101. The sources of the upper FETs 111, 113, and 115 are connected to the drains of the lower FETs 112, 114, and 116, respectively. The sources of the lower FETs 112, 114, and 116 are connected to the negative terminal of the smoothing capacitor 101. The connection point between the upper FET 111 and the lower FET 112 of the U phase is connected to the U phase stator coil 18U of the electric motor 18. The connection point between the upper FET 113 and the lower FET 114 of the V phase is connected to the V phase stator coil 18V of the electric motor 18. The connection point between the upper FET 115 and the lower FET 116 of the W phase is connected to the W phase stator coil 18W of the electric motor 18. Each of the FETs 111 to 116 is controlled based on a PWM signal output from an inverter control unit 51 described later.

[0055] The power supply 100 is installed in the vehicle. The negative (-) electrode of the power supply 100 is electrically connected to the metallic frame (frame ground) 130 of the vehicle. Therefore, the frame 130 and the negative electrode of the power supply 100 are at the same potential. The electric power steering device 1 equipped with the electric motor 18 is installed on the frame 130 by bolts or the like. The positive power line and the negative power line of the ECU are connected to the positive and negative electrodes of the power supply 100 through longer wires, respectively. The housing of the electric motor 18 is electrically connected to the frame 130. There is a parasitic capacitance C1 between the stator coils 18U, 18V, 18W of the electric motor 18 and the housing. Therefore, there is a parasitic capacitance C1 between the electric motor 18 and the frame 130. In addition, there are parasitic capacitances C2 and C3 between the positive power line 131 and the negative power line 132 connecting the power supply 100 and the electric power steering device 1 and the frame 130.

[0056] The noise elimination circuit 32 includes a half-bridge circuit 41, an RLC circuit 42, and a pull-down resistor 43. The half-bridge circuit 41 is connected to the power supply 100 in parallel with the motor drive circuit 31. The half-bridge circuit 41 is composed of a series circuit of two switching elements 44 and 45. Each switching element 44 and 45 is composed of an n-channel MOSFET. Hereinafter, the switching element 44 is referred to as an upper FET 44, and the switching element 45 is referred to as a lower FET 45.

[0057] The drain of the upper FET 44 is connected to the positive power supply line 131. The source of the upper FET 44 is connected to the drain of the lower FET 45. The source of the lower FET 45 is connected to the negative power supply line 132. The RLC circuit 42 is composed of a series circuit of a resistor 46, a coil 47, and a capacitor 48. The resistor 46 is connected to one end of the coil 47, and the capacitor 48 is connected to the other end of the coil 47. One end of the RLC circuit 42 (the end on the resistor 46 side) is connected to the connection point between the upper FET 44 and the lower FET 45. The other end of the RLC circuit 42 (the end on the capacitor 48 side) is connected to the frame 130. The connection point between the upper FET 44 and the lower FET 45 (the source of the upper FET 44) is electrically connected to the negative power supply line 132 via the pull-down resistor 43.

[0058] Figure 3 1 is a block diagram mainly showing the functional structure of the microcomputer 33. Two current sensors 25 and 26 are provided on the power supply line for connecting the motor drive circuit 31 and the electric motor 18. These current sensors 25 and 26 are provided so as to be able to detect the phase current flowing in two of the three power supply lines for connecting the motor drive circuit 31 and the electric motor 18.

[0059] The microcomputer 33 includes a CPU and a memory (ROM, RAM, nonvolatile memory, etc.). The microcomputer 33 functions as a plurality of functional processing units by executing a predetermined program. The plurality of functional processing units include an inverter control unit 51 and an elimination circuit control unit 52. The inverter control unit 51 controls the motor drive circuit 31. The elimination circuit control unit 52 controls the noise elimination circuit 32.

[0060] The inverter control unit 51 includes an auxiliary current value setting unit 61, a current command value setting unit 62, a current deviation calculation unit 63, a PI (proportional integral) control unit 64, a two-phase / three-phase conversion unit 65, a PWM duty cycle calculation unit (PWM Duty calculation unit) 66, a common mode noise reduction unit 67, a first PWM output unit 68, a three-phase / two-phase conversion unit 69, a rotation angle calculation unit 70, a rotation speed calculation unit 71, and a rotation angle estimation unit 72.

[0061] like Figure 4A As shown, the period (hereinafter referred to as "PWM period") Tc of the PWM signal is smaller than the current control period Ta. Here, the so-called current control period Ta is the calculation period of the control loop of the motor current. The current control period Ta is determined in consideration of the scale of the program, the computing power of the microcomputer 33, etc. In the present embodiment, the PWM duty is updated by the PWM duty calculation unit 66 at the first opportunity within the current current control period Ta. The updated PWM duty ratios Cu, Cv, and Cw are output. In the present embodiment, Tc is 1 / 10 of Ta. In other words, the current control period Ta includes 10 periods of PWM period Tc. There is a case where the first period of the 10 periods of PWM period Tc is called the first period, and the subsequent periods are called the second, third, ..., ninth, and tenth periods. In addition, there is a case where the period number of the PWM period is represented by i (i = 1, 2, ..., 9, 10). In addition, the frequency (= 1 / Tc) of the PWM signal is called the carrier frequency.

[0062] The PWM waveform generation method in this embodiment is described. In the microcomputer 33, a counter (not shown) is used to count up and count down the clock of the PWM clock frequency generated by the clock generator (not shown). If the count value of the counter is plotted with time on the horizontal axis and count value on the vertical axis, the count value is as follows: Figure 4B Here, the count value is interpreted as an unsigned integer. In addition, there are cases where the count value is called a carrier count. In this embodiment, Figure 4BThe waveform is the carrier waveform. The carrier waveform is a triangular wave. One cycle of the triangular wave is equal to Tc. The frequency (carrier frequency) of the PWM signal is determined by the maximum value of the carrier waveform, in other words, the maximum value of the count value. In this embodiment, the PWM clock frequency is 100 [MHz], and the frequency of the PWM signal (hereinafter referred to as "PWM frequency") is set to 100 [kHz], so the maximum value of the count value is 100,000,000 ÷ 100,000 ÷ 2 = 500. Because of the up and down counting, 100,000,000 / 100,000 is divided by 2.

[0063] like Figure 4C As shown, the first PWM output unit 68 (refer to Figure 3 ) compares the given PWM count with the count value of the counter, and outputs a high signal or a low signal to the motor drive circuit 31. The first PWM output unit 68 outputs a high signal (or a low signal) when the count value of the counter ≥ the PWM count is established, and outputs a low signal (or a high signal) otherwise. The high signal and the low signal are PWM signals.

[0064] In the present embodiment, there are the following two patterns as the change patterns (ON / OFF patterns) of the ON / OFF states of the upper-stage FET and the lower-stage FET within the PWM period Tc.

[0065] First on-off mode: From the start of carrier counting, the mode changes from the upper FET on-state → the lower FET on-state → the upper FET on-state.

[0066] Second on-off mode: From the start of carrier counting, the mode changes from the on-state of the lower FET → the on-state of the upper FET → the on-state of the lower FET.

[0067] In the present embodiment, the upper and lower segment FETs of two phases of the U phase, the V phase, and the W phase are controlled to be the same mode of any one of the first on-off mode and the second on-off mode. The upper and lower segment FETs of the remaining one phase are controlled to be in another mode. One of the two phases in which the upper and lower segment FETs are controlled to be in one on-off mode is referred to as phase A, and the other phase is referred to as phase B. In some cases, the remaining one phase in which the upper and lower segment FETs are controlled to be in another on-off mode is referred to as phase C.

[0068] The on-off mode for each phase is preset. In the present embodiment, the on-off mode for the U phase and the W phase within the PWM period Tc is controlled to be the first on-off mode. The on-off mode for the V phase within the PWM period Tc is controlled to be the second on-off mode. Therefore, in the present embodiment, one of the U phase and the W phase is equivalent to the A phase, the other phase is equivalent to the B phase, and the V phase is equivalent to the C phase.

[0069] Return to Figure 3 The rotation angle calculation unit 70 calculates the rotation angle θ (electrical angle) of the rotor of the electric motor 18 in each current control cycle Ta based on the output signal of the rotation angle sensor 23. The rotor rotation angle θ calculated by the rotation angle calculation unit 70 is given to the three-phase / two-phase conversion unit 69, the rotation speed calculation unit 71, and the rotation angle estimation unit 72. In the present embodiment, the timing for acquiring (detecting) the rotor rotation angle θ is the central time of the current control cycle Ta.

[0070] The rotation speed calculation unit 71 calculates the rotation speed (angular speed) ω of the rotor of the electric motor 18 by time-differentiating the rotor rotation angle θ calculated by the rotation angle calculation unit 70. The rotation speed ω calculated by the rotation speed calculation unit 71 is given to the rotation angle estimation unit 72. The rotation angle estimation unit 72 estimates the rotor rotation angle θ(m+1) at the center time of the next current control cycle Ta based on the following formula (1) using the rotor rotation angle θ(m-1) at the center time of the previous current control cycle Ta acquired in the previous current control cycle Ta.

[0071] θ(m+1)=θ(m-1)+ω·2Ta…(1)

[0072] The rotor rotation angle θ(m+1) in the next current control period Ta estimated by the rotation angle estimation unit 72 is given to the two-phase / three-phase conversion unit 65. The auxiliary current value setting unit 61 sets the auxiliary current value Ia* for each current control period Ta based on the detected steering torque T detected by the torque sensor 11 and the vehicle speed V detected by the vehicle speed sensor 24. The setting of the auxiliary current value Ia* for the detected steering torque T is as follows: Figure 5 As shown. The detected steering torque T, for example, is taken as a positive value for the torque used for steering toward the right, and is taken as a negative value for the torque used for steering toward the left. For the auxiliary current value Ia*, it is set to a positive value when the electric motor 18 is to generate a steering assist force for right steering, and is set to a negative value when the electric motor 18 is to generate a steering assist force for left steering. For the auxiliary current value Ia*, a positive value is taken for a positive value of the detected steering torque T, and a negative value is taken for a negative value of the detected steering torque T.

[0073] When the detected steering torque T is a small value in the range of -T1 to T1 (for example, T1 = 0.4 N·m) (torque dead zone), the auxiliary current value Ia* is set to zero. When the detected steering torque T is a value outside the range of -T1 to T1, the auxiliary current value Ia* is set to be larger as the absolute value of the detected steering torque T is larger. The auxiliary current value Ia* is set to be smaller as the vehicle speed V detected by the vehicle speed sensor 24 is larger. As a result, the steering assist force is increased when the vehicle is traveling at a low speed, and the steering assist force is reduced when the vehicle is traveling at a high speed.

[0074] The current command value setting unit 62 sets the current value to flow through the coordinate axis of the dq coordinate system as the current command value based on the auxiliary current value Ia* set by the auxiliary current value setting unit 61. Specifically, the current command value setting unit 62 sets the d-axis current command value Id* and the q-axis current command value Iq* (hereinafter, when they are collectively referred to as "two-phase current command value Idq*"). More specifically, the current command value setting unit 62 sets the q-axis current command value Iq* to the auxiliary current value Ia* set by the auxiliary current value setting unit 61, and on the other hand, sets the d-axis current command value Id* to zero. The two-phase current command value Idq* set by the current command value setting unit 62 is given to the current deviation calculation unit 63.

[0075] The three-phase / two-phase conversion unit 69 first calculates the U-phase current IU, the V-phase current IV, and the W-phase current IW (hereinafter, when collectively referred to as "three-phase detection current IUVW") based on the phase currents of the two phases detected by the current sensors 25 and 26. The three-phase / two-phase conversion unit 69 converts the three-phase detection current IUVW of the UVW coordinate system into the two-phase detection current Idq of the dq coordinate system. The two-phase detection current Idq is composed of the d-axis detection current Id and the q-axis detection current Iq. In this coordinate conversion, the rotor rotation angle θ calculated by the rotation angle calculation unit 70 is used.

[0076] The current deviation calculation unit 63 calculates the deviation of the d-axis detection current Id with respect to the d-axis current command value Id* and the deviation of the q-axis detection current Iq with respect to the q-axis current command value Iq*. These deviations are given to the PI control unit 64. The PI control unit 64 performs PI calculation on the current deviation calculated by the current deviation calculation unit 63. Thus, a two-phase voltage command value Vdq* (d-axis voltage command value Vd* and q-axis voltage command value Vq*) to be applied to the electric motor 18 is generated. The two-phase voltage command value Vdq* is given to the two-phase / three-phase conversion unit 65.

[0077] The two-phase / three-phase conversion unit 65 uses the rotation angle estimation value θ(m+1) for the next current control cycle Ta calculated by the rotation angle estimation unit 72 in the current current control cycle Ta to perform two-phase / three-phase conversion on the two-phase voltage command value Vdq* calculated by the PI control unit 64 in the current current control cycle Ta. Thus, the three-phase voltage command value VUVW* for the next current control cycle Ta is calculated. The three-phase voltage command value VUVW* is composed of the U-phase voltage command value VU*, the V-phase voltage command value VV*, and the W-phase voltage command value VW*. Thus, the three-phase voltage command value VUVW* for the next current control cycle Ta is obtained.

[0078] The three-phase voltage command value VUVW* for the next current control cycle Ta obtained by the two-phase / three-phase conversion unit 65 is given to the PWM duty ratio calculation unit 66. The PWM duty ratio calculation unit 66 generates the U-phase PWM count (PWM duty ratio), the V-phase PWM count, and the W-phase PWM count for the next current control cycle Ta based on the three-phase voltage command value VUVW* for the next current control cycle Ta, and gives them to the common mode noise reduction unit 67.

[0079] The PWM count of the U phase in which the upper and lower stage FETs are controlled to be in the first on-off mode is obtained, for example, as follows. That is, the PWM duty ratio calculation unit 66 uses the U phase voltage command value VU* for a certain current control cycle Ta obtained by the two-phase / three-phase conversion unit 65 and the maximum value of the PWM count (500 in this example) to calculate the U phase PWM count Cu for the current control cycle Ta based on the following formula (2).

[0080] Cu=VU*×(maximum value of PWM count / Vb)=VU*×(500 / Vb)…(2)

[0081] In the above equation (2), Vb is the power supply voltage (output voltage of the power supply 100) of the motor drive circuit 31. The PWM count Cw of the W phase in which the upper and lower stage FETs are controlled to be in the first on-off mode can be calculated by using the W phase voltage command value VW* instead of the U phase voltage command value VU* on the right side of the above equation (2).

[0082] The PWM count Cv of the V phase in which the upper and lower stage FETs are controlled to be in the second on-off mode is obtained as follows. That is, the PWM duty ratio calculation unit 66 uses the V phase voltage command value VV* for a certain current control cycle Ta obtained by the two-phase / three-phase conversion unit 65 and the maximum value of the PWM count (500 in this example) to calculate the V phase PWM count Cv for the current control cycle Ta based on the following formula (3).

[0083] Cv = maximum value of PWM count - {VV*×(maximum value of PWM count / Vb)}

[0084] =500-{VV*×(500 / Vb)}…(3)

[0085] In the above formula (3), Vb is the power supply voltage of the motor drive circuit 31 (the output voltage of the power supply 100). The common mode noise reduction unit 67 is provided to reduce the common mode noise by canceling the noise current generated by the on and off of the switching element of a certain phase by the noise current generated by the on and off of the switching element of other phases. The common mode noise reduction unit 67 performs a process (noise reduction process) for reducing the common mode noise based on the U-phase PWM count Cu, the V-phase PWM count Cv, and the W-phase PWM count Cw for the next current control cycle Ta given from the PWM duty cycle calculation unit 66. Thus, the U-phase PWM count, the V-phase PWM count, and the W-phase PWM count for each PWM cycle Tc in the next current control cycle Ta are obtained. The details of the operation of the common mode noise reduction unit 67 will be described later.

[0086] The U-phase PWM count, V-phase PWM count, and W-phase PWM count for each PWM period Tc in the next current control period Ta after the noise reduction process by the common mode noise reduction unit 67 are given to the first PWM output unit 68. The first PWM output unit 68 stores the U-phase PWM count, V-phase PWM count, and W-phase PWM count for each PWM period Tc in the current control period Ta given from the common mode noise reduction unit 67 over a plurality of current control periods. The first PWM output unit 68 generates a U-phase PWM signal, a V-phase PWM signal, and a W-phase PWM signal for each PWM period Tc in the current current control period Ta based on the U-phase PWM count, V-phase PWM count, and W-phase PWM count for each PWM period Tc in the current current control period Ta given from the common mode noise reduction unit 67 in the previous current control period Ta, and supplies the U-phase PWM signal, the V-phase PWM signal, and the W-phase PWM signal to the motor drive circuit 31. Specifically, the first PWM output unit 68 generates a U-phase PWM signal, a V-phase PWM signal, and a W-phase PWM signal with duty ratios corresponding to the U-phase PWM count, the V-phase PWM count, and the W-phase PWM count for each PWM period Tc within the current control period Ta, and supplies them to the motor drive circuit 31.

[0087] The six FETs 111 to 116 constituting the motor drive circuit 31 are controlled by the PWM signal given from the first PWM output unit 68. As a result, a voltage corresponding to the three-phase voltage command value VUVW* for each PWM cycle Tc is applied to the stator coils 18U, 18V, and 18W of each phase of the electric motor 18. The current deviation calculation unit 63 and the PI control unit 64 constitute a current feedback control unit. Through the operation of the current feedback control unit, the motor current flowing in the electric motor 18 is controlled to be close to the two-phase current command value Idq* set by the current command value setting unit 62.

[0088] The common mode noise reduction unit 67 will be described in detail below. Figure 6 The basic idea of ​​common mode noise reduction by the common mode noise reduction unit 67 is described below. The waveform of the output voltage of one phase among the three phases (hereinafter referred to as the first phase voltage) is Figure 6 In the case of (a), due to the first phase voltage, the parasitic capacitance C1 (see Figure 2 ) is the current flowing in Figure 6 In other words, at the falling time t1 of the first phase voltage, a negative current flows in the parasitic capacitor C1, and at the rising time t2 of the first phase voltage, a positive current flows in the parasitic capacitor C1.

[0089] Therefore, if Figure 6 As shown in (b), the waveform of the output voltage of one of the other two phases (hereinafter referred to as the second phase voltage) is set to Figure 6 (a) is a waveform after the waveform of the first phase voltage is inverted. Thus, due to the second phase voltage, the parasitic capacitance C1 (see Figure 2 ) is the current flowing in Figure 6 (d) In other words, at the rising moment t1 of the second phase voltage, the positive current flows in the parasitic capacitor C1. At the falling moment t2 of the second phase voltage, the negative current flows in the parasitic capacitor C1. Therefore, at each moment t1 and t2, the current flowing in the parasitic capacitor C1 due to the first phase voltage and the current flowing in the parasitic capacitor C1 due to the second phase voltage cancel each other out. Therefore, Figure 6 As shown in (e), the parasitic capacitors C2 and C3 (see Figure 2 ) decreases.

[0090] Figure 7 This is an equivalent circuit focusing on the common mode noise current. The first phase voltage and the second phase voltage can be regarded as the noise generation source. It can be considered that the positive and negative electrodes of the power supply 100 are short-circuited in the alternating current such as the common mode noise current. Figure 7 In the diagram, the common mode noise current flows as indicated by the solid arrow due to the increase in the first phase voltage. The common mode noise current flows as indicated by the dashed arrow due to the decrease in the second phase voltage. Therefore, since the directions of the common mode noise currents flowing in the parasitic capacitors C2 and C3 are opposite to each other, they cancel each other out, and as a result, the total common mode noise current is reduced.

[0091] The common mode noise reduction unit 67 sets the final PWM count of the unit PWM cycle in such a manner that, in each PWM cycle within the current control cycle, the current flowing in the parasitic capacitor due to the phase voltage of any one of the three phases is offset by the current flowing in the parasitic capacitor due to the phase voltage of any one of the other two phases. However, the common mode noise reduction unit 67 sets the final PWM count of each PWM cycle Tc in such a manner that the total value of the PWM count of the unit PWM cycle within the current control cycle Ta for each phase becomes a value corresponding to the PWM count of the unit current control cycle of the corresponding phase. In the present embodiment, the value corresponding to the PWM count of the unit current control cycle of the corresponding phase is a value obtained by multiplying the PWM count of the unit current control cycle of the corresponding phase by 10.

[0092] Figure 8 1 is a flowchart for explaining an example of the operation of the common mode noise reduction unit. Figure 3 ) First, the PWM counts Cu, Cv and Cw of the U phase, V phase and W phase for the next current control period Ta assigned from the PWM duty cycle calculation unit 66 are set to the PWM counts Cu, Cv and Cw of the U phase, V phase and W phase for each PWM period Tc within the next current control period Ta (step S1).

[0093] Fig.11A The diagram shows an example of PWM counts Cu, Cv and Cw of the U-phase, V-phase and W-phase in each PWM period Tc within the current control period Ta set in step S1. Next, the common mode noise reduction unit 67 sets a switching timing taking into account the dead time for each phase (step S2).

[0094] Fig. 9 1 is a schematic diagram mainly showing the relationship between the PWM count and the upper FET command and the lower FET command of each phase. In other words, it is used to control the first PWM output unit 68 (refer to Figure 3 ) is a schematic diagram for explaining an example of the operation of each phase of the PWM. In the present embodiment, as described above, the carrier waveform is a triangular wave, and the output count of the PWM count is set to 0 to 500. In addition, in the present embodiment, the count value corresponding to the dead time is set to 10.

[0095] The upper FET command and the lower FET command in which the upper and lower FETs are controlled to become the U phase and the W phase (the first on-off mode phase) of the first on-off mode are described. When the carrier count is larger than the PWM count of the first on-off mode phase, the switching timing of the upper FET of the first on-off mode phase is set so that the upper FET command of the first on-off mode phase becomes the off command. In other words, if the carrier count is equal to the PWM count of the first on-off mode phase (time t2) during the up counting of the carrier count, then Fig. 9 As shown in (a), the upper FET instruction of the first on-off mode phase changes from the on instruction to the off instruction. Furthermore, when the carrier count is equal to the PWM count of the first on-off mode phase during the down counting of the carrier count (time t5), the upper FET instruction of the first on-off mode phase changes from the off instruction to the on instruction.

[0096] like Fig. 9 As shown in (b), if the dead time Td passes from time t2 (time t3), the lower FET instruction of the first on-off mode phase changes from the off instruction to the on instruction. Moreover, at a time (time t4) that is earlier than the dead time Td relative to time t5, the lower FET instruction of the first on-off mode phase changes from the on instruction to the off instruction. The upper FET instruction and the lower FET instruction of the V phase (second on-off mode phase) in which the upper and lower FETs are controlled to become the second on-off mode are described. When the carrier count is larger than the PWM count of the second on-off mode phase, the switching timing of the upper FET of the second on-off mode phase is set in such a way that the upper FET instruction of the second on-off mode phase becomes the on instruction. In other words, if the carrier count is equal to the PWM count of the second on-off mode phase during the up counting of the carrier count (time t2), then as shown in Fig. 9 As shown in (e), the upper FET instruction of the second on-off mode phase changes from the off instruction to the on instruction. Furthermore, when the carrier count is equal to the PWM count of the second on-off mode phase during the down counting of the carrier count (time t5), the upper FET instruction of the second on-off mode phase changes from the on instruction to the off instruction.

[0097] like Fig. 9 As shown in (f), at the moment (time t1) that is earlier than the moment t2 by the dead time Td, the lower FET instruction of the second on-off mode phase changes from the on instruction to the off instruction. When the dead time Td has passed from the moment t5 (time t6), the lower FET instruction of the second on-off mode phase changes from the off instruction to the on instruction. Fig. 10A as well as Fig. 10BThe phase voltage of a certain phase during the dead time period will be described. Here, the U phase will be described as an example, but the same is true for the other two phases.

[0098] like Fig. 10A As shown in FIG. 1 , in a state where the current flows from the connection point of the upper FET 111 and the lower FET 112 toward the electric motor 18, during the dead time, as shown by arrow 141, the current flows through the diode 122 connected in antiparallel to the lower FET 112. Therefore, during the dead time, the phase voltage Vu is at a low level. Therefore, the period during which the phase voltage Vu is at a low level is the same as the off period of the upper FET 111.

[0099] On the other hand, Fig. 10B As shown in FIG. 1 , in a state where the current flows from the electric motor 18 side toward the connection point of the upper FET 111 and the lower FET 112, during the dead time, as shown by the arrow 142, the current flows through the diode 121 connected in antiparallel to the upper FET 111. Therefore, during the dead time, the phase voltage Vu becomes a high level. Therefore, the period of the low level of the phase voltage Vu is shorter than the off period of the upper FET 111. In other words, the period of the high level of the phase voltage Vu is longer than the on period of the upper FET 111.

[0100] In the U phase and the W phase as the first on-off mode phase, when the PWM count is 1 / 2 or more of the maximum PWM count (250 or more), the on time of the upper FET becomes longer than when the PWM count is less than 1 / 2 of the maximum PWM count. Therefore, in this embodiment, for the sake of convenience, when the PWM count is 250 or more, it is considered that the current flows from the connection point of the upper FET and the lower FET toward the electric motor 18 side ( Fig. 10A Therefore, during the dead time, the phase voltage is considered to be at a low level. Fig. 9 Therefore, the timing of the phase voltage level change coincides with the switching timing of the upper FET.

[0101] On the other hand, in the U phase and the W phase, when the PWM count is less than 1 / 2 of the maximum PWM count value (less than 250), the on time of the upper FET becomes shorter than when the PWM count is more than 1 / 2 of the maximum PWM count value. Therefore, in this embodiment, for the sake of convenience, when the PWM count is less than 250, it is considered that the current flows from the electric motor 18 side to the connection point between the upper FET and the lower FET ( Fig. 10B Therefore, during the dead time, the phase voltage is considered to be at a high level. Fig. 9 (d) shows a change, so the phase voltage level change timing is inconsistent with the switching timing of the upper FET. The virtual PWM count (switching timing considering the dead time) in which the switching timing of the upper FET is consistent with the phase voltage level change timing is the value obtained by adding the count value equivalent to the dead time (in this embodiment, "10") to the actual PWM count.

[0102] In the V phase as the second on-off mode phase, when the PWM count is 1 / 2 or more of the maximum PWM count (250 or more), the on time of the upper FET is shortened compared to the case where the PWM count is less than 1 / 2 of the maximum PWM count. Therefore, in this embodiment, for the sake of convenience, when the PWM count is 250 or more, it is considered that the current flows from the electric motor 18 side to the connection point between the upper FET and the lower FET ( Fig. 10B Therefore, during the dead time, the phase voltage is considered to be at a high level. Fig. 9 (g) As a result, the phase voltage level change timing is inconsistent with the switching timing of the upper FET. The virtual PWM count (switching timing taking into account the dead time) in which the switching timing of the upper FET is consistent with the phase voltage level change timing is the value obtained by subtracting the count value corresponding to the dead time ("10" in this embodiment) from the actual PWM count.

[0103] On the other hand, in the V phase, when the PWM count is less than 1 / 2 of the maximum PWM count value (less than 250), the on time of the upper FET is extended compared to the case where the PWM count is more than 1 / 2 of the maximum PWM count value. Therefore, in this embodiment, for the sake of convenience, when the PWM count is less than 250, it is considered that the current flows from the connection point of the upper FET and the lower FET toward the electric motor 18 side ( Fig. 10A Therefore, during the dead time, the phase voltage is considered to be at a low level. Fig. 9 Therefore, the timing of the phase voltage level change coincides with the switching timing of the upper FET.

[0104] In this embodiment, for the sake of convenience, the direction of the phase current is estimated based on whether the PWM count is 1 / 2 or more of the maximum PWM count in each phase. However, the phase current may be detected and the direction of the phase current may be estimated based on the detected value. In step S2, the common mode noise reduction unit 67 calculates the PWM count corresponding to the timing of the level change of the phase voltage of the phase (the actual timing PWM count) for each PWM count of the PWM cycle Tc of each phase set in step S1.

[0105] Specifically, for the PWM counts Cu and Cw of the U-phase and the W-phase of each PWM cycle Tc in the next current control cycle Ta, which are 250 or more, the common mode noise reduction unit 67 sets the values ​​as they are to the PWM counts corresponding to the timing of the phase voltage level change of the phase. For the PWM counts Cu and Cw of the U-phase and the W-phase, which are less than 250, the common mode noise reduction unit 67 adds the count value (in this embodiment, "10") corresponding to the dead time to the values, and sets the values ​​as the PWM counts corresponding to the timing of the phase voltage level change of the phase.

[0106] For PWM counts of 250 or more among the PWM counts Cv of the V phase for each PWM cycle Tc in the next current control cycle Ta, the common mode noise reduction unit 67 sets the value obtained by subtracting the count value corresponding to the dead time ("10" in the present embodiment) from the value as the PWM count corresponding to the timing of the phase voltage level change of the phase. For PWM counts of less than 250 among the PWM counts Cv of the V phase, the common mode noise reduction unit 67 sets the value as the PWM count corresponding to the timing of the phase voltage level change of the phase.

[0107] The PWM count per unit PWM cycle of each phase set in step S1 is Fig.11A In the case of the PWM count per unit PWM cycle of each phase set in step S2, Fig. 11B If Fig.11A and Fig. 11B By comparison, it can be seen that the PWM count Cv of the V phase changes from 300 to 290, and the PWM count Cw of the W phase changes from 100 to 110.

[0108] Next, the common mode noise reduction unit 67 sets the phase having the PWM count closest to the maximum value ("500" in the present embodiment) or the minimum value ("0" in the present embodiment) of the PWM count set by the process of step S2 as the reference phase (step S3). Fig. 11B In the example, since the PWM count Cu (Cu=400) of the U phase (equivalent to the A phase or the B phase) is closest to 500 or 0, the U phase is set as the reference phase. In the present embodiment, when one of the A phase and the B phase is set as the reference phase, the phase set as the reference phase is referred to as the A phase, and the other phase is referred to as the B phase. In the present embodiment, when the U phase is set as the reference phase as described above, the U phase is the A phase, and the W phase is the B phase.

[0109] Next, the common mode noise reduction unit 67 determines whether the reference phase is the A phase or the B phase (step S4). Fig. 11BIn the example, since the U phase is set as the reference phase, it is determined that the reference phase is the A phase or the B phase. When it is determined that the reference phase is the A phase or the B phase (step S4: Yes), the common mode noise reduction unit 67 performs the first PWM count change process (step S5).

[0110] by Fig.11A as well as Fig. 11B Taking the first PWM count change process as an example, the first PWM count change process is described in detail. Fig. 11B In the example of , as described above, the U phase is set as the reference phase. The common mode noise reduction unit 67 allocates the C phase (V phase) as the first count change target phase in which the PWM count is changed in order to cancel the noise current of the A phase (U phase) as the reference phase. The common mode noise reduction unit 67 allocates the phase different from the reference phase (in this example, the B phase (W phase)) among the A phase and the B phase as the second count change target phase for canceling the noise current of the C phase (V phase) after the count change.

[0111] The common mode noise reduction unit 67 sets an amplitude for canceling the noise current for each count change target phase (in this example, the C phase (V phase) and the B phase (W phase)). For a certain count change target phase, in order to change the PWM count value so that the total value of the PWM count value in the current control period Ta is not changed, the PWM count value of the count change target phase is added with, for example, Fig. 12A The first amplitude mode shown corresponds to an amplitude or Fig. 12A The amplitude corresponding to the second amplitude mode shown is sufficient.

[0112] Fig. 12A The x in is an amplitude regulation value for regulating the absolute value of the amplitude. In the present embodiment, the first amplitude mode is assigned to the first count change target phase (C phase (V phase)). The second amplitude mode is assigned to the second count change target phase (B phase (W phase)). The common mode noise reduction unit 67 calculates the amplitude regulation value x for each of the first count change target phase (C phase (V phase)) and the second count change target phase (B phase (W phase)) as follows based on the PWM count set by the process of step S2. The common mode noise reduction unit 67 calculates the absolute value of the difference between the PWM count of the C phase (V phase) and the PWM count of the reference phase (A phase (U phase)) that should cancel the noise current as the amplitude regulation value x for the C phase (V phase).

[0113] In this example, the amplitude specified value x for the C phase (V phase) is 110 (=400-290). Therefore, the first calculated value obtained by adding the amplitude specified value x for the C phase (V phase) to the PWM count of the C phase (V phase) is 400 (=290+110). The second calculated value obtained by subtracting the amplitude specified value x for the C phase (V phase) from the PWM count of the C phase (V phase) is 180 (=290-110).

[0114] The common mode noise reduction unit 67 calculates the absolute value of the difference between the value (in this example, the second calculated value) of the first calculated value and the second calculated value that is different from the PWM count value of the A phase (U phase) as the reference phase and the PWM count of the B phase (W phase) as the amplitude predetermined value x for the B phase (W phase). In this example, the amplitude predetermined value x for the B phase (W phase) is 70 (=180-110).

[0115] The common mode noise reduction unit 67 sets the amplitude of each PWM cycle Tc for each count change target phase based on the amplitude predetermined value x for each count change target phase calculated in this way and the amplitude pattern for the phase. Fig. 11B The amplitude of each PWM cycle Tc of the C phase (V phase) and the B phase (W phase) set by the PWM count of the unit PWM cycle of each phase is shown in FIG. Fig. 12B .

[0116] Next, the common mode noise reduction unit 67 obtains the final PWM count of each phase for each PWM period Tc in the next current control period Ta. Specifically, the PWM count of the count change target phase set in step S1 is changed based on the amplitude of each count change target phase. More specifically, the common mode noise reduction unit 67 adds the amplitude of the count change target phase to the PWM count of the count change target phase for each PWM period Tc set in step S1, thereby changing the PWM count of the count change target phase for each PWM period Tc. The PWM count of the count change target phase after the change relative to the PWM count set in step S1 becomes the final PWM count.

[0117] Next, the common mode noise reduction unit 67 obtains the PWM count corresponding to the timing of the level change of each phase voltage corresponding to the final PWM count (PWM count at the actual timing). Specifically, based on the amplitude for each count change target phase, the PWM count of the count change target phase set in step S2 is changed. More specifically, the common mode noise reduction unit 67 adds the amplitude of the count change target phase to the PWM count of the count change target phase for each PWM cycle Tc set in step S2. As a result, the PWM count of the count change target phase for each PWM cycle Tc is changed. With respect to the PWM count set in step S2, the PWM count of the count change target phase after the change becomes the PWM count at the actual timing. As a result, the first PWM count change process ends.

[0118] Next, the common mode noise reduction unit 67 gives the actual timing PWM count obtained by the first PWM count change process to the cancellation circuit control unit 52 (step S6 ).

[0119] Furthermore, the common mode noise reduction unit 67 gives the final PWM count obtained by the first PWM count change process to the first PWM output unit 68 (step S7 ). Then, the common mode noise reduction unit 67 ends the process in the current current control period Ta.

[0120] The PWM count per unit PWM cycle of each phase set in step S1 is Fig.11A The values ​​shown are as follows: The amplitude of the phase to be counted is Fig. 12B In the case of the values ​​shown, the final PWM count per unit PWM cycle of each phase is as follows Fig. 12C The actual PWM count is as shown in Fig.12D As shown. Fig.12D As shown in FIG. 1 , the PWM count of the U phase (first on-off mode phase) in the odd-numbered PWM cycle Tc coincides with the PWM count of the V phase (second on-off mode phase). Therefore, in the odd-numbered PWM cycle Tc, the parasitic capacitance C1 (refer to FIG. 1 ) on the electric motor 18 side due to the phase voltage of the U phase is Figure 2 ) is offset by the noise current flowing in the parasitic capacitance C1 on the electric motor 18 side due to the phase voltage of the V phase.

[0121] The PWM count of the V phase (second on-off mode phase) in the even-numbered PWM cycle Tc coincides with the PWM count of the W phase (first on-off mode phase). Therefore, in the even-numbered PWM cycle Tc, the parasitic capacitance C1 (refer to Figure 2 ) is cancelled by the noise current flowing in the parasitic capacitance C1 on the electric motor 18 side due to the phase voltage of the W phase. As a result, the common mode noise is reduced.

[0122] However, in the odd-numbered PWM cycle Tc, the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the W phase (the first on-off mode phase) is not offset by the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the other phases. In addition, in the even-numbered PWM cycle Tc, the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the U phase (the first on-off mode phase) is not offset by the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the other phases. As described later, the common mode noise based on the noise current that is not offset in this way is reduced by the noise elimination circuit 32.

[0123] In step S4, when it is determined that the reference phase is the C phase (step S4: No), the common mode noise reduction unit 67 performs the second PWM count change process (step S8). In the present embodiment, when the C phase is set as the reference phase, any one of the two phases other than the C phase is referred to as the A phase, and the other phase is referred to as the B phase. In the present embodiment, of the two phases other than the C phase, that is, the U phase and the W phase, the U phase is referred to as the A phase, and the W phase is referred to as the B phase.

[0124] Reference Fig.13A as well as Fig. 13B , the second PWM count change processing is described in detail. Fig.13A 1 is a diagram showing an example of PWM counts Cu, Cv, and Cw of the U-phase, V-phase, and W-phase in each PWM cycle Tc within the current control cycle Ta set in step S1. The PWM count per unit PWM cycle of each phase set in step S1 is Fig.13A In the case of the PWM count per unit PWM cycle of each phase set in step S2, Fig. 13B If Fig.13A and Fig. 13B By comparison, it can be seen that the PWM count Cv of the V phase (C phase) changes from 400 to 390. Fig. 13B In the example, since the PWM count Cu (Cu=390) of the V phase (equivalent to C) is closest to 500 or 0, the V phase is set as the reference phase in step S3. Therefore, in step S4, it is determined that the reference phase is the C phase.

[0125] In the second PWM count change processing, the common mode noise reduction unit 67 first allocates two phases, the A phase (U phase) and the B phase (W phase), as count change target phases whose PWM count is changed in order to cancel the noise current of the C phase (V phase) as the reference phase. Hereinafter, the A phase (U phase) is referred to as the first count change target phase, and the B phase (W phase) is referred to as the second count change target phase.

[0126] Then, the common mode noise reduction unit 67 sets the amplitude for canceling the noise current for each count change target phase (in this example, the A phase (U phase) and the B phase (W phase)). For a certain count change target phase, in order to change the PWM count value so as not to change the total value of the PWM count value in the current control period Ta, the PWM count value of the count change target phase is added with, for example, Fig.14A The first amplitude mode shown corresponds to an amplitude or Fig.14A The amplitude corresponding to the second amplitude mode shown is sufficient. Fig.14AThe x in is an amplitude regulation value for regulating the absolute value of the amplitude. In this embodiment, the first amplitude pattern is assigned to the A phase (U phase) as the first count change target phase. The second amplitude pattern is assigned to the B phase (W phase) as the second count change target phase.

[0127] The common mode noise reduction unit 67 calculates the amplitude specified value x for the A phase (U phase) as the first count change target phase and the B phase (W phase) as the second count change target phase in the following manner based on the PWM count set by the process of step S2. The common mode noise reduction unit 67 calculates the absolute value of the difference between the PWM count of the A phase (U phase) and the PWM count of the C phase (V phase) to cancel the noise current as the amplitude specified value x for the A phase (U phase). In this example, the amplitude specified value x for the A phase (U phase) is 30 (=390-360). The common mode noise reduction unit 67 calculates the absolute value of the difference between the PWM count of the B phase (W phase) and the PWM count of the C phase (V phase) to cancel the noise current as the amplitude specified value x for the B phase (W phase). In this example, the amplitude specified value x for the B phase (W phase) is 110 (=390-280).

[0128] The common mode noise reduction unit 67 sets the amplitude of each PWM cycle Tc for each count change target phase based on the amplitude predetermined value x for each count change target phase calculated in this way and the amplitude pattern for the phase. Fig. 14B Shown based on Fig. 13B The PWM count per unit PWM period of each phase shown sets the amplitude of each PWM period Tc of the U phase and the W phase.

[0129] Next, the common mode noise reduction unit 67 obtains the final PWM count of each phase for each PWM period Tc in the next current control period Ta. Specifically, the common mode noise reduction unit 67 changes the PWM count of the count change target phase for each PWM period Tc in the next current control period Ta set in step S1 based on the amplitude of each count change target phase. More specifically, the common mode noise reduction unit 67 changes the PWM count of the count change target phase for each PWM period Tc by adding the amplitude of the count change target phase to the PWM count of the count change target phase for each PWM period Tc set in step S1. The PWM count of the count change target phase after the count change is changed relative to the PWM count set in step S1 becomes the final PWM count.

[0130] Next, the common mode noise reduction unit 67 obtains the PWM count corresponding to the timing of the level change of each phase voltage corresponding to the final PWM count (PWM count at the actual timing). Specifically, based on the amplitude for each count change target phase, the PWM count of the count change target phase set in step S2 is changed. More specifically, the common mode noise reduction unit 67 adds the amplitude of the count change target phase to the PWM count of the count change target phase for each PWM cycle Tc set in step S2. As a result, the PWM count of the count change target phase for each PWM cycle Tc is changed. With respect to the PWM count set in step S2, the PWM count of the count change target phase after the change becomes the PWM count at the actual timing. As a result, the second PWM count change process ends.

[0131] Next, the common mode noise reduction unit 67 gives the actual timing PWM count obtained by the second PWM count change process to the cancellation circuit control unit 52 (step S9 ).

[0132] Furthermore, the common mode noise reduction unit 67 gives the final PWM count obtained by the second PWM count change process to the first PWM output unit 68 (step S10 ). Then, the common mode noise reduction unit 67 ends the process in the current current control period Ta.

[0133] The PWM count per unit PWM cycle of each phase set in step S1 is Fig.13A The values ​​shown are as follows: The amplitude of the phase to be counted is Fig. 14B In the case of the values ​​shown, the final PWM count per unit PWM cycle of each phase is as follows Fig. 14C In addition, the actual timing of PWM count is as follows Fig.14D As shown. Fig.14D As shown in FIG. 1 , the PWM count of the V phase (second on-off mode phase) in the odd-numbered PWM cycle Tc coincides with the PWM count of the U phase (first on-off mode phase). Therefore, in the odd-numbered PWM cycle Tc, the parasitic capacitance C1 (refer to FIG. 1 ) on the electric motor 18 side due to the phase voltage of the V phase is Figure 2 ) is offset by the noise current flowing in the parasitic capacitance C1 on the electric motor 18 side due to the phase voltage of the U phase.

[0134] The PWM count of the V phase (second on-off mode phase) in the even-numbered PWM cycle Tc coincides with the PWM count of the W phase (first on-off mode phase). Therefore, in the even-numbered PWM cycle Tc, the parasitic capacitance C1 (refer to Figure 2) is cancelled by the noise current flowing in the parasitic capacitance C1 on the electric motor 18 side due to the phase voltage of the W phase. As a result, the common mode noise is reduced.

[0135] However, in the odd-numbered PWM cycle Tc, the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the W phase (the first on-off mode phase) is not offset by the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the other phases. In addition, in the even-numbered PWM cycle Tc, the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the U phase (the first on-off mode phase) is not offset by the noise current flowing in the parasitic capacitor C1 due to the phase voltage of the other phases. As described later, the common mode noise based on the noise current that is not offset in this way is reduced by the noise elimination circuit 32.

[0136] As in the present embodiment, when the on / off mode for the A phase and the B phase is set to the first on / off mode, the on / off mode for the phase of the noise current that is not cancelled by the common mode noise reduction unit 67 becomes the first on / off mode. On the other hand, when the on / off mode for the A phase and the B phase is set to the second on / off mode, the on / off mode for the phase of the noise current that is not cancelled by the common mode noise reduction unit 67 becomes the second on / off mode.

[0137] Return to Figure 3 The elimination circuit control unit 52 includes a PWM count setting unit 81 and a second PWM output unit 82. The PWM count setting unit 81 sets the PWM count for PWM control of the FETs 44 and 45 in the noise elimination circuit 32 based on the PWM count at the actual timing given by the common mode noise reduction unit 67. Specifically, the PWM count setting unit 81 first extracts a pattern (non-elimination pattern) of PWM counts in which the noise current is not cancelled by the common mode noise reduction unit 67 from among the PWM counts at the actual timing.

[0138] The PWM count in actual timing is, for example, Fig.12D In the case of , as the non-elimination mode, the PWM count setting unit 81 extracts the PWM count value "40" of the W phase in the odd-numbered PWM cycle Tc and the PWM count value "400" of the U phase in the even-numbered PWM cycle Tc. Next, the PWM count setting unit 81 sets the PWM count of the same pattern as the extracted non-elimination mode as the PWM count for PWM control of the FETs 44 and 45. The PWM count at the actual timing is, for example, Fig.12D In the case of Fig.15A shown.

[0139] Then, the PWM count setting unit 81 gives the PWM count thus set as the PWM count for each PWM period Tc in the next current control period Ta to the second PWM output unit 82. In the next current control period Ta, the second PWM output unit 82 controls the FETs 44 and 45 of the noise elimination circuit 32 based on the PWM count given from the PWM count setting unit 81 in the current current control period Ta.

[0140] In the present embodiment, the on-off mode for the phase of the noise current that is not cancelled by the common mode noise reduction unit 67 is the first on-off mode. The second PWM output unit 82 generates a PWM signal in such a manner that the change pattern of the on-off state of the upper stage FET 44 and the lower stage FET 45 within the PWM period Tc becomes the second on-off mode. Thus, the noise cancellation circuit 32 can generate a noise cancellation current of the opposite phase to the noise current that is not cancelled by the common mode noise reduction unit 67.

[0141] The first PWM output unit 68 in the inverter control unit 51 is based on Fig. 12C The final PWM count shown generates a PWM signal, and the second PWM output unit 82 in the elimination circuit control unit 52 generates a PWM signal based on the following Fig.15A The operation of the noise canceling circuit 32 when the PWM signal is generated by the PWM count shown will be described. Fig.16 It is a timing chart showing the W-phase phase voltage Vw in the odd-numbered PWM cycle Tc, the command to the upper FET 44 in the noise canceling circuit 32 (upper FET command), the command to the lower FET 45 (lower FET command), and the like.

[0142] In the following description, the direction in which the current flows in the rack 130 is referred to as the positive direction, and the direction in which the current is introduced from the rack 130 is referred to as the negative direction. Fig.12D As shown in FIG. 1 , the PWM count at the actual timing of the W phase in the odd-numbered PWM cycle Tc is "40". Therefore, the W phase voltage Vw changes from a high level to a low level at time t2 after a time corresponding to "40" of the PWM count has passed from the start time of the PWM cycle Tc, and changes from a low level to a high level at time t3 after a predetermined time has passed from time t2 (refer to Fig.16 (a)).

[0143] Therefore, at the falling timing t2 of the W-phase voltage Vw, Fig.16 The common mode current (negative current) shown in (b) is generated by the parasitic capacitance C1 (refer to Figure 3 ) flows in the Fig.15AAs shown in FIG. 1 , the PWM count value of the noise elimination circuit 32 in the odd-numbered PWM cycle Tc is "40". The second PWM output unit 82 generates a PWM signal in the second on-off mode. Fig.16 As shown in (c), the instruction for the upper FET 44 (upper FET instruction) changes from the OFF instruction to the ON instruction at time t2, and changes from the ON instruction to the OFF instruction at time t3. Fig.16 As shown in (d), the command to the lower FET 45 (lower FET command) changes from the on command to the off command at the time (time t1) that is earlier than the time t2 by the dead time Td, and changes from the off command to the on command at the time (time t4) that is later than the dead time Td from the time t3. The count value corresponding to the dead time is set to "10" in the same manner as the dead time used in the motor drive circuit 31.

[0144] The connection point between the upper FET 44 and the lower FET 45 is connected to the negative power supply line 132 via the pull-down resistor 43. Therefore, during the dead time, the voltage at the connection point between the upper FET 44 and the lower FET 45 is at a low level. Fig.16 As shown in (e), the period during which the voltage at the connection point between the upper FET 44 and the lower FET 45 is at a high level is equal to the period during which the command to the upper FET 44 is an on command (the period from t2 to t3).

[0145] like Fig.16 As shown in (e), the voltage at the connection point between the upper FET 44 and the lower FET 45 changes from a low level to a high level at time t2. Fig.16 As shown in (f), the noise elimination circuit 32 (RLC circuit 42) generates Fig.16 (b) is a noise canceling current (current in the positive direction) having an opposite phase to the common mode current. Figures 17A to 17C This is an equivalent circuit focusing on the common mode noise current. At the falling timing t2 of the W phase voltage Vw, due to the W phase voltage Vw, the common mode noise current is as follows Fig.17A In addition, at this time t2, the noise elimination current flows through the noise elimination circuit 32 as shown by the arrow Q1. Fig. 17B The liquid flows as shown by arrow Q2.

[0146] Due to this noise elimination current, a negative current flows from the frame 130 through the parasitic capacitor C1 into the electric motor 18 at time t2 as shown in Fig. 17C As indicated by arrow Q1' in FIG. 1 , the current flows in the chassis 130 as a positive current via the upper FET 44 and the RLC circuit 42. This can suppress the common mode current flowing in the parasitic capacitances C2 and C3 between the power supply lines 131 and 132 and the chassis 130.

[0147] On the other hand, at the rising timing t3 of the W-phase voltage Vw, as shown in FIG. Fig.16 The common mode current (positive current) shown in (b) is generated by the parasitic capacitance C1 (refer to Figure 3 ) flows in the Fig.16 As shown in (e), the voltage at the connection point between the upper FET 44 and the lower FET 45 changes from a high level to a low level at time t3. Fig.16 As shown in (f), the noise elimination circuit 32 (RLC circuit 42) generates Fig.16 (b) is a noise canceling current (current in the negative direction) having an opposite phase to the common mode current.

[0148] Figures 18A to 18C This is an equivalent circuit focusing on the common mode noise current. At the rising timing t3 of the W phase voltage Vw, due to the W phase voltage Vw, the common mode noise current is as follows Fig.18A In addition, at time t3, the noise elimination current flows through the noise elimination circuit 32 as shown by the arrow Q3. Fig.18B Due to the noise elimination current, the positive current flowing from the electric motor 18 through the parasitic capacitor C1 into the frame 130 at time t3 is as shown in the arrow Q4. Fig. 18C As shown by arrow Q3', a negative current flows from frame 130 through RLC circuit 42 and further flows into electric motor 18 through upper FET 44. This can suppress common mode current flowing in parasitic capacitances C2 and C3 between power lines 131 and 132 and frame 130.

[0149] In other words, in the odd-numbered PWM cycle Tc, the common mode current flowing in the parasitic capacitances C2 and C3 between the power supply lines 131 and 132 and the frame 130 due to the noise current that cannot be cancelled by the common mode noise reduction unit 67 can be suppressed. The cancellation circuit control unit 52 also performs the same processing as the above-mentioned odd-numbered PWM cycle Tc in the even-numbered PWM cycle Tc. As a result, in the even-numbered PWM cycle Tc, the common mode current flowing in the parasitic capacitances C2 and C3 between the power supply lines 131 and 132 and the frame 130 due to the noise current that cannot be cancelled by the common mode noise reduction unit 67 can be suppressed.

[0150] In the above-described embodiment, in each PWM period Tc within the current control period Ta, the current flowing in the frame ground 130 due to the output voltage of any one phase (for example, the V phase) can be offset by the current flowing in the frame ground 130 due to the output voltage of any one phase (for example, the U phase or the W phase) of the other two phases. In the above-described embodiment, the noise canceling circuit 32 can generate a current of a phase opposite to the current flowing in the frame ground 130 due to the phase voltage of the other phase (for example, the W phase if the one phase is the U phase, and the U phase if the one phase is the W phase) of the other two phases in each PWM period Tc within the current control period Ta.

[0151] Thus, in each PWM period Tc within the current control period Ta, the common mode noise based on the current flowing in the frame ground line 130 due to the phase voltages of all the three phases can be reduced. Thus, the common mode noise can be effectively reduced. In the above-mentioned embodiment, the connection point between the upper FET 44 and the lower FET 45 in the noise elimination circuit 32 is connected to the negative power supply line 132 through the pull-down resistor 43. However, if Figure 2 As shown by the dotted line, the connection point between the upper FET 44 and the lower FET 45 may be connected to the positive power line 131 via the pull-up resistor 49 instead of being connected to the negative power line 132 via the pull-down resistor 43 .

[0152] At this time, during the dead time period, the voltage at the connection point between the upper FET 44 and the lower FET 45 is at a high level. Therefore, the moment when the voltage at the connection point between the upper FET 44 and the lower FET 45 changes from a low level to a high level is earlier than the moment when the instruction to the upper FET 44 changes from an off instruction to an on instruction by the amount of the dead time period. Therefore, in this case, compared with the case where the connection point between the upper FET 44 and the lower FET 45 is pulled down, it is necessary to delay the timing of turning on the upper FET 44 and the timing of turning off the lower FET 45 by the amount of the dead time period. Therefore, in this case, the PWM count setting unit 81 in the cancellation circuit control unit 52 performs the following processing.

[0153] That is, the PWM count setting unit 81 first extracts the pattern (non-elimination mode) of the PWM count in which the noise current is not cancelled by the common mode noise reduction unit 67 from the PWM count in the actual timing. Next, the PWM count setting unit 81 adds the count value corresponding to the dead time period ("10" in this embodiment) to the extracted PWM count in the non-elimination mode. Moreover, the PWM count setting unit 81 sets the PWM count of the same pattern as the non-elimination mode after adding the count value corresponding to the dead time period as the PWM count for PWM control of the FETs 44 and 45. The PWM count in the actual timing is, for example, Fig.12DIn the case of Fig. 15B Then, the PWM count setting unit 81 gives the PWM count thus set to the second PWM output unit 82 as the PWM count for each PWM period Tc in the next current control period Ta.

[0154] In the above-mentioned embodiment, the case where the on-off mode for the A phase and the B phase is the first on-off mode is described. However, the on-off mode for the A phase and the B phase may be the second on-off mode. In this case, the second PWM output unit 82 in the cancellation circuit control unit 52 may generate a PWM signal in such a way that the change pattern of the on-off state of the upper stage FET 44 and the lower stage FET 45 within the PWM period Tc becomes the first on-off mode.

[0155] In the above embodiment, the present invention is applied to the motor control device of the electric power steering device. However, the present invention can also be applied to the motor control device used in other than the electric power steering device. In addition, various design changes can be implemented within the scope of the matters described in the claims.

Claims

1. A motor control device, comprising: a three-phase inverter for driving an electric motor, the electric motor having a housing connected to a frame ground wire connected to a negative terminal of a power source; and a control unit, wherein a current control cycle includes a plurality of PWM cycles, the control unit controlling the three-phase inverter based on a PWM signal of a unit PWM cycle generated in each PWM cycle, The motor control device comprises: A PWM count calculation unit calculates the PWM count of a unit current control period of each of the three phases in each current control period; a noise reduction unit that sets the PWM count per unit current control period of each phase given from the PWM count calculation unit as the PWM count per unit PWM period for each PWM period in the current control period of the corresponding phase, and changes the PWM count per unit PWM period for the PWM period to a final PWM count so that a total value of the PWM count per unit PWM period in the current control period becomes a value corresponding to the PWM count per unit current control period of the corresponding phase, and in each PWM period in the current control period, a current flowing in the frame ground due to a phase voltage of any one of the three phases is offset by a current flowing in the frame ground due to a phase voltage of any one of the other two phases; and The noise canceling circuit is configured to generate a current of an opposite phase to a current flowing in the frame ground due to a phase voltage of another phase of the other two phases in each PWM period within the current control period.

2. The motor control device according to claim 1, wherein: The above-mentioned noise elimination circuit comprises: a half-bridge circuit connected to the power supply in parallel with the three-phase inverter; and The RLC circuit is connected between the midpoint of the half-bridge circuit and the frame ground wire, and is composed of a series circuit of a resistor, a coil and a capacitor.

3. The motor control device according to claim 1 or 2, wherein: The noise reduction unit includes: Setting the PWM count per unit current control period for each phase of the current control period to the unit PWM count per unit PWM period for each PWM period in the current control period in the corresponding phase; and A unit that changes the PWM count per unit PWM period of one of the other two phases in each PWM period within the current control period so that the output voltage waveform of the phase is an inverted waveform of the output voltage waveform of any one of the phases.

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