Pulse Blanking in Amplifiers

Abstract

Embodiments of the present application relate to pulse blanking in an amplifier. A circuit includes: a comparator (106) that compares an analog signal with a ramp signal to generate a pulse width modulated output signal; and a driver (112) that generates a control signal for a plurality of power transistors (M1 to M4). A pulse blanking circuit (110) receives the pulse width modulated output signal. For each pulse of the pulse width modulated output signal, the pulse blanking circuit (110) passes the pulse to the driver (112) in response to the width of the pulse being greater than a threshold. In response to the width of the pulse being less than the threshold, the pulse blanking circuit (110) prevents the pulse from being passed to the driver.

Description

[0001] Related Applications

[0002] This application claims priority to Indian Provisional Application No. 201841021304 filed on June 7, 2018, which is hereby incorporated by reference. Technical Field

[0003] Embodiments of the present application relate to electronic circuits. Background Art

[0004] Class D amplifiers are used in a variety of applications, such as for driving speakers. Class D amplifiers provide better efficiency than Class A, Class B, or Class AB amplifiers. However, at low power levels, Class D switching losses due to the inherent capacitance of the power transistors charging and discharging can be significant, especially during idle channels in audio applications (e.g., when no perceptible audio signal is to be amplified and provided to the speaker). For audio applications, the audio signal typically has a relatively high peak-to-average ratio. Typically, the input audio signal has a relatively low amplitude. In addition, the switching frequency tone is typically present in the Class D output. The tone degrades the Class D out-of-band performance and can intermodulate with the D / A converter switching frequency and also degrade the in-band noise performance. Summary of the invention

[0005] A circuit includes: a comparator that compares an analog signal with a ramp signal to generate a pulse width modulated output signal; and a driver that generates a control signal for a plurality of power transistors. A pulse blanking circuit receives the pulse width modulated output signal. For each pulse of the pulse width modulated output signal, the pulse blanking circuit passes the pulse to the driver in response to the width of the pulse being greater than a threshold. In response to the width of the pulse being less than the threshold, the pulse blanking circuit prevents the pulse from being passed to the driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various embodiments, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 An amplifier for driving a load according to an example is described.

[0008] Figure 2 exhibit Figure 1 Examples of error integrators that can be used in amplifiers.

[0009] Figure 3A An example implementation of a low-side recycle circuit is shown.

[0010] Figure 3B exhibit Figure 1 Waveforms showing the operation of the low-side loop circuit contained in the amplifier.

[0011] Figure 4 exhibit Figure 1 An example of a pulse blanking circuit included in an amplifier.

[0012] Figure 5 exhibit Figure 4 Waveform of the operation of the pulse blanking circuit.

[0013] Figure 6 Shows an example of an analog delay element that can be used in a pulse blanking circuit.

[0014] Figure 7 An example of a counter that can be used as a delay element in a pulse blanking circuit is shown.

[0015] Figure 8 A method of operating an amplifier according to an example is demonstrated. DETAILED DESCRIPTION

[0016] An amplifier (e.g., a class D amplifier) ​​is described herein that reduces switching losses by blanking pulse width modulation pulses that are narrower than a defined threshold. The threshold typically corresponds to a low input signal amplitude. The narrow pulses typically correspond to a low level of the error signal, and operating the amplifier at a low error signal level may be inefficient. By blanking the pulses used to drive the amplifier's power transistor, the amplifier is effectively turned off at low error signal levels, thereby alleviating the inefficiency problem. Once the integrated error level exceeds the threshold, pulses are again permitted to drive the amplifier's power transistor.

[0017] Figure 1 An example of amplifier 100 is shown. Figure 1 The example amplifier is implemented based on a Class D amplifier architecture. Figure 1 The amplifier includes a digital / analog converter (DAC) 101, a subtractor 102, an error integrator 104, a comparator 106, a ramp generator 107, a low-side loop (LSR) circuit 108, a pulse blanking circuit 110, a driver 112, and a plurality of transistors M1, M2, M3, and M4. In some examples, Figure 1 The analog signals in (signal 103, error signal (ERR) 105, and integrated error (INT_ERR) signal 109) are implemented as differential signals, although in other examples they may be single-ended.

[0018] Transistors M1-M4 comprise power transistors and are controlled by control signals from driver 112. Driver 112 asserts control signals to turn on and off the various transistors M1-M4 to thereby drive load 115. Figure 1In the example of , load 115 is shown as a speaker, and thus in this example, amplifier 100 is an audio amplifier. However, in other examples, load 115 may be different from a speaker. In this example, transistors M1 to M4 include n-type metal oxide semiconductor field effect transistors (NMOS), but in other examples, may be implemented as p-type metal oxide semiconductor field effect transistors (PMOS), bipolar junction transistors (n-type or p-type), or other types of transistors. The drains of M1 and M3 are coupled together and coupled to a positive supply voltage node (VDD). The source of M1 is coupled to the drain of M2, and the source of M3 is coupled to the drain of M4. The sources of M2 and M4 are coupled to a ground node.

[0019] Load 115 is coupled to node 116 interconnecting M1 and M2 and to node 117 interconnecting M3 and M4, as shown. Nodes 116 and 117 provide output voltages from amplifier 100. Driver 112 asserts control signals to each of the gates of M1 to M4 to turn each respective transistor on and off individually. For example, driver 112 turns on M1 and M4 to cause node 116 to be approximately VDD, while node 117 is approximately ground. In an alternate state, driver 112 turns on M3 and M2 to cause node 117 to be approximately VDD, while node 116 is approximately ground. M1 and M2 are not turned on at the same time and M3 and M4 are not turned on at the same time.

[0020] DAC 101 receives a digital input signal (DIG IN) 99 and converts the digital input signal into an analog signal equivalent (signal 103). Analog signal 103 is provided to subtractor 102. Output voltages from nodes 116 and 117 are also provided to subtractor 102. Subtractor 102 subtracts the output voltages across nodes 116 and 117 from analog signal 103 to generate an error signal (ERR) 105. The magnitude of error signal 105 is a function of the difference between signal 103 and the output voltage of the amplifier at node 116. Amplifier 100 reacts to error signal 105 by controlling the states of transistors M1 to M4 to reduce the magnitude of error signal 105 to zero.

[0021] Error integrator 104 integrates error signal 105 over time and generates a voltage that is a function of the error signal over time. Figure 2 An example of an error integrator 104 is shown. The example error integrator 104 includes resistors R1 and R2, capacitors C1 and C2, and an operational amplifier 200. As shown, the error signal 105 (at Figure 2) is provided to resistors R1 and R2, and the output of operational amplifier 200 is integrated error signal 109 (also a differential signal). Integrated error signal 109 includes a differential voltage proportional to the time integral of input error signal 105.

[0022] Refer to Figure 1 , the comparator 106 compares the integrated error signal 109 with a ramp signal 111 (RAMP) generated by the ramp generator 107. In some examples, the ramp generator 107 is implemented as a capacitor, a current source, and a plurality of switches. The switch is controlled to cause a constant current to charge the capacitor during the charging phase and then cause the capacitor to discharge during the discharging phase. The rate of change of the voltage across the capacitor is linear (ramp), and the voltage of the capacitor increases linearly during the charging phase and then decreases linearly during the discharging phase. The switch is controlled by a clock signal to cause the ramp generator 107 to generate a periodic ramp signal 111. In response to the integrated error signal 109 being greater than the ramp signal 111, the output signal 113 of the comparator is forced to high, and in response to the integrated error signal 109 being less than the ramp signal 111, the output signal 113 of the comparator is forced to low. The output signal 113 of the comparator is therefore a PWM output signal and is used to operate transistors M1 to M4 through LSR 108, pulse blanking circuit 110, and driver 112.

[0023] Figure 3A An example implementation of LSR 108 is shown. In this example, LSR 108 includes inverters 301 and 302 and AND gates 303 and 304. Inverter 301 receives a signal shown as COMP_OUTM, and inverter 302 receives a signal shown as COMP_OUTP. The COMP_OUTP and COMP_OUTM signals represent the differential PWM output signal 113 generated by comparator 106, and the OUTP and OUTM signals from AND gates 303 and 304 represent the output 125 of the LSR. AND gate 303 logically ANDs COMP_OUTP with an inverted version of COMP_OUTM, and AND gate 304 logically ANDs COMP_OUTM with an inverted version of COMP_OUTP. LSR 108 receives PWM output signal 113 from comparator 106 and generates output pulse signals 125 (OUT_P and OUT_M) to pulse blanking circuit 110.

[0024] Figure 3BWaveforms of signals related to the operation of LSR 108 are shown. Ramp signal 111 is generated using a clock signal (CLK). The rising and falling edges of CLK coincide with transition points in ramp signal 111. Signals INP 300 and INM 320 are examples of differential integrated error signal 109 from error integrator 104. As INP decreases, INM increases, and vice versa, as shown. Ramp signal 111 is also illustrated. In response to ramp signal 111 being greater than INP 300, COMP_OUTP is high (e.g., as shown at 330), and in response to ramp signal 111 being less than INP 300, COMP_OUTP is low (e.g., as shown at 332). Thus, the width of the pulse of COMP_OUTP is larger when INP 300 is lower than when INP 300 is higher (e.g., as indicated at 325).

[0025] Similarly, in response to ramp signal 111 being greater than INM 340, COMP_OUTM is high (e.g., shown at 340), and in response to ramp signal 111 being less than INM 320, COMP_OUTM is low (e.g., shown at 342). Thus, when INM 320 is low (e.g., indicated at 337), the width of the pulse of COMP_OUTM is smaller than when INM 320 is high (e.g., indicated at 335). Thus, the width of the pulse of COMP_OUTP is inversely proportional to the width of the pulse of COMP_OUTM.

[0026] The LSR 108 implements the truth table below. OUT_P and OUT_M represent the output signals 125 from the LSR, as described above.

[0027] Truth table for LSR 108

[0028] COMP_OUTP COMP_OUTM OUT_P OUT_M 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0

[0029] As shown, OUT_P is a logic 1 only when COMP_OUTP is 1 and COMP_OUTM is 0. OUT_M is a logic 1 only when COMP_OUTP is 0 and COMP_OUTM is 1. Thus, when the width of the COMP_OUTP pulse is wider than the width of the COMP_OUTM pulse, OUT_P is a series of pulses shown at 350, and when the width of the COMP_OUTM pulse is wider than the width of the COMP_OUTP pulse, OUT_M is a series of pulses shown at 360. M2 and M4 are turned on when OUT_P and OUT_M are 0. M2 and M3 are turned on when OUT_P is 0 and OUT_M is 1. M1 and M4 are turned on when OUT_P is 1 and OUT_M is 0.

[0030] The OUT_P and OUT_M signals are provided to a pulse blanking circuit 110 which, in response to the width of the pulse being greater than a threshold, passes the pulse to a driver 112. However, in response to the width of the pulse being less than the threshold, the pulse blanking circuit 110 prevents the pulse from being passed to the driver 112.

[0031] Figure 4 An example implementation of pulse blanking circuit 110 is shown. In this example, pulse blanking circuit 110 includes delay elements 402 and 412 and logic gates 404 and 414. Delay 412 and logic gate 414 form falling edge delay circuit 410. In this example, logic gate 404 includes an AND gate, and logic gate 414 includes an OR gate, and is referred to herein as AND gate 404 and OR gate 414, respectively. In other examples, logic gates 404 and 414 may be implemented as different from AND and OR gates, respectively. The output of AND gate 404 is signal 405, and the output of OR gate 413 is signal 145. Delay elements 402, 412 include an even number of inverters connected in series or any other type of circuit that generates an output signal that matches an input signal but delays a defined time period. The output signal from delay element 402 is signal 403, and the output signal from delay element 412 is signal 413. The delay time period of delay element 402 approximately matches the delay time period of delay element 412. The pulse blanking circuit 110 may include Figure 4 Multiple examples of the circuit shown in , one for OUT_P and another for OUT_M.

[0032] The input signal (eg, OUT_P) to the pulse blanking circuit 110 is provided to both the delay 402 and the logic gate 404. The output signal 403 of the delay element 402 is a delayed version of the input signal. Figure 5 Example waveforms are shown illustrating the operation of the pulse blanking circuit 110. Reference numeral 500 shows a single pulse of OUT_P, and reference numeral 510 shows a delayed version of the pulse as signal 403 from delay element 402. The amount of time delay (T1) corresponds to the time delay implemented by delay element 402. AND 404 receives both the original pulse 500 and the delayed pulse 510. Reference numeral 520 represents the output pulse of the AND gate on signal 405, and is therefore a logic high in response to both pulses 500 and 510 being high.

[0033] The pulse blanking circuit 110 is configured to pass an input pulse (e.g., pulse 500) to its output and driver 112 in response to the width of the input pulse being greater than a threshold. The threshold is the time delay T1 implemented by the delay element 402. As long as the width W1 of the input pulse 500 is greater than the time delay (threshold) T1, both the pulse 500 and the delayed pulse 510 will be logic high at the same time, and thus the output signal 405 of the AND gate 404 will also be logic high. The width of the pulse 520 generated by the AND gate 404 is W2, which is less than W1. However, the width of the output pulse on the signal 415 from the pulse blanking circuit 110 should be W1.

[0034] Falling edge delay circuit 410 performs the function of receiving pulse 520 from AND gate 404 and generating output pulse 540 whose rising edge 541 coincides with rising edge 521 of pulse 520 and whose falling edge 542 occurs after a time period equal to T1 of falling edge 522 of pulse 520. Delay element 412 of falling edge delay circuit 410 receives pulse 520 on signal 405 from AND gate 404 and generates signal 413 to OR gate 414, which includes pulse 530 which is a delayed version of pulse 520. The amount of delay is also T1. Output signal 145 from OR gate 414 is logic high in response to at least one of its inputs being logic high. OR gate 414 ORs signal 405 with signal 413 to produce pulse 540, as shown. The resulting output pulse 540 from pulse blanking circuit 110 has width W1, which is the same as the width of pulse 500. Thus, pulse 540 on signal 145 provided to driver 112 has the same width as the input pulse generated by LSR 108 but is slightly delayed in time due to time delay T1 of delay element 402. This time delay in the pulse provided to driver 112 does not affect the performance of amplifier 100. Pulse 500 passes through pulse blanking circuit 110 to the driver because its width W1 is greater than the threshold implemented by delay element 402.

[0035] Still refer to Figure 5 , another example of pulse 560 is shown as the OUT_P signal. However, the width W3 of pulse 560 is less than T1. Thus, by the time delayed pulse 570 is generated by delay element 402, the falling edge of pulse 560 has already occurred. Therefore, output signal 405 of AND gate 404 does not become a logic high, and the output signal of OR gate 414 remains at a logic low level. Pulse blanking circuit 110 thus blanks pulse 560 to prevent it from reaching driver 112.

[0036] Figure 6An example implementation of either or both of the delay elements 402 and 412 is shown. This example implementation includes an analog delay element and includes capacitors C1, C2, ..., Cn. A corresponding switch (e.g., a transistor) is coupled to each capacitor. Therefore, SW1 is coupled to C1, and SW2 ... SWn are coupled to C2 ... Cn, respectively, as shown. The switch labeled SW_EN is an activation switch and is controlled by an input signal 602, which is a signal to be delayed by the delay element. Switches SW_EN, SW1, SW2, ... SWn are coupled together and coupled to the input of the current source I1 and the comparator 610. A reference voltage VREF couples another input to the comparator 610. Switch SW_EN is usually closed (turned on), which causes the voltage on node 615 (which is provided to the negative input of the comparator 610) to be the supply voltage AVDD provided to the capacitors C1 to Cn. The output signal 625 of the comparator 610 is a logic low because VREF is selected to be less than AVDD. The voltage drop across the capacitor is zero due to the short circuit closure caused by SW_EN.

[0037] After receiving the rising edge of the signal to be delayed on signal 602, the switch SW_EN is opened (turned off), which in turn causes the capacitor to charge due to the constant current from the current source I1. The capacitors C1 to Cn that are charged are only those whose corresponding switches SW1 to SWn are closed and whose switches are independently configured to implement the desired time delay. The voltage across those capacitors C1 to Cn whose switches SW1 to SWn are closed increases due to the constant current from the current source I1. As one plate of each capacitor C1 to Cn is coupled to the fixed voltage AVDD, the voltage on the opposite plate coupled to the node 615 decreases, and decreases at a substantially linear rate, which is a function of the value of the sum of the capacitance and the magnitude of the current from the current source I1. Therefore, the rate of change of the voltage on the node 615 can be controlled by the selective closure of the switches SW1 to SWn. In one example, the more switches SW1 to SWn are closed, the longer it takes for the voltage on the node 615 to drop to a level below VREF. Once the voltage on node 615 drops below VREF, the output signal 625 of comparator 610 is forced high. Once input signal 602 experiences a falling edge, enable switch SW_EN closes, which forces the voltage on node 615 back to AVDD and the output 625 of comparator 610 becomes logic low again.

[0038] The time delay between the time when the input signal experiences a rising edge to the time when the output signal experiences a rising edge (i.e., the time delay of delay elements 402, 412) is a controllable selection of an appropriate number of switches SW1 to SWn. The capacitance values ​​of capacitors C1 to Cn may all be the same, or two or more capacitors may have different capacitance values.

[0039] Figure 7 The example of delay elements 402 and 412 is shown as including a counter. The counter may include a Johnson counter or other suitable counter. In this example, the counter includes a series of flip-flops 702, 704, 706, and 708. The Q output of flip-flop 702 is provided to the D input of flip-flop 704. The Q output of flip-flop 704 is provided to the D input of flip-flop 706. The Q output of flip-flop 706 is provided to the D input of flip-flop 708, and the Qbar output of flip-flop 708 is provided to the D input of flip-flop 702. Figure 7 The reset signal (RESET) shown in FIG. 1 resets the flip-flop. The clock signal (CLK) has a frequency, and the period of CLK defines the blanking resolution.

[0040] Figure 8 804, the method includes determining a delay ( Figure 3B The method determines whether the pulse width is less than a threshold value (Th1) in the delay. The size of the threshold value Th1 is configured to identify that the pulse is of a sufficiently wide width that it will not be blanked by the pulse blanking circuit 110. If the delay is less than Th1, the pulse is passed to the driver 112. If the delay is greater than Th1, the method includes determining (810) whether the pulse width is less than a different threshold value Th2. If the pulse width is less than Th2, then at 812 the pulse is masked. The pulse blanking circuit performs this operation. However, if the pulse width is greater than Th2, then at 814 the pulse is passed to the driver 112 as described above.

[0041] In this description, the term "couple" or "couples" means an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. "About" means the same as or within plus or minus 10% of another value or range of values.

[0042] Modifications are possible in the embodiments described, and other embodiments are possible within the scope of the claims.

Claims

1. An electronic circuit comprising: a comparator that compares the analog signal with the ramp signal to generate a pulse width modulated output signal; a driver that generates control signals for the plurality of power transistors; and A pulse blanking circuit receives the pulse width modulated output signal and for each pulse of the pulse width modulated output signal: In response to the width of the pulse being greater than a threshold, the pulse blanking circuit transmits the pulse to the driver for generating control signals for the plurality of power transistors; and In response to the width of the pulse being less than the threshold, the pulse blanking circuit prevents the pulse from being delivered to the driver.

2. The electronic circuit of claim 1 , wherein the pulse blanking circuit comprises: a first delay element coupled to receive the pulse width modulated output signal and to generate a delay element output signal, the delay element output signal being a delayed version of the pulse width modulated output signal; a first logic gate coupled to an output of the first delay element; and A falling edge delay circuit is coupled to the output of the logic gate.

3. The electronic circuit of claim 2, wherein the first logic gate comprises an AND gate comprising a first input and a second input, the first input receiving the delay element output signal and the second input receiving the pulse width modulated output signal.

4. The electronic circuit of claim 2 , wherein the falling edge delay circuit generates a falling edge delay circuit output signal that replicates an output pulse from the logic gate, wherein a falling edge of the replicated output pulse includes a time delay approximately equal to a time delay of the first delay element.

5. The electronic circuit of claim 2, wherein the falling edge delay circuit comprises a second delay element and a second logic gate. The electronic circuit of claim 2 , wherein the first delay element comprises a counter.

7. The electronic circuit of claim 2, wherein the first delay element comprises an analog delay circuit.

8. The electronic circuit of claim 7, wherein the analog delay circuit comprises: Multiple capacitors; a plurality of transistor switches, each transistor switch coupled to a respective capacitor; Start switch; a current source device coupled to the enable transistor switch and each combination of the transistor switch and a corresponding capacitor; and A comparator includes first and second inputs, the first input coupled to each combination of the enable switch and transistor switch and a respective capacitor, and the second input coupled to receive a reference voltage.

9. The electronic circuit of claim 1, further comprising the plurality of power transistors and a speaker coupled to the plurality of power transistors.

10. The electronic circuit of claim 1, further comprising: Digital / analog converter DAC; a subtractor coupled to the DAC, the subtractor generating an error signal comprising a difference between an output signal from the DAC and a voltage generated by at least one of the plurality of transistors; and an error integrator that integrates the error signal from the subtractor to generate the analog signal for the comparator.

11. An electronic circuit comprising: a first delay element coupled to receive an input pulse, the input pulse having a width; a first logic gate comprising first and second inputs, the first input coupled to an output of the first delay element and the second input directly coupled to receive the input pulse; a second delay element coupled to the output of the first logic gate; and A second logic gate includes third and fourth inputs, the third input coupled to the output of the second delay element and the fourth input coupled directly to the output of the first logic gate, wherein the first logic gate comprises an AND gate and the second logic gate comprises an OR gate.

12. The electronic circuit of claim 11, wherein each of the first and second delay elements implement approximately the same time delay.

13. The electronic circuit of claim 11, wherein at least one of the first and second delay elements comprises a counter.

14. The electronic circuit of claim 11, wherein at least one of the first and second delay elements comprises an analog delay circuit.

15. The electronic circuit of claim 14, wherein the analog delay circuit comprises: Multiple capacitors; a plurality of transistor switches, each transistor switch coupled to a respective capacitor; Start switch; a current source device coupled to the enable transistor switch and each combination of the transistor switch and a corresponding capacitor; and A comparator includes first and second inputs, the first input coupled to each combination of the enable switch and transistor switch and a respective capacitor, and the second input coupled to receive a reference voltage.

16. An electronic circuit comprising: a comparator that compares the analog signal with the ramp signal to generate a pulse width modulated output signal; a driver that generates control signals for the plurality of power transistors; and A pulse blanking circuit receives the pulse width modulated output signal and, in response to each pulse of the pulse width modulated output signal being less than a threshold, prevents the pulse from being passed to the driver.

17. The electronic circuit of claim 16, wherein in response to each pulse of the pulse width modulated output signal being greater than the threshold, the pulse blanking circuit passes the pulse to the driver.

18. The electronic circuit of claim 16, wherein the pulse blanking circuit comprises: a first delay element coupled to receive the pulse width modulated output signal and to generate a delay element output signal, the delay element output signal being a delayed version of the pulse width modulated output signal; a first logic gate coupled to an output of the first delay element; and A falling edge delay circuit is coupled to the output of the logic gate.

19. The electronic circuit of claim 18, wherein the falling edge delay circuit generates a falling edge delay circuit output signal that replicates an output pulse from the first logic gate, wherein a falling edge of the replicated output pulse includes a time delay approximately equal to a time delay of the first delay element.

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