An IO port multiplexing circuit

Abstract

An IO port multiplexing circuit includes: N signal receiving ends for receiving N input signals; each of the signal receiving ends is connected to each of the input signals in a one-to-one correspondence; N square wave generators are used to receive the N input signals on the N signal receiving ends and convert the N input signals into N different square wave signals; each of the square wave generators is connected to each of the signal receiving ends in a one-to-one correspondence; an IO port for receiving the N square wave signals; the IO port is respectively connected to the N square wave generators; an identifier is used to receive the N square wave signals on the IO port and use its own interrupt to count the N square wave signals to identify the N input signals. The IO port multiplexing circuit provided by the present invention can detect two or more input signals simultaneously through one IO port, and can detect multiple input signals without adding channel switching signals or communication conversion chips.

Description

Technical Field

[0001] The invention belongs to the technical field of signal detection circuits, and in particular relates to an IO port multiplexing circuit. Background Art

[0002] In the signal detection circuit, DSP / MCU is often used to detect the signal. The specific method is as follows:

[0003] (1) For multiple signals, multiple IO ports are used to detect multiple signals and transmit the signals to DSP / MCU;

[0004] (2) Use line selection chips to switch each channel for detection separately, or use communication buses such as I2C to transmit the levels of multiple input signals to the DSP / MCU.

[0005] However, this approach has the following disadvantages:

[0006] (1) It is necessary to set up multiple IO ports at the DSP / MCU pins, and multiple components are required;

[0007] (2) It is necessary to switch channels for detection, which is a complicated method and can easily lead to confusion. Summary of the invention

[0008] In order to solve the above problems, the present invention provides an IO port multiplexing circuit, comprising:

[0009] N signal receiving ends, used to receive N input signals; each of the signal receiving ends is connected to each of the input signals in a one-to-one correspondence;

[0010] N square wave generators, used for receiving the N input signals on the N signal receiving ends, and converting the N input signals into N mutually different square wave signals; each of the square wave generators is connected to each of the signal receiving ends in a one-to-one correspondence;

[0011] An IO port, used to receive the N square wave signals; the IO port is connected to the N square wave generators respectively;

[0012] The identifier is used to receive the N square wave signals on the IO port and use its own interrupt to count the N square wave signals to identify the N input signals.

[0013] Preferably, the identifier comprises a DSP or an MCU.

[0014] Preferably, the square wave generator includes a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor and a comparator, wherein the anode of the first diode is grounded and the cathode is connected to the signal receiving end, the anode of the second diode is connected to the signal receiving end and the cathode is connected to the first positive potential, the first end of the first resistor is connected to the second positive potential and the second end is connected to the first end of the second resistor and the positive input end of the comparator respectively, the second end of the second resistor is connected to the signal receiving end, the first end of the third resistor is connected to the positive input end of the comparator and the second end is connected to the IO port, the negative input end of the comparator is connected to the first end of the first capacitor and the first end of the fourth resistor respectively, the second end of the first capacitor is grounded, the second end of the fourth resistor is connected to the IO port, the output end of the comparator is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the IO port.

[0015] Preferably, the comparator model is LM2903.

[0016] Preferably, the first positive potential and the second positive potential are both 5V.

[0017] Preferably, the square wave generator includes a sixth resistor, a seventh resistor, a second capacitor, a third capacitor and an oscillator, the VCC terminal of the oscillator is respectively connected to its own RESET terminal, the first end of the sixth resistor, the first end of the seventh resistor and the third positive potential, the CONT terminal of the oscillator is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the second end of the sixth resistor is respectively connected to the DISCH terminal, the THRES terminal and the first end of the third capacitor of the oscillator, the second end of the third capacitor is grounded, the OUT terminal of the oscillator is respectively connected to the second end of the seventh resistor and the IO port, the TRIG terminal of the oscillator is connected to the signal receiving terminal, and the GND terminal of the oscillator is grounded.

[0018] Preferably, the model of the oscillator is NE555.

[0019] Preferably, the third positive potential is in the range of 5-15V.

[0020] Preferably, among the N different square wave signals, any one of the frequencies and duty cycles of any two of the square wave signals are different from each other.

[0021] Preferably, when N is 2, among the frequencies of the two square wave signals, the larger frequency is at least 3 times the smaller frequency.

[0022] The IO port multiplexing circuit provided by the present invention has the following advantages:

[0023] (1) This circuit can be used to simultaneously detect two or more input signals through one IO port, without the need to add additional channel switching signals or detect multiple input signals through a communication conversion chip;

[0024] (2) Reduce the number of IO ports used, save processor hardware resources, and facilitate expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0026] Figure 1 It is a principle block diagram of an IO port multiplexing circuit provided by the present invention;

[0027] Figure 2 This is a connection diagram of an IO port multiplexing circuit provided by the present invention;

[0028] Figure 3 This is a schematic diagram of a square wave generator embodiment 1 of an IO port multiplexing circuit provided by the present invention;

[0029] Figure 4 This is a schematic diagram of a square wave generator embodiment 2 of an IO port multiplexing circuit provided by the present invention;

[0030] Figure 5 This is a connection diagram of Example 1 of an IO port multiplexing circuit provided by the present invention;

[0031] Figure 6 This is a connection diagram of Example 2 of an IO port multiplexing circuit provided by the present invention;

[0032] Figure 7 This is a connection diagram of Example 3 of an IO port multiplexing circuit provided by the present invention;

[0033] Figure 8 This is a connection diagram of Example 4 of an IO port multiplexing circuit provided by the present invention;

[0034] Fig. 9 It is a waveform diagram of an IO port multiplexing circuit provided by the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

[0036] like Figure 1 and 2 The present invention provides an IO port multiplexing circuit, including: a signal receiving end, a square wave generator, an IO port and an identifier. Each part is described in detail below.

[0037] like Figure 1 and 2 In an embodiment of the present application, the present invention provides an IO port multiplexing circuit, comprising:

[0038] N signal receiving ends, used to receive N input signals; each of the signal receiving ends is connected to each of the input signals in a one-to-one correspondence;

[0039] N square wave generators, used for receiving the N input signals on the N signal receiving ends, and converting the N input signals into N mutually different square wave signals; each of the square wave generators is connected to each of the signal receiving ends in a one-to-one correspondence;

[0040] An IO port, used to receive the N square wave signals; the IO port is connected to the N square wave generators respectively;

[0041] The identifier is used to receive the N square wave signals on the IO port and use its own interrupt to count the N square wave signals to identify the N input signals.

[0042] like Figure 2 In an embodiment of the present application, the identifier includes a DSP or an MCU.

[0043] like Figure 3In the embodiment of the present application, the square wave generator includes a first diode, a second diode, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1 and a comparator U1A, wherein the anode of the first diode is grounded and the cathode is connected to the signal receiving end, the anode of the second diode is connected to the signal receiving end and the cathode is connected to the first positive potential, the first end of the first resistor R1 is connected to the second positive potential and the second end is connected to the first end of the second resistor R2 and the positive input end of the comparator U1A respectively, the second end of the second resistor R2 is connected to the signal receiving end, the first end of the third resistor R3 is connected to the positive input end of the comparator U1A and the second end is connected to the IO port, the negative input end of the comparator U1A is connected to the first end of the first capacitor C1 and the first end of the fourth resistor R4 respectively, the second end of the first capacitor C1 is grounded, the second end of the fourth resistor R4 is connected to the IO port, the output end of the comparator U1A is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the IO port. When the square wave generator is used, the actually required square wave frequency f and duty cycle D are generated by selecting resistors R1 - R5 and the first capacitor C1 with appropriate parameters.

[0044] like Figure 3 In the embodiment of the present application, the comparator model is LM2903, and the first positive potential and the second positive potential are both 5V.

[0045] like Figure 4 In the embodiment of the present application, the square wave generator includes a sixth resistor RA, a seventh resistor RL, a second capacitor, a third capacitor and an oscillator, the VCC end of the oscillator is respectively connected to its own RESET end, the first end of the sixth resistor RA, the first end of the seventh resistor RL and the third positive potential, the CONT end of the oscillator is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the second end of the sixth resistor RA is respectively connected to the DISCH end, the THRES end and the first end of the third capacitor of the oscillator, the second end of the third capacitor is grounded, the OUT end of the oscillator is respectively connected to the second end of the seventh resistor RL and the IO port, the TRIG end of the oscillator is connected to the signal receiving end, and the GND end of the oscillator is grounded. When using this square wave generator, the actual required square wave frequency f and duty cycle D are generated by selecting resistors RA, RL, the second capacitor and the third capacitor with appropriate parameters.

[0046] like Figure 4 In the embodiment of the present application, the model of the oscillator is NE555, and the range of the third positive potential is 5-15V.

[0047] In an embodiment of the present application, among the N different square wave signals, any one of the frequencies and duty cycles of any two of the square wave signals are different from each other, that is, when the frequency f and duty cycle D of one square wave signal are different from any one of the frequency F and duty cycle d of another square wave signal, the two square wave signals are different.

[0048] like Figure 5-9 , which is an embodiment when N=2, the working principle of an IO port multiplexing circuit of this application is described in detail below.

[0049] Specifically, for two input signals, two square wave generators are used to generate two square wave signals, with frequencies of f1 and f2 (the larger one is at least 3 times the smaller one, which can have a greater degree of distinction), and duty cycles of D1 and D2, respectively. Then, the signal can be distinguished according to the following table:

[0050]

[0051]

[0052] Among them, "1" and "0" respectively indicate that the input signal state is "high level" and "low level".

[0053] Embodiment 1:

[0054] like Figure 5 As shown, when the input signals 1 and 2 are both "1", the outputs of the square wave generator are both high level, and the outputs to the IO port are also high level, and the duty cycle is 100%.

[0055] Embodiment 2:

[0056] like Figure 6 and 9 As shown, when the input signal 1 is "0" and the input signal 2 is "1", after passing through the square wave generator, signal 1 becomes a square wave with a frequency of f1 and a duty cycle of D1, and signal 2 is a high level. After the two are connected to one place, the input IO is a square wave with a frequency of f1 and a duty cycle of D1.

[0057] Embodiment 3:

[0058] like Figure 7 and 9 As shown, when the input signal 1 is "1" and the input signal 2 is "0", signal 1 still maintains a high level after passing through the square wave generator, and signal 2 becomes a square wave with a frequency of f2 and a duty cycle of D2. After the two are connected to one place, the input IO is a square wave with a frequency of f2 and a duty cycle of D2.

[0059] Embodiment 4:

[0060] like Figure 8 and 9 As shown, when both input signals are "0", after passing through the square wave generator, signal 1 becomes a square wave with a frequency of f1 and a duty cycle of D1, and signal 2 becomes a square wave with a frequency of f2 and a duty cycle of D2. After the two are connected to one place, the input IO is a waveform with a duty cycle of D1*D2.

[0061] Therefore, when the input signal exhibits different levels, the duty cycle of the signal input to the IO port is different. The identifier can determine the levels of input signals 1 and 2 by judging the duty cycle of the input signal, thereby realizing the detection of multiple input signal states with only one IO port.

[0062] When N>2, the same logic applies. The maximum number of detectable signals can be determined by the interrupt frequency of the identifier (DSP or MCU).

[0063] The IO port multiplexing circuit provided by the present invention has the following advantages:

[0064] (1) This circuit can be used to simultaneously detect two or more input signals through one IO port, without the need to add additional channel switching signals or detect multiple input signals through a communication conversion chip;

[0065] (2) Reduce the number of IO ports used, save processor hardware resources, and facilitate expansion.

[0066] It should be understood that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. An IO port multiplexing circuit, characterized in that: include: N signal receiving ends, used for receiving N input signals; Each of the signal receiving ends is connected to each of the input signals in a one-to-one correspondence; N square wave generators, used for receiving the N input signals on the N signal receiving ends, and converting the N input signals into N mutually different square wave signals; each of the square wave generators is connected to each of the signal receiving ends in a one-to-one correspondence; An IO port, used to receive the N square wave signals; the IO port is connected to the N square wave generators respectively; Identifier, for receiving the N square wave signals on the IO port, and using its own interrupt to count the N square wave signals to identify the N input signals; The square wave generator includes a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor and a comparator, wherein the anode of the first diode is grounded and the cathode is connected to the signal receiving end, the anode of the second diode is connected to the signal receiving end and the cathode is connected to the first positive potential, the first end of the first resistor is connected to the second positive potential and the second end is connected to the first end of the second resistor and the positive input end of the comparator respectively, the second end of the second resistor is connected to the signal receiving end, the first end of the third resistor is connected to the positive input end of the comparator and the second end is connected to the IO port, the negative input end of the comparator is connected to the first end of the first capacitor and the first end of the fourth resistor respectively, the second end of the first capacitor is grounded, the second end of the fourth resistor is connected to the IO port, the output end of the comparator is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the IO port; Among the N different square wave signals, any one of the frequencies and duty cycles of any two of the square wave signals is different from each other.

2. The IO port multiplexing circuit according to claim 1, characterized in that: The identifier includes a DSP or an MCU.

3. The IO port multiplexing circuit according to claim 1, characterized in that: The comparator model is LM2903.

4. The IO port multiplexing circuit according to claim 1, characterized in that: The first positive potential and the second positive potential are both 5V.

5. The IO port multiplexing circuit according to claim 1, characterized in that: The square wave generator includes a sixth resistor, a seventh resistor, a second capacitor, a third capacitor and an oscillator. The VCC terminal of the oscillator is respectively connected to its own RESET terminal, the first end of the sixth resistor, the first end of the seventh resistor and the third positive potential, the CONT terminal of the oscillator is connected to the first end of the second capacitor, the second end of the second capacitor is grounded, the second end of the sixth resistor is respectively connected to the DISCH terminal, the THRES terminal and the first end of the third capacitor of the oscillator, the second end of the third capacitor is grounded, the OUT terminal of the oscillator is respectively connected to the second end of the seventh resistor and the IO port, the TRIG terminal of the oscillator is connected to the signal receiving terminal, and the GND terminal of the oscillator is grounded.

6. The IO port multiplexing circuit according to claim 5, characterized in that: The model of the oscillator is NE555.

7. The IO port multiplexing circuit according to claim 6, characterized in that: The third positive potential ranges from 5V to 15V.

8. The IO port multiplexing circuit according to claim 1, characterized in that: When N is 2, among the frequencies of the two square wave signals, the larger frequency is at least 3 times the smaller frequency.

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