A high capacitance array substrate and manufacturing method thereof

Abstract

The present invention discloses an array substrate with a high capacitance structure and a manufacturing method thereof, wherein the method comprises the following steps: manufacturing a buffer layer on the array substrate; manufacturing a hole on the buffer layer; manufacturing a first electrode in the hole; manufacturing a first electrode insulating layer covering the first electrode in the hole; manufacturing a second electrode on the first electrode insulating layer in the hole, and manufacturing a second electrode insulating layer covering the second electrode in the hole; manufacturing a third electrode on the second insulating layer in the hole; and further arranging a thin film field effect transistor on the buffer layer outside the hole; the thin film field effect transistor with a high capacitance structure is manufactured by this scheme, and the circuit driven by the high capacitance structure has a better voltage stabilizing effect, can increase the capacitance of the storage capacitor while reducing the occupied area of ​​the capacitor, and also has the advantages of increasing the pixel density (ppi) of the panel and reducing the size of the panel frame.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate with a high capacitance structure and a manufacturing method thereof. Background Art

[0002] The rapid development of active matrix organic light emitting diode displays (AMOLED) and high performance active matrix liquid crystal displays (AMLCD) has led to many high resolution and high frame rate displays. In order to make the drive circuit have a better voltage stabilization effect in the array substrate, a large capacitance capacitor is usually required. However, the large capacitance capacitor causes the drive circuit to occupy a large area, making it impossible to further reduce the display panel frame size and pixel size. Therefore, how to design and prepare a high performance and small size array substrate structure has become a research topic that needs to be tackled more and more.

[0003] IGZO (indium gallium zinc oxide) is an amorphous oxide containing indium, gallium and zinc. Its carrier mobility is 20 to 30 times that of amorphous silicon. It can greatly increase the charging and discharging rate of TFT to pixel electrodes, improve the response speed of pixels, have a faster panel refresh rate, and realize ultra-high-resolution display panels. At the same time, existing amorphous silicon production lines only need to be slightly modified to be compatible with IGZO processes, so they are more competitive than low-temperature polysilicon (LTPS) in terms of cost. Summary of the invention

[0004] Therefore, it is necessary to provide an array substrate with a high capacitance structure and a manufacturing method thereof, so as to solve the problem of excessive area occupation when high capacitance is provided in manufacturing a display device.

[0005] To achieve the above object, the inventor provides a method for manufacturing an array substrate with a high capacitance structure, comprising the following steps:

[0006] forming a buffer layer on the array substrate;

[0007] making holes in the buffer layer;

[0008] Depositing a first layer of metal to form a first electrode in the hole, the first electrode serving as a plate of a lower capacitor structure;

[0009] After covering the first insulating layer, continue to deposit a second layer of metal to form a first electrode insulating layer covering the first electrode in the hole, and form a second electrode on the first electrode insulating layer in the hole, the second electrode serving as a common electrode plate of the upper and lower layer capacitor structures;

[0010] Covering the second insulating layer, forming a second electrode insulating layer covering the second electrode in the hole;

[0011] Depositing a third layer of metal to form a third electrode on the second insulating layer in the hole, the third electrode serving as a plate of the upper capacitor structure;

[0012] A thin film field effect transistor is also arranged on the buffer layer outside the hole.

[0013] Furthermore, the method further comprises the following steps:

[0014] When depositing the first layer of metal, extend the first electrode in the hole to the surface of the buffer layer; or: after covering the first insulating layer, when continuing to deposit the second layer of metal, extend the second electrode in the hole and the first electrode insulating layer to the surface of the buffer layer outside the hole; or: when covering the second insulating layer, extend the second electrode insulating layer in the hole to the surface of the buffer layer outside the hole; or: when depositing the third layer of metal, extend the third electrode in the hole to the surface of the buffer layer outside the hole; or: connect the third electrode on the surface of the buffer layer outside the hole with the first electrode on the surface of the buffer layer outside the hole.

[0015] Furthermore, the thin film field effect transistor is manufactured by the following steps:

[0016] After depositing the first layer of metal, continue to deposit the gate metal, and form the first metal and the gate scanning line on the buffer layer outside the hole, the first metal is on the buffer layer outside the hole, and the gate scanning line is on the first metal;

[0017] After covering the first insulating layer, continue to deposit a second metal layer to form a gate insulating layer on the gate scanning line, the gate insulating layer covers and wraps the gate scanning line and the first metal, and forms the second metal on the gate insulating layer;

[0018] forming a barrier layer on the second metal while covering the second insulating layer;

[0019] When depositing the third metal layer, a third metal is formed on the barrier layer to wrap around the second metal and both sides of the barrier layer, and the third metal is exposed from the central part of the barrier layer;

[0020] A fourth layer of metal is deposited to form a source signal line on one side of the third metal and a drain on the other side of the third metal.

[0021] Furthermore, after depositing the first metal layer, when continuing to deposit the gate metal, the following steps are also included:

[0022] A photoresist is coated on the gate metal, and the photoresist is patterned using a half-color mask having a semi-transparent area, a fully transparent area, and a fully shading area. After the photoresist is developed, the semi-transparent area corresponds to an incompletely developed area, the fully transparent area or the fully shading area corresponds to a fully developed area, the incompletely developed area corresponds to an area of ​​the first electrode in the capacitor structure, and the fully developed area corresponds to an area of ​​the gate scanning line;

[0023] Using the photoresist as a mask, etching the gate metal and the first metal layer on the area outside the complete development area and the incomplete development area;

[0024] The photoresist on the first metal layer in the incompletely developed area is removed by ashing, and the photoresist on the gate metal in the fully developed area is retained;

[0025] The gate metal in the incompletely developed area is etched to the first metal layer, the first metal layer is retained as the first electrode, and the photoresist on the completely developed area is removed to form the first metal and the gate scanning line.

[0026] Furthermore, after covering the first insulating layer, when continuing to deposit the second metal layer, the following steps are also included:

[0027] Coating a photoresist on the second metal layer, and patterning the photoresist using a half-color mask having a semi-transparent area, a fully transparent area, and a fully shading area, wherein after developing the photoresist, the semi-transparent area corresponds to an incompletely developed area, and the fully transparent area or the fully shading area corresponds to a fully developed area, wherein the incompletely developed area corresponds to an area of ​​the second electrode in the capacitor structure, and the fully developed area corresponds to an area of ​​the second metal;

[0028] The second layer of metal on the area outside the incomplete development area and the complete development area is etched, the photoresist on the second layer of metal in the incomplete development area is removed by ashing treatment, and then hydrogen ions are implanted to remove the photoresist on the first insulating layer material in the complete development area, and the second layer of metal and the first insulating layer in the incomplete development area are retained as the second electrode and the first electrode insulating layer, respectively, and the second layer of metal and the first insulating layer in the complete development area are retained as the second metal and the gate insulating layer, respectively.

[0029] Further, the method further comprises the following steps:

[0030] A third insulating layer material is covered, and a passivation layer is formed on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, wherein the passivation layer protects the capacitor structure and the thin film field effect transistor.

[0031] Furthermore, the material of the first metal layer is indium tin oxide.

[0032] The present invention provides an array substrate with a high capacitance structure, characterized in that the array substrate with a high capacitance structure is manufactured by any one of the above-mentioned methods for manufacturing an array substrate with a high capacitance structure.

[0033] The present invention provides an array substrate with a high capacitance structure, comprising:

[0034] A buffer layer is arranged on the array substrate, a hole is arranged on the buffer layer, and a thin film field effect transistor is arranged on the buffer layer outside the hole;

[0035] A first electrode, a first electrode insulating layer, a second electrode, a second electrode insulating layer and a third electrode are sequentially arranged on the surface of the buffer layer in the hole and between the holes. The first electrode serves as a plate of a lower capacitor structure, the first electrode insulating layer covers the first electrode and serves as a dielectric layer of the lower capacitor structure, the second electrode is on the first electrode insulating layer and serves as a common plate of the upper and lower capacitor structures, the second electrode insulating layer covers the second electrode and serves as a dielectric layer of an upper capacitor structure, and the third electrode is on the second electrode insulating layer and serves as a plate of the upper capacitor structure.

[0036] Furthermore, the thin film field effect transistor comprises:

[0037] A first metal is arranged on the buffer layer outside the hole, and a gate scanning line is arranged on the first metal;

[0038] A gate insulating layer is arranged on the gate scanning line, and the gate insulating layer covers and wraps the gate scanning line and the first metal;

[0039] A second metal is disposed on the gate insulating layer, and a barrier layer is disposed on the second metal;

[0040] A third metal is arranged on the barrier layer, the third metal wraps around the second metal and both sides of the barrier layer, the third metal exposes the central part of the barrier layer, a source signal line is arranged on one side of the third metal, and a drain is arranged on the other side of the third metal.

[0041] Different from the existing technology, the above technical solution produces a thin film field effect transistor with a high capacitance structure. The circuit driven by the high capacitance structure has a better voltage stabilization effect, can increase the capacitance of the storage capacitor while reducing the occupied area of ​​the capacitor, and also has the advantages of increasing the panel pixel density (ppi) and reducing the size of the panel frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the cross-sectional structure of manufacturing a buffer layer and holes on an array substrate according to the present invention;

[0043] Figure 2 The process flow chart of manufacturing the first electrode, the first metal and the gate scanning line on the array substrate of the present invention;

[0044] Figure 3 A process flow chart of manufacturing a first electrode insulating layer, a gate insulating layer, a second electrode and a second metal on an array substrate according to the present invention;

[0045] Figure 4 It is a schematic cross-sectional structure diagram of manufacturing a second electrode insulating layer and a barrier layer on an array substrate according to the present invention;

[0046] Figure 5is a schematic cross-sectional structure diagram of a thin film field effect transistor according to another embodiment of the present invention;

[0047] Figure 6 It is a schematic cross-sectional structure diagram of manufacturing a third electrode, a third metal, a source signal line and a drain on an array substrate according to the present invention;

[0048] Figure 7 It is a schematic diagram of the cross-sectional structure of manufacturing a passivation layer on an array substrate according to the present invention;

[0049] Figure 8 It is a schematic diagram of the structure of the grid-like capacitor structure connected in parallel according to the present invention;

[0050] Fig. 9 It is a schematic diagram of the cross-sectional structure of the gate-like capacitor structure of the present invention.

[0051] Description of reference numerals:

[0052] 1. Array substrate;

[0053] 2. Buffer layer;

[0054] 201, hole;

[0055] 3. The first layer of metal;

[0056] 301, a first electrode;

[0057] 302, first metal;

[0058] 4. Gate metal;

[0059] 401, gate scanning line;

[0060] 5. Half-color mask;

[0061] 6. The first insulating layer;

[0062] 601, a first electrode insulating layer;

[0063] 602, gate insulating layer;

[0064] 7. Second layer of metal;

[0065] 701, a second electrode;

[0066] 702, second metal;

[0067] 8. Second insulating layer;

[0068] 801, a second electrode insulating layer;

[0069] 802, barrier layer;

[0070] 9. The third layer of metal;

[0071] 901, third electrode;

[0072] 902, tertiary metal;

[0073] 10. The fourth layer of metal;

[0074] 1001, source signal line;

[0075] 1002, drain;

[0076] 1100. Passivation layer. DETAILED DESCRIPTION

[0077] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0078] See also Figures 1 to 9 This embodiment provides a method for manufacturing an array substrate with a high capacitance structure. This method can be performed on an array substrate 1. A field thin film effect transistor is manufactured on one side of the array substrate 1, and a capacitance structure is manufactured on the other side of the array substrate 1. The method includes the following steps: manufacturing a buffer layer 2 and a hole 201 on the array substrate 1; referring to Figure 1 , the specific process is to cover a buffer layer 2 on the array substrate 1, and the material of the buffer layer 2 is one or more of organic photosensitive materials, polyimide (PI), silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), and titanium oxide. After the buffer layer 2 is made, a hole 201 is made on the buffer layer 2; a photoresist is coated on the buffer layer 2, and the photoresist is patterned, that is, the exposure and development are performed to open the part where the hole 201 is to be made, and then the buffer layer 2 is etched with the photoresist as a mask to obtain the hole, and the photoresist is removed after the hole is made. This production method can produce multiple holes 201 at the same time, and the cross section of the hole 201 can be rectangular, circular, or other irregular shapes. For example, the production method shows that the cross section of the hole 201 is rectangular, and the width of the cross section gradually decreases from top to bottom, and the width of the bottom of the hole is smaller than the width of the hole mouth, thereby forming a hole 201 with a strip grid structure, and a grid capacitor structure can be made in the hole 201 and between the holes 201 and the holes 201.

[0079] Next, the first metal layer 3 and the gate metal 4 are formed on the array substrate 1 to form the first electrode 301, the first metal 302 and the gate scanning line 401; see Figure 2 The specific process steps are as follows: the first metal layer 3 and the gate metal 4 are plated on the array substrate 1 by electroplating, evaporation or sputtering, and the gate metal 4 covers the first metal layer 3. The structure is as follows Figure 2As shown in the first figure. The material of the first metal layer 3 is indium tin oxide (ITO), and the thickness of the indium tin oxide film is relatively thin, ranging from 100 angstroms to 1000 angstroms. The material of the gate metal 4 is one or more metals with good conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, or other alloys. Then, the photoresist on the gate metal 4 is patterned using a half-color mask 5 having a semi-transparent area 501, a fully transparent area 502, and a fully shielded area 503. The structure is as shown in FIG. Figure 2 As shown in the second figure. The light transmittance of the semi-transparent area 501 is 50%, the light transmittance of the fully transparent area 502 is 100%, and the light transmittance of the fully shading area 503 is 0%. After the photoresist is developed, the semi-transparent area 501 corresponds to the incomplete development area, the fully transparent area 502 or the fully shading area 503 corresponds to the fully developed area, the incomplete development area corresponds to the area of ​​the first electrode 301 in the capacitor structure, and the fully developed area corresponds to the area of ​​the gate scanning line 401 of the thin film field effect transistor. Wherein, if a negative photoresist is applied, the semi-transparent area 501 corresponds to the incomplete development area, i.e., the area of ​​the first electrode 301 in the capacitor structure, and the fully transparent area 502 corresponds to the fully developed area, i.e., the area of ​​the gate scanning line 401; if a positive photoresist is applied, the semi-transparent area 501 corresponds to the incomplete development area, i.e., the area of ​​the first electrode 301 in the capacitor structure, and the fully shading area 503 corresponds to the fully developed area, i.e., the area of ​​the gate scanning line 401. In this manufacturing method, a positive photoresist is coated on the gate metal 4, and a half-color mask having a semi-transparent area 501, a fully transparent area 502, and a fully shielded area 503 is used to pattern the photoresist. The semi-transparent area 501 corresponds to an incompletely developed area, which corresponds to the area of ​​the first electrode 301 in the capacitor structure, and the fully shielded area 503 corresponds to a fully developed area, which corresponds to the area of ​​the gate scanning line 401 in the thin film field effect transistor. After the photoresist is developed, the photoresist in the incompletely developed area and the area outside the fully developed area is completely removed, and the photoresist in the incompletely developed area is thinner than the photoresist in the fully developed area. The structure is as follows: Figure 2 Then, the gate metal 4 and the first metal layer 3 on the incompletely developed area and the area outside the fully developed area are etched with photoresist and mask, and the structure is as shown in FIG. Figure 2 As shown in the third figure of FIG. 1 , the photoresist on the first metal layer 3 in the incompletely developed area is then removed by ashing treatment. The structure is as shown in FIG. Figure 2As shown in the fourth figure, the gate metal 4 in the incompletely developed area is removed by etching time control or the selectivity of the etching solution, the first layer of metal 3 in the incompletely developed area is retained and the first electrode 301 is formed in the hole 201, the gate metal 4 and the first layer of metal 3 in the fully developed area are retained and the gate scanning line 401 and the first metal 302 are formed on the buffer layer 2 outside the hole 201, and finally the metal is lifted off and the first metal 302 is removed and cleaned. The first electrode 301 and the first metal 302 are on the buffer layer 2, the first electrode 301 and the first metal 302 have a gap, and the gate scanning line 401 is on the first metal 302. Among them, the first electrode 301 serves as a plate 1 of the lower capacitor structure. When the first electrode 301 is formed in the hole 201, the useful first electrode 301 is generally retained. A portion of the first layer of metal 3 on the surface of the buffer layer 2 between the holes 201 and the holes 201 or on the surface of the buffer layer 2 around the holes 201 on both sides can also be retained as the first electrode 301. On the one hand, the first electrode 301 on the surface of the buffer layer 2 can be used as a connection point between the capacitor structure and other circuits, such as the parallel connection between the upper and lower capacitor structures. On the other hand, the first electrode 301 between the holes 201 and the holes 201 can connect the capacitor structures in the two holes 201, thereby further improving the capacitor capacity. The manufacturing method forms the first metal layer 3 and the gate metal 4 at one time and only retains the first metal layer 3 as an electrode in the capacitor region. Since the material of the first metal layer 3 is indium tin oxide, which is relatively thin (100 angstroms to 1000 angstroms), it is beneficial to increase the number of holes in the strip-shaped grid and further improve the capacitance. Secondly, using indium tin oxide as a bridge to connect the active layer with the source signal line 1001 and the drain 1002 can reduce the ohmic contact resistance and improve the electrical performance of the thin film field effect transistor. The manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

[0080] After the first electrode, the first metal and the gate scanning line are manufactured, the first electrode insulating layer 601, the gate insulating layer 602, the second electrode 701 and the second metal 702 are manufactured; see Figure 3 The specific process is to cover the array substrate 1 with a first insulating layer 6, and then continue to plate a second metal layer 7 on the first insulating layer 6. The second metal layer 7 can be made by electroplating, evaporation, or sputtering. The structure is as follows: Figure 3As shown in the first figure. The first insulating layer 6 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc., and the second metal layer 7 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. The photoresist is also patterned using a half-color mask 5 having a semi-transparent area 501, a fully transparent area 502, and a fully shading area 503. The light transmittance of the semi-transparent area 501 is 50%, the light transmittance of the fully transparent area 502 is 100%, and the light transmittance of the fully shading area 503 is 0%. After the photoresist is developed, the semi-transparent area 501 corresponds to an incompletely developed area, the fully transparent area 502 or the fully shading area 503 corresponds to a fully developed area, the incompletely developed area corresponds to the area of ​​the second electrode 701 in the capacitor structure, and the fully developed area corresponds to the area of ​​the second metal 702. Wherein, if negative photoresist is applied, the semi-transparent area 501 corresponds to the incompletely developed area, i.e., the area of ​​the second electrode 701 in the capacitor structure, and the fully transparent area 502 corresponds to the fully developed area, i.e., the area of ​​the second metal 702; if positive photoresist is applied, the semi-transparent area 501 corresponds to the incompletely developed area, i.e., the area of ​​the second electrode 701 in the capacitor structure, and the fully shielded area 503 corresponds to the fully developed area, i.e., the area of ​​the second metal 702. Please refer to Figure 3 In the second figure, a positive photoresist is coated on the second metal layer 7, and the photoresist is patterned using a half-color mask 5 having a semi-transparent area 501, a fully transparent area 502, and a fully shielded area 503. The semi-transparent area 501 corresponds to an incompletely developed area, which corresponds to the area of ​​the second electrode 701 in the capacitor structure, and the fully shielded area 503 corresponds to a fully developed area, which corresponds to the area of ​​the second metal of the thin film field effect transistor. After the photoresist is developed, the photoresist in the incompletely developed area and the area outside the fully developed area is completely removed, and the photoresist in the incompletely developed area is thinner than that in the fully developed area. The structure is as shown in FIG. Figure 3 Then, the second metal layer 6 in the area outside the incompletely developed area and the fully developed area is etched with a photoresist and a mask, and the first insulating layer 6 is retained. The structure is as shown in FIG. Figure 3 Then, the photoresist on the second metal layer 7 in the incompletely developed area is removed by ashing, and the metal oxide of the capacitor structure is made conductive by hydrogen ion implantation, and the ohmic contact characteristics of the oxide of the thin film field effect transistor with the source signal line 1001 and the drain 1002 are improved to reduce the contact resistance. The structure is as shown in FIG. Figure 3As shown in the fifth figure. After hydrogen ion implantation, the first insulating layer 6 of the incompletely developed area is retained, and a first electrode insulating layer 601 covering the first electrode 301 is formed on the surface of the buffer layer 2 in the hole 201 and between the holes 201 and 201, the second layer of metal 7 of the incompletely developed area is retained, and a second electrode 701 is formed in the hole 201, the first insulating layer 6 and the second layer of metal 7 of the fully developed area are retained, and a gate insulating layer 602 and a second metal 702 are formed on the buffer layer 2 outside the hole 201, and finally the metal is lifted off and the glue is removed and cleaned. When forming the second electrode 701 in the hole 201, the useful second electrode 701 is generally retained, and a part of the second layer of metal 7 on the surface of the buffer layer 2 between the holes 201 and the holes 201 or on the surface of the buffer layer 2 around the holes 201 on both sides is also retained as the second electrode 701, and the second electrode 701 between the holes 201 and the holes 201 can connect the capacitor structures in the two holes 201. The present manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

[0081] The first electrode insulating layer 601 covering the first electrode 301 serves as a dielectric layer of the lower capacitor structure. The first electrode insulating layer 601 realizes isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, thereby avoiding electrical connection between the first electrode 301 and the second electrode 701. The second electrode 701 is on the first electrode insulating layer 601, and the second electrode 601 serves as a common electrode plate of the upper and lower capacitor structures; the gate insulating layer 602 covers and wraps the gate scanning line 401 and the first metal 302. The second metal 702 is on the gate insulating layer 602 and serves as an active layer of the thin film field effect transistor.

[0082] Then, a second electrode insulating layer 801 and a barrier layer 802 are formed; see Figure 4The specific process is to cover the array substrate 1 with a second insulating layer 8. The second insulating layer 8 is made of the same material as the first insulating layer 6, such as silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc. Then, the second insulating layer 8 is patterned by photolithography, and the second insulating layer 8 is etched with a photoresist as a mask to expose the two sides of the second metal 702 and the two sides of the gate insulating layer, and a blocking layer 802 is formed on the second metal 702. The second insulating layer 8 on the surface of the buffer layer 2 outside the hole 201 is etched with a photoresist as a mask to form a through hole to the first electrode 301, and the bottom of the through hole is the first electrode 301. A second electrode insulating layer 801 covering the second electrode 701 is formed on the second electrode 701 on the surface of the buffer layer 2 inside the hole 201 and between the holes 201 and 201. The second electrode insulating layer 801 serves as a dielectric layer of the upper capacitor structure, and the second electrode insulating layer 801 realizes the isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding the electrical connection between the second electrode 701 and the third electrode 901. The first electrode 301 at the bottom of the through hole can be connected to the third electrode 901, thereby realizing the connection between the upper capacitor structure and the lower capacitor structure. After the second electrode insulating layer 801 and the barrier layer 802 are formed, the photoresist is removed. In some embodiments, the barrier layer 802 on the second metal 702 may not need to be formed, and a BCE structure thin film field effect transistor can be designed as needed, which can save a photomask. Figure 5 shown.

[0083] After the second electrode insulating layer 801 and the barrier layer 802 are fabricated, the third electrode 901, the third metal 903, the source signal line 1001 and the drain 1002 are fabricated; see Figure 6 , deposit the third metal layer 9, form the third metal 902 on the second metal 702 and the barrier layer 802, form the third electrode 9 in the hole 201, and retain a portion of the third metal layer 9 on the surface of the buffer layer 2 between the holes 201 and the holes 201 or on the surface of the buffer layer 2 around the holes 201 on both sides as the third electrode 901, and the third electrode 901 can be connected to the first electrode 301 through the through hole of the second electrode insulating layer 802 on the first electrode 301. After the third electrode 901 is connected to the first electrode 301, the upper capacitor structure and the lower capacitor structure are connected in parallel. This manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

[0084] The third metal 902 wraps the second metal 702 and both sides of the barrier layer 802 on the barrier layer 802. The third metal 902 exposes the central part of the barrier layer 802, that is, the third metal 902 has two parts. After the third metal 902 is made, the fourth metal layer 10 is deposited. The fourth metal layer 10 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. A source signal line 1001 is formed on one side of the third metal 902, and a drain 1002 is formed on the other side of the third metal 902. There is a gap between the source signal line 1001 and the drain 1002. The structure is as follows: Figure 6 After the third electrode 901, the source signal line 1001 and the drain 1002 are manufactured, the metal is lifted off and the resin is removed and cleaned.

[0085] In order to protect the capacitor structure and avoid direct contact between the external structure and the capacitor structure and the thin film field effect transistor, the present manufacturing method further performs the manufacturing of the passivation layer 1100; see Figure 7 , a passivation layer 1100 can be plated by chemical vapor deposition, and the passivation layer 1100 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, and the third electrode 901. After covering, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film field effect transistor are not contacted.

[0086] See also Figures 8 to 9 Compared with the original flat plate capacitor, the three-dimensional grid structure capacitor of the present invention can effectively reduce the area occupied by the capacitor area, and reduce the size of the capacitor while maintaining the same capacity; by retaining the metal oxide in the capacitor area of ​​the array substrate and making it conductive so that it can be used as a capacitor electrode, the ohmic contact characteristics are improved, the contact resistance is reduced, and two sets of parallel capacitors with excellent performance are formed, further increasing the capacitance. Please refer to Figure 8 According to the parallel capacitor formula, C parallel = C1 + C2, (C1 and C2 are upper and lower capacitor structures), in order to keep the capacitance equal, the actual area occupied by the grid capacitor can be further reduced by 50% compared with the theoretical area of ​​the flat plate capacitor; please refer to Fig. 9 , where the capacitance area of ​​the grid capacitor is S = (S1+S2+S3+S4)*n, and the occupied area is S 实 =(S1′+S2+S3+S4′)*n, according to the trigonometric function S1′=Sinα*S1, if S1′=S2=S3, Taperα=60°, while keeping the capacitance equal, the actual area occupied by the grid capacitor can be reduced by 33% compared to the flat capacitor area.

[0087] The first layer of metal and the gate metal are formed at one time and only indium tin oxide (the material of the first layer of metal) is retained as an electrode in the capacitor area. The indium tin oxide is thinner (100 angstroms to 1000 angstroms), which is conducive to increasing the number of holes in the strip-shaped grid and further improving the capacitance. Secondly, using indium tin oxide as a bridge to connect the active layer with the source and drain electrodes can reduce the ohmic contact resistance and improve the electrical performance of the thin film field effect transistor. The electrode area of ​​this production method can also directly use metal as an electrode plate, which can simplify the process.

[0088] The present invention provides an array substrate with a high capacitance structure, such as Figure 1 , Figures 4 to 9 As shown, the array substrate with a high capacitance structure of this embodiment can be manufactured according to the above method. The array substrate with a high capacitance structure includes: a buffer layer 2 is arranged on the array substrate 1, and the material of the buffer layer 2 is one or more of an organic photosensitive material, a polyimide film (PI), a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), and titanium oxide. A plurality of holes 201 are arranged on the buffer layer 2, and the structure is as follows Figure 1 The cross section of the hole 201 of the present invention can be rectangular, circular, or other irregular shapes. Figure 6 As shown, for example, the cross section of the hole 201 of the strip-shaped gate structure is rectangular, and the width of the cross section gradually decreases from top to bottom, the width of the hole bottom is smaller than the width of the hole mouth, and a gate-shaped capacitor structure is arranged in the hole 201 and between the holes 201. A thin film field effect transistor is arranged on the buffer layer 2 outside the hole 201.

[0089] See also Figure 4 , a first electrode 301, a first electrode insulating layer 601 and a second electrode 701 are sequentially arranged in the hole 201 and between the holes 201; the first electrode 301 serves as the electrode plate of the lower capacitor structure, the first electrode insulating layer 601 covers the first electrode 301 and serves as the dielectric layer of the lower capacitor structure, the second electrode is on the first electrode insulating layer and serves as the common electrode plate of the upper and lower capacitor structures; the second electrode insulating layer covers the second electrode and serves as the dielectric layer of the upper capacitor structure, the first electrode insulating layer 601 realizes the isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, thereby avoiding electrical connection between the first electrode 301 and the second electrode 701. The first electrode 301, the first electrode insulating layer 601 and the second electrode 701 constitute the lower capacitor structure. Since the first electrode 301 and the second electrode 701 on both sides of the inner wall of the hole are grid-like planes, the metal area can be greatly increased, thereby achieving a larger capacitance value. At the same time, the influence of parasitic capacitance and the required semiconductor device area are reduced. Please refer to Fig. 9 , where the capacitance area of ​​the grid capacitor is S = (S1+S2+S3+S4)*n, and the occupied area is S 实=(S1′+S2+S3+S4′)*n, according to the trigonometric function S1′=Sinα*S1, if S1′=S2=S3, Taperα=60°, while keeping the capacitance equal, the actual occupied area of ​​the grid capacitor can be reduced by 33% compared with the traditional flat capacitor.

[0090] The first electrode 301 is indium tin oxide, which is relatively thin (100 angstroms to 1000 angstroms), which is conducive to increasing the number of first electrodes 301 and further improving the capacitance; secondly, using indium tin oxide as a bridge to connect the active layer with the source signal line 1001 and the drain 1002 can reduce the ohmic contact resistance and improve the electrical performance of the thin film field effect transistor. The first electrode insulating layer 601 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc.

[0091] See also Figure 6 , a second electrode insulating layer 801 and a third electrode 901 are sequentially arranged in the hole 201 and between the holes 201 and the holes 201; the second electrode insulating layer 801 covers the second electrode 701 and serves as a dielectric layer of the upper capacitor structure, the third electrode 901 is on the second electrode insulating layer 801 and serves as a plate of the upper capacitor structure, and the first electrode insulating layer 601, the second electrode insulating layer 801 and the second electrode 701 on the surface of the buffer layer 2 expose the first electrode 301 underneath. The second electrode insulating layer 801 realizes the isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding the electrical connection between the second electrode 701 and the third electrode 901. The second electrode 701, the second electrode insulating layer 801 and the third electrode 901 constitute the lower capacitor structure. Since the second electrode 701 and the third electrode 901 on both sides of the inner wall of the hole are grid-shaped planes, the area of ​​the metal can be greatly increased, thereby achieving a larger capacitance value. The first electrode 301 and the third electrode 901 on the buffer layer 2 are connected to realize the parallel connection of the upper and lower layer capacitor structures. Figure 8 According to the parallel capacitance formula, C parallel = C1 + C2, (C1 and C2 are upper and lower capacitor structures), in order to keep the capacitance equal, the actual area occupied by the grid capacitor can be further reduced by 50% compared with the theoretical area of ​​the flat plate capacitor.

[0092] See also Figure 6 A thin film field effect semiconductor is arranged on the buffer layer 2 outside the hole 201, and the thin film field effect semiconductor includes: a first metal 302 is arranged on the buffer layer 2 outside the hole 201, and the first metal 302 is indium tin oxide; a gate scanning line 401 is arranged on the first metal 302, and the gate scanning line 401 is one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, or other alloys.

[0093] A gate insulating layer 602 is provided on the gate scanning line 401, and the gate insulating layer 602 covers and wraps the gate scanning line 401 and the first metal 302. The gate insulating layer 602 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc.

[0094] A second metal 702 is disposed on the gate insulating layer 602. The second metal 702 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc.; a barrier layer 802 is disposed on the second metal 702. The second metal 702 is on the gate insulating layer 602 and serves as an active layer of the thin film field effect transistor. In some embodiments, the barrier layer may not be disposed. The structure is as follows: Figure 5 shown.

[0095] A third metal 902 is arranged on the barrier layer 802. The third metal 902 is a metal oxide such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. The third metal 903 wraps the second metal 702 and both sides of the barrier layer 802. The third metal 902 exposes the central part of the barrier layer 802. A source signal line 1001 is arranged on one side of the third metal 902, and a drain 1002 is arranged on the other side of the third metal 903. The source signal line 1001 and the drain 1002 are metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. There is a gap between the source signal line 1001 and the drain 1002. The structure is as follows: Figure 6 shown.

[0096] In order to protect the capacitor structure and avoid direct contact between the external structure and the capacitor structure and the thin film field effect transistor, a passivation layer 1100 is provided on the capacitor region and the thin film field effect transistor. The passivation layer 1100 is made of materials such as silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, and the third electrode 901. After covering, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film field effect transistor are not contacted.

[0097] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate having a high capacitance structure, characterized in that: The steps include: Fabricating a buffer layer on the array substrate; making holes in the buffer layer; Depositing a first layer of metal to form a first electrode in the hole, the first electrode serving as a plate of a lower capacitor structure; After covering the first insulating layer, continue to deposit a second layer of metal to form a first electrode insulating layer covering the first electrode in the hole, and form a second electrode on the first electrode insulating layer in the hole, the second electrode serving as a common electrode plate of the upper and lower layer capacitor structures; Covering the second insulating layer, forming a second electrode insulating layer covering the second electrode in the hole; Depositing a third layer of metal to form a third electrode on the second insulating layer in the hole, the third electrode serving as a plate of the upper capacitor structure; A thin film field effect transistor is also arranged on the buffer layer outside the hole.

2. The method for manufacturing an array substrate with a high capacitance structure according to claim 1, characterized in that: The following steps are also included: When depositing the first metal layer, the first electrode in the hole is extended to the surface of the buffer layer; or: after covering the first insulating layer, when continuing to deposit the second metal layer, the second electrode in the hole and the first electrode insulating layer are extended to the surface of the buffer layer outside the hole; Or: when covering the second insulating layer, the second electrode insulating layer in the hole is extended to the surface of the buffer layer outside the hole; or: when depositing the third layer of metal, the third electrode in the hole is extended to the surface of the buffer layer outside the hole; Or: connecting the third electrode on the surface of the buffer layer outside the hole and the first electrode on the surface of the buffer layer outside the hole.

3. The method for manufacturing an array substrate with a high capacitance structure according to claim 2, characterized in that: The manufacturing steps of the thin film field effect transistor are as follows: After depositing the first layer of metal, continue to deposit the gate metal, and form the first metal and the gate scanning line on the buffer layer outside the hole, the first metal is on the buffer layer outside the hole, and the gate scanning line is on the first metal; After covering the first insulating layer, continue to deposit a second metal layer to form a gate insulating layer on the gate scanning line, the gate insulating layer covers and wraps the gate scanning line and the first metal, and forms the second metal on the gate insulating layer; forming a barrier layer on the second metal while covering the second insulating layer; When depositing the third metal layer, a third metal is formed on the barrier layer to wrap around the second metal and both sides of the barrier layer, and the third metal is exposed from the central part of the barrier layer; A fourth layer of metal is deposited to form a source signal line on one side of the third metal and a drain on the other side of the third metal.

4. The method for manufacturing an array substrate with a high capacitance structure according to claim 3, characterized in that: After depositing the first metal layer, the gate metal is deposited, and the following steps are also included: A photoresist is coated on the gate metal, and the photoresist is patterned using a half-color mask having a semi-transparent area, a fully transparent area, and a fully shading area. After the photoresist is developed, the semi-transparent area corresponds to an incompletely developed area, the fully transparent area or the fully shading area corresponds to a fully developed area, the incompletely developed area corresponds to an area of ​​the first electrode in the capacitor structure, and the fully developed area corresponds to an area of ​​the gate scanning line; Using the photoresist as a mask, etching the gate metal and the first metal layer on the area outside the complete development area and the incomplete development area; The photoresist on the first metal layer in the incompletely developed area is removed by ashing, and the photoresist on the gate metal in the fully developed area is retained; The gate metal in the incompletely developed area is etched to the first metal layer, the first metal layer is retained as the first electrode, and the photoresist on the completely developed area is removed to form the first metal and the gate scanning line.

5. The method for manufacturing an array substrate with a high capacitance structure according to claim 3, characterized in that: After covering the first insulating layer, when continuing to deposit the second metal layer, the following steps are also included: Coating a photoresist on the second metal layer, and patterning the photoresist using a half-color mask having a semi-transparent area, a fully transparent area, and a fully shading area, wherein after developing the photoresist, the semi-transparent area corresponds to an incompletely developed area, and the fully transparent area or the fully shading area corresponds to a fully developed area, wherein the incompletely developed area corresponds to an area of ​​the second electrode in the capacitor structure, and the fully developed area corresponds to an area of ​​the second metal; The second layer of metal on the area outside the incomplete development area and the complete development area is etched, the photoresist on the second layer of metal in the incomplete development area is removed by ashing treatment, and then hydrogen ions are implanted to remove the photoresist on the first insulating layer material in the complete development area, and the second layer of metal and the first insulating layer in the incomplete development area are retained as the second electrode and the first electrode insulating layer, respectively, and the second layer of metal and the first insulating layer in the complete development area are retained as the second metal and the gate insulating layer, respectively.

6. The method for manufacturing an array substrate with a high capacitance structure according to claim 1, 2 or 3, characterized in that: Also includes the following steps: A third insulating layer material is covered, and a passivation layer is formed on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, wherein the passivation layer protects the capacitor structure and the thin film field effect transistor.

7. The method for manufacturing an array substrate with a high capacitance structure according to claim 1, 2 or 3, characterized in that: The material of the first metal layer is indium tin oxide.

8. An array substrate with a high capacitance structure, characterized in that: The array substrate with a high capacitance structure is manufactured by the manufacturing method according to any one of claims 1 to 7.

9. An array substrate with a high capacitance structure, characterized in that: include: A buffer layer is arranged on the array substrate, a hole is arranged on the buffer layer, and a thin film field effect transistor is arranged on the buffer layer outside the hole; A first electrode, a first electrode insulating layer, a second electrode, a second electrode insulating layer and a third electrode are sequentially arranged on the surface of the buffer layer in the hole and between the holes. The first electrode serves as a plate of a lower capacitor structure, the first electrode insulating layer covers the first electrode and serves as a dielectric layer of the lower capacitor structure, the second electrode is on the first electrode insulating layer and serves as a common plate of the upper and lower capacitor structures, the second electrode insulating layer covers the second electrode and serves as a dielectric layer of an upper capacitor structure, and the third electrode is on the second electrode insulating layer and serves as a plate of the upper capacitor structure.

10. The array substrate with a high capacitance structure according to claim 9, characterized in that: The thin film field effect transistor comprises: A first metal is arranged on the buffer layer outside the hole, and a gate scanning line is arranged on the first metal; A gate insulating layer is arranged on the gate scanning line, and the gate insulating layer covers and wraps the gate scanning line and the first metal; A second metal is disposed on the gate insulating layer, and a barrier layer is disposed on the second metal; A third metal is arranged on the barrier layer, the third metal wraps around the second metal and both sides of the barrier layer, the third metal exposes the central part of the barrier layer, a source signal line is arranged on one side of the third metal, and a drain is arranged on the other side of the third metal.

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