Slit structure and preparation method thereof, semiconductor storage device and preparation method thereof

Abstract

The present invention provides a slit structure and a preparation method thereof as well as a semiconductor memory device and a preparation method thereof. The slit structure preparation method of the present invention covers the sidewall and bottom of a first groove by a spacer layer, forms a second groove whose groove width is smaller than the first groove width in the first groove, and modifies the spacer layer covering the sidewall and bottom of the first groove and the photoresist layer so that different regions of the spacer layer have different molecular structures. The spacer layer is etched by utilizing the difference in etching rates of materials with different molecular structures, and finally a complete slit structure is obtained. The present invention can form a slit structure with an aspect ratio between 1:500 and 500:1, can form a micro-pore structure or micro-groove below the limiting resolution, and can control the size of the slit structure according to the type and concentration of the injected ions. Therefore, the device size can be reduced while ensuring the performance of the semiconductor device, which is conducive to the integration of the device.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and in particular to a semiconductor device slit structure and a preparation method thereof, and a semiconductor storage device and a preparation method thereof. Background Art

[0002] With the continuous development of integrated circuit technology, the size of integrated circuits is getting smaller and smaller. The method of forming a pattern on an integrated circuit substrate is generally to first, Figure 1-2 As shown, the pattern is transferred from the mask 104 to the photoresist 103 via a photolithography process; secondly, as shown Figure 3-4 As shown, the pattern is then transferred to the substrate 101 of the integrated circuit through the photoresist 103 with the pattern through an etching process, specifically, to the semiconductor layer 102 of the substrate 101. In the integrated circuit pattern manufacturing process, the formation of the slit is obviously much more difficult than forming other patterns such as fine lines on the wafer, because for conventional photolithography processes, such as Figure 5 As shown in FIG. 1 , if a mask 504 with a slit pattern of a smaller size is used, the diffraction angle of the photolithography beam will become larger after passing through the mask, resulting in the photolithography beam being unable to be focused on the photoresist 503 and thus unable to be focused on the substrate 501, and thus unable to form a semiconductor layer 502 on the substrate 501. Figure 6 The photolithography pattern shown.

[0003] At present, the commonly used technology for micro-sized graphics (such as slits) is RELACS (resolution enhancement lithography assisted by chemical shrink) technology, which first uses a water-soluble chemical shrinking agent RELACS to be coated on the exposed lithographic pattern, and then through mixed baking, the photoacid molecules in the photoresist are heated to diffuse and enter the RELACS reagent, catalyzing the RELACS reagent, so that the polymer in the RELACS reagent and the cross-linked molecules produce a cross-linking reaction, so that a new layer of water-insoluble cross-linking layer is formed on the surface of the photoresist to achieve the purpose of shrinking the groove width. However, the disadvantage of this method is that the shrinkage width is fixed, and the width of the groove can only be shrunk by about 20-30nm, and the free control of the slit size cannot be achieved.

[0004] Another commonly used technology is to form a spacer layer on the groove and photoresist after photolithography, so that the groove becomes smaller to form a slit, and then form a slit pattern through etching. Figure 7 As shown, a groove 705 is formed on the photoresist layer 703; then, as shown Figure 8As shown, a spacer layer 704 is formed on the photoresist layer 703 and in the groove 705, so that the groove becomes smaller to form a slit 706; then the spacer layer 704 is dry-etched. Since the etching rate of the spacer layer outside the slit is faster than that of the spacer layer inside the slit, as shown in FIG. Fig. 9 As shown in FIG. 1 , the slit pattern has not yet been formed on the hard mask 702 on the substrate 701, but the spacer layer outside the slit has been completely etched away. Therefore, the disadvantage of this method is that the etching rates inside the slit are different from those outside the slit, which results in the slit pattern not yet being formed on the hard mask, but the spacer layer and photoresist outside the slit have been completely consumed, and the slit cannot be effectively formed on the hard mask, and further, the required slit structure cannot be formed on the substrate or substrate. Summary of the invention

[0005] In view of this, the present invention provides a semiconductor device slit structure and a preparation method thereof, as well as a semiconductor memory device and a preparation method thereof, to solve the problem in the prior art that an effective slit cannot be formed and the slit size cannot be controlled.

[0006] According to the first aspect of the present application, an embodiment of the present invention provides a method for preparing a slit structure in a semiconductor device, comprising at least the following steps:

[0007] providing a substrate;

[0008] coating a photoresist layer on the substrate;

[0009] forming a first groove in the photoresist layer;

[0010] Depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0011] Modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0012] The modified spacer layer is etched to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove.

[0013] Optionally, modifying the spacer layer includes doping different ions in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer and a portion of the spacer layer covering the bottom of the first trench.

[0014] Optionally, the process of modifying the spacer layer includes implanting ions into the spacer layer, and controlling the spacer layer portion covering the sidewall of the first trench and the photoresist layer and the spacer layer portion covering the bottom of the first trench to have different ion concentrations.

[0015] Optionally, modifying the spacer layer includes doping ions into a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer.

[0016] Optionally, the spacer layer is modified by ion implantation, and the ion implantation angle is greater than 0° and less than arc tan A / B, where A is the depth of the second groove, and B is the width of the second groove.

[0017] Optionally, the depth of the ion implantation is between 2 nm and 1000 nm, and the intensity is between 2 KeV and 900 KeV.

[0018] Optionally, the implanted ions are boron ions or phosphorus ions.

[0019] Optionally, the spacer layer is silicon oxide or silicon nitride.

[0020] Optionally, the step of etching the modified spacer layer to form a slit structure on the substrate includes:

[0021] dry etching the modified spacer layer;

[0022] The substrate is etched to form a slit structure.

[0023] Optionally, after etching the substrate to form a slit structure, the method further comprises the following steps:

[0024] removing the spacer layer covering the photoresist layer and the sidewall and bottom of the first trench;

[0025] The photoresist layer is removed.

[0026] Optionally, before coating the photoresist layer on the substrate, the method further includes forming a semiconductor layer on the substrate.

[0027] Optionally, etching the modified spacer layer to form a slit structure on the substrate further comprises etching the semiconductor layer.

[0028] Optionally, before coating the photoresist layer on the substrate, a step of forming a hard mask on the substrate is further included, and the hard mask includes one of SiN, SiO2, TaN and TiN or a combination thereof.

[0029] Optionally, the step of etching the modified spacer layer to form a slit structure on the substrate further includes:

[0030] etching the hard mask to form a third trench on the hard mask;

[0031] The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

[0032] According to a second aspect of the present invention, the present invention provides a slit structure, characterized in that the slit structure comprises:

[0033] A substrate is provided with a plurality of slit structures, wherein the aspect ratio of the slit structures is between 1:500 and 500:1.

[0034] Optionally, the width of the slit structure is between 2nm and 1000nm.

[0035] Optionally, the depth of the slit structure is between 2 nm and 1000 nm.

[0036] Optionally, the slit structure is formed by the following steps:

[0037] providing a substrate;

[0038] coating a photoresist layer on the substrate;

[0039] forming a first groove in the photoresist layer;

[0040] Depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0041] Modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0042] The modified spacer layer is etched to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove.

[0043] Optionally, modifying the spacer layer includes doping different ions in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer and a portion of the spacer layer covering the bottom of the first trench.

[0044] Optionally, modifying the spacer layer includes implanting ions into the spacer layer, and controlling the spacer layer portion covering the sidewall of the first trench and the photoresist layer and the spacer layer portion covering the bottom of the first trench to have different ion concentrations.

[0045] Optionally, modifying the spacer layer includes doping ions into a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer.

[0046] Optionally, the spacer layer is modified by ion implantation, and the ion implantation angle is greater than 0° and less than arc tan A / B, where A is the depth of the second groove, and B is the width of the second groove.

[0047] Optionally, the depth of the ion implantation is between 2 nm and 1000 nm, and the intensity is between 2 KeV and 900 KeV.

[0048] Optionally, the implanted ions are boron ions or phosphorus ions.

[0049] Optionally, the spacer layer is silicon oxide or silicon nitride.

[0050] Optionally, the step of etching the modified spacer layer to form a slit structure on the substrate includes:

[0051] dry etching the modified spacer layer;

[0052] The substrate is etched to form a slit structure.

[0053] Optionally, after etching the substrate to form a slit structure, the method further comprises the following steps:

[0054] removing the spacer layer covering the photoresist layer and the sidewall and bottom of the first trench;

[0055] The photoresist layer is removed.

[0056] Optionally, the slit structure further includes a semiconductor layer formed on the substrate, and the slit structure is formed in the substrate and the semiconductor layer.

[0057] According to a third aspect of the present invention, the present invention provides a method for preparing a semiconductor memory device, the method comprising the following steps:

[0058] Providing a semiconductor substrate;

[0059] coating a photoresist layer on the substrate;

[0060] forming a first groove in the photoresist layer;

[0061] Depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0062] Modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0063] Etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove;

[0064] A gate assembly is formed in the slit.

[0065] Optionally, modifying the spacer layer includes doping different ions in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer and a portion of the spacer layer covering the bottom of the first trench.

[0066] Optionally, modifying the spacer layer includes implanting ions into the spacer layer, and controlling the spacer layer portion covering the sidewall of the first trench and the photoresist layer and the spacer layer portion covering the bottom of the first trench to have different ion concentrations.

[0067] Optionally, modifying the spacer layer includes doping ions into a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer.

[0068] Optionally, the spacer layer is modified by ion implantation, and the ion implantation angle is greater than 0° and less than arc tan A / B, where A is the depth of the second groove, and B is the width of the second groove.

[0069] Optionally, the depth of the ion implantation is between 2 nm and 1000 nm, and the intensity is between 2 KeV and 900 KeV.

[0070] Optionally, the implanted ions are boron ions or phosphorus ions.

[0071] Optionally, the spacer layer is silicon oxide or silicon nitride.

[0072] Optionally, the step of etching the modified spacer layer to form a slit structure on the substrate includes:

[0073] dry etching the modified spacer layer;

[0074] The substrate is etched to form a slit structure.

[0075] Optionally, after etching the substrate to form a slit structure, the method further comprises the following steps:

[0076] removing the spacer layer covering the photoresist layer and the sidewall and bottom of the first trench;

[0077] The photoresist layer is removed.

[0078] Optionally, before coating the photoresist layer on the substrate, the method further includes forming a semiconductor layer on the substrate.

[0079] Optionally, etching the modified spacer layer to form a slit structure on the substrate further comprises etching the semiconductor layer.

[0080] Optionally, before coating the photoresist layer on the substrate, a step of forming a hard mask on the substrate is further included, and the hard mask includes one of SiN, SiO2, TaN and TiN or a combination thereof.

[0081] Optionally, the step of etching the modified spacer layer to form a slit structure on the substrate further includes:

[0082] etching the hard mask to form a third trench on the hard mask;

[0083] The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

[0084] According to a fourth aspect of the present invention, the present invention provides a semiconductor memory device, the semiconductor memory device comprising:

[0085] A semiconductor substrate having at least one groove therein, the opening of the groove facing the surface of the semiconductor substrate; and at least one gate component, the gate component being buried in the groove;

[0086] Wherein, the groove is a slit structure, and the aspect ratio of the slit structure is between 1:500 and 500:1.

[0087] Optionally, the width of the slit structure is between 2 nm and 1000 nm.

[0088] Optionally, the depth of the slit structure is between 2 nm and 1000 nm.

[0089] Optionally, the substrate surface includes source regions respectively located outside the gate components and drain regions located between the gate components.

[0090] Optionally, the gate component includes a gate dielectric layer and a gate electrode.

[0091] Optionally, the slit structure is prepared by the method provided by the first aspect of the present invention.

[0092] As described above, the method for preparing the slit structure of the present invention has the following technical effects:

[0093] The preparation method of the slit structure of the present invention is to cover the sidewall and bottom of the first groove by a spacer layer, and form a second groove with a groove width smaller than the first groove in the first groove. By modifying the spacer layer covering the sidewall and bottom of the first groove and covering the photoresist layer, different regions of the spacer layer have different molecular structures. By utilizing the difference in etching rates of materials with different molecular structures, when etching the spacer layer, the etching rate in the second groove is faster than the etching rate outside the second groove, and finally a complete slit structure is obtained, and the size of the slit structure can be controlled according to the type and concentration of the injected ions. The method of the present invention can form a micro-pore structure or micro-groove below the limiting resolution. The slit structure of the present invention, because it has a significantly reduced size relative to the prior art, is helpful to reduce the size of related semiconductor devices, such as semiconductor storage devices, and can ensure the good functionality of the semiconductor device. The semiconductor storage device of the present invention and the preparation method thereof can reduce the device size while ensuring the performance of the semiconductor device, which is conducive to the integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 The diagram shows a schematic diagram of transferring a pattern from a mask to a photoresist through a photolithography process in the prior art.

[0095] Figure 2 FIG. 4 is a schematic cross-sectional view of a photoresist pattern formed in the prior art.

[0096] Figure 3 The figure shows a cross-sectional schematic diagram of transferring a photoresist pattern onto a substrate of an integrated circuit through an etching process in the prior art.

[0097] Figure 4 A schematic cross-sectional view of a substrate of an integrated circuit with a pattern formed in the prior art is shown.

[0098] Figure 5 The diagram shows a photolithography process performed through a mask having a slit pattern of a relatively small size when forming a slit structure in the prior art.

[0099] Figure 6 Display as Figure 5 Schematic diagram of a target slit pattern that cannot be formed by the photolithography process shown.

[0100] Figure 7-9 FIG. 4 is a schematic cross-sectional view of another method for forming a slit structure in a semiconductor in the prior art.

[0101] Fig.10 It also shows a flow chart of the method for forming the slit structure in the first embodiment, the second embodiment and the fourth embodiment of the present invention.

[0102] Fig.11The display is the execution of the first embodiment, the second embodiment and the fourth embodiment. Fig.10 The cross-sectional diagram presented during steps S200 - S300 is shown.

[0103] Fig.12 The display is the execution of the first embodiment, the second embodiment and the fourth embodiment. Fig.10 The cross-sectional diagram presented during steps S400 - S500 is shown.

[0104] Fig.13 It is a schematic diagram showing the angle of ion implantation when the spacer layer is modified by ion implantation in the first, second and fourth embodiments.

[0105] Fig.14 It also shows the cross-sectional structure schematic diagram of the slit structure in the first embodiment, the second embodiment, the third embodiment and the fourth embodiment.

[0106] Fig.15 Shown is a flow chart of a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention.

[0107] Reference numerals

[0108] 101 Substrate

[0109] 102 Semiconductor layer

[0110] 103 Photoresist

[0111] 104 Mask

[0112] 501 substrate

[0113] 502 Semiconductor layer

[0114] 503 Photoresist

[0115] 504 Photomask

[0116] 701 substrate

[0117] 702 Semiconductor layer

[0118] 703 Photoresist

[0119] 704 Spacer

[0120] 705 Groove

[0121] 706 Slit

[0122] 1101 Substrate

[0123] 1102 Semiconductor layer

[0124] 1103 Photoresist layer

[0125] 1104 The spacer layer portion covering the bottom of the first trench 1107

[0126] 1105 covers the sidewall of the first trench 1107 and the spacer layer portion of the photoresist layer 1103

[0127] 1106 Second Groove

[0128] 1107 First Groove

[0129] 1403 Slit Structure DETAILED DESCRIPTION

[0130] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0131] Embodiment 1

[0132] This embodiment provides a method for preparing a slit structure of a semiconductor device, such as Fig.10 As shown, the method comprises at least the following steps:

[0133] S100, providing a substrate;

[0134] S200, coating a photoresist layer on the substrate;

[0135] S300, forming a first groove in the photoresist layer;

[0136] S400, depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0137] S500, modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0138] S600, etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove.

[0139] Combined with Fig.11As shown, first, in step S100, a substrate 1101 is provided, and the substrate 1101 can be a substrate material commonly used in the art, such as bulk silicon, silicon on an insulating layer, etc. Then, in step S200, a photoresist layer 1103 is coated on the substrate 1101, for example, by using a spin coating method to coat the photoresist layer 1103; finally, in step S300, for example, a first groove 1107 is formed on the photoresist layer 1103 by using a photolithography process commonly used in the art, such as alignment, exposure, and development.

[0140] Subsequently, combined with Fig.12 As shown, after forming the first trench 1107, a spacer layer is deposited in step S400, the spacer layer covers the photoresist layer 1103 having the first trench 1107 pattern and the sidewall and bottom of the first trench 1107, and the spacer layer forms a second trench 1106, the width of the second trench 1106 is smaller than the width of the first trench 107, for example, the width of the second trench 1106 can be reduced by 20nm to 60nm relative to the width of the first trench 1107, and the reduced width of the second trench 1106 can be adjusted according to process requirements. The deposited spacer layer can be a material suitable for dry etching, such as silicon oxide or silicon nitride.

[0141] Continue to refer to the attached Fig.13 , in step S500, the deposited spacer layer is modified so that different regions of the spacer layer have different etching rates. Modifying the spacer layer may include: doping different ions in the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107, or injecting the same ions into the spacer layer, but controlling the ion concentration of the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107 to be different. Through any of the above modification methods, different etching rates can be obtained in the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107. Specifically, the etching rate of the spacer layer portion 1104 covering the bottom of the first trench 1107 is greater than the etching rate of the spacer layer portion 1105 covering the sidewall of the first trench 1107 and the photoresist layer 1103 .

[0142] In a further embodiment of this embodiment, ions are doped only on the sidewalls of the first trench 1107 and the spacer layer portion 1105 of the photoresist layer 1103 to modify the spacer layer. Fig.13In this further embodiment, the spacer layer portion 1105 is modified by ion implantation, and the angle θ of the ion implantation is greater than 0° and less than arc tanA / B, where A is the depth of the second groove 1106 and B is the width of the second groove 1106. The depth of the ion implantation is between 2nm and 1000nm, and the intensity is between 2KeV and 900KeV. The implanted ions can be ions such as boron ions or phosphorus ions that can change the etching rate of the spacer layer. According to the size requirements of the slit structure, the etching rate of the spacer layer inside and outside the slit can be controlled by controlling the energy, type and / or concentration of the ion implantation, and then the size of the slit structure can be controlled.

[0143] Finally, the modified spacer layer is etched, such as Fig.14 As shown, a slit structure 1403 is formed on the substrate 1101, and the width of the slit structure 1403 is smaller than the width of the first groove 1107. Specifically, the steps of forming the slit structure 1403 are as follows: dry etching the modified spacer layer; etching the substrate 1101 to form the slit structure 1403. Since the etching rate of the spacer layer portion 1104 covering the bottom of the first groove 1107 is greater than the etching rate of the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103, during the etching process, the spacer layer portion 1104 at the bottom of the first groove 1107 exposed below the second groove 1106 will be consumed first, and then as the etching proceeds, a groove pattern is formed on the substrate 1101 until the desired slit structure 1403 is formed, and then the etching is stopped. Forming the slit structure further includes: removing the spacer layer covering the photoresist layer 1103 and the sidewalls and bottom of the first groove 1107 ; and removing the photoresist layer 1103 .

[0144] According to another further embodiment of the present invention, before coating the photoresist layer 1103 on the substrate 1101, the method further includes forming a semiconductor layer 1102 (such as Fig.11 As shown). For example, the semiconductor layer 1102 may be a silicon oxide layer, and a thermal oxidation method is used to control the oxidation temperature between 900 and 1000° C. to grow a silicon oxide layer with a thickness of The semiconductor layer 1102 may also be a multi-layer structure, for example, it may include a silicon oxide layer grown by thermal oxidation and a silicon nitride layer formed by chemical vapor deposition or the like.

[0145] In this further embodiment, the step of etching the modified spacer layer to form a slit structure 1403 on the substrate 1101 further includes etching the semiconductor layer 1102 to form a slit structure 1403 on the semiconductor layer 1102 .

[0146] According to yet another further embodiment of the present invention, before coating the photoresist layer 1103 on the substrate 1101, the method further comprises forming a hard mask (not further shown) on the substrate 1101. For example, the hard mask may comprise one of SiN, SiO2, TaN and TiN or a combination thereof. For example, the hard mask may be formed on the substrate 1101 by chemical vapor deposition.

[0147] In this further embodiment, the step of etching the modified spacer layer to form the slit structure 1403 on the substrate 1101 further includes:

[0148] etching the hard mask to form a third trench on the hard mask;

[0149] The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

[0150] Embodiment 2

[0151] This embodiment provides a slit structure, the slit structure comprising:

[0152] Substrate,

[0153] The substrate is provided with a plurality of slit structures, and the aspect ratio of the slit structures is between 1:500 and 500:1.

[0154] In a further embodiment of this embodiment, the width of the slit structure is between 2 nm and 1000 nm, and the depth of the slit structure is between 2 nm and 1000 nm.

[0155] Still refer to the attached Figure 10-14 In another further embodiment of this embodiment, the slit structure is attached Fig.10 The steps shown form:

[0156] S100, providing a substrate;

[0157] S200, coating a photoresist layer on the substrate;

[0158] S300, forming a first groove in the photoresist layer;

[0159] S400, depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0160] S500, modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0161] S600, etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove.

[0162] Combined with Fig.11 As shown, first, in step S100, a substrate 1101 is provided, and the substrate 1101 can be a substrate material commonly used in the art, such as bulk silicon, silicon on an insulating layer, etc. Then, in step S200, a photoresist layer 1103 is coated on the substrate 1101, for example, by using a spin coating method to coat the photoresist layer 1103; finally, for example, a first groove 1107 is formed on the photoresist layer 1103 by a photolithography process commonly used in the art, such as alignment, exposure, and development.

[0163] Subsequently, combined with Fig.12 As shown, after forming the first trench 1107, a spacer layer is deposited, the spacer layer covers the photoresist layer 1103 having the first trench 1107 pattern and the sidewall and bottom of the first trench 1107, and the spacer layer forms a second trench 1106, the width of the second trench 1106 is smaller than the width of the first trench 1107, for example, the width of the second trench 1106 can be reduced by nearly 400 nm relative to the width of the first trench 1107. The deposited spacer layer can be various materials suitable for dry etching, such as silicon oxide or silicon nitride.

[0164] Continue to refer to the attached Fig.12 , modifying the deposited spacer layer so that different regions of the spacer layer have different etching rates. Modifying the spacer layer may include: doping different ions in the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107, or injecting the same ions into the spacer layer, but controlling the ion concentration of the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107 to be different. Through any of the above modification methods, the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103 and the spacer layer portion 1104 covering the bottom of the first groove 1107 have different etching rates. Specifically, the etching rate of the spacer layer portion 1104 covering the bottom of the first trench 1107 is greater than the etching rate of the spacer layer portion 1105 covering the sidewall of the first trench 1107 and the photoresist layer 1103 .

[0165] In a further embodiment of this embodiment, ions are doped only on the sidewalls of the first trench 1107 and the spacer layer portion 1105 of the photoresist layer 1103 to modify the spacer layer. Fig.13In this further embodiment, the spacer layer portion 1105 is modified by ion implantation, and the angle θ of the ion implantation is greater than 0° and less than arc tanA / B, where A is the depth of the second groove 1106, and B is the width of the second groove 1106. The depth of the ion implantation is between 2nm and 1000nm, and the intensity is between 2KeV and 900KeV. The implanted ions can be ions such as boron ions or phosphorus ions that can change the etching rate of the spacer layer. According to the size requirements of the slit structure, the etching rate of the spacer layer inside and outside the second groove can be controlled by controlling the energy, type and / or concentration of the ion implantation, and then the size of the slit structure can be controlled.

[0166] Finally, the modified spacer layer is etched, such as Fig.14 As shown, a slit structure 1403 is formed on the substrate 1101, and the width of the slit structure 1403 is smaller than the width of the first groove 1107. The steps of forming the slit structure 1403 are as follows: dry etching the modified spacer layer; etching the substrate 1101 to form the slit structure 1403. Since the etching rate of the spacer layer portion 1104 covering the bottom of the first groove 1107 is greater than the etching rate of the spacer layer portion 1105 covering the sidewall of the first groove 1107 and the photoresist layer 1103, during the etching process, the spacer layer portion 1104 at the bottom of the first groove 1107 exposed below the second groove 1106 will be consumed first, and then as the etching proceeds, a groove pattern is formed on the substrate 1101 until the desired slit structure 1403 is formed, and then the etching is stopped. Forming the slit structure also includes: removing the spacer layer covering the photoresist layer 1103 and the sidewall and bottom of the first groove; removing the photoresist layer 1103.

[0167] According to another further embodiment of the present invention, before coating the photoresist layer 1103 on the substrate 1101, the method further includes forming a semiconductor layer 1102 (such as Fig.11 As shown). For example, the semiconductor layer 1102 may be a silicon oxide layer, and a thermal oxidation method is used to control the oxidation temperature between 900 and 1000° C. to grow a silicon oxide layer with a thickness of The semiconductor layer 1102 may also be a multi-layer structure, for example, it may include a silicon oxide layer grown by thermal oxidation and a silicon nitride layer formed by chemical vapor deposition or the like.

[0168] In this further embodiment, the step of etching the modified spacer layer to form a slit structure 1403 on the substrate 1101 further includes etching the semiconductor layer 1102 to form a slit structure 1403 on the semiconductor layer 1102 .

[0169] According to yet another further embodiment of the present invention, before coating the photoresist layer 1103 on the substrate 1101, the method further comprises forming a hard mask (not further shown) on the substrate 1101. For example, the hard mask may comprise one of SiN, SiO2, TaN and TiN or a combination thereof. For example, the hard mask may be formed on the substrate 1101 by chemical vapor deposition.

[0170] In this further embodiment, the step of etching the modified spacer layer to form the slit structure 1403 on the substrate 1101 further includes:

[0171] etching the hard mask to form a third trench on the hard mask;

[0172] The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

[0173] Embodiment 3

[0174] This embodiment provides a method for preparing a semiconductor memory device, such as Fig.15 As shown, the method comprises the following steps:

[0175] S100, providing a substrate;

[0176] S200, coating a photoresist layer on the substrate;

[0177] S300, forming a first groove in the photoresist layer;

[0178] S400, depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench;

[0179] S500, modifying the spacer layer so that different regions of the spacer layer have different etching rates;

[0180] S600, etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove;

[0181] S700, forming a gate component in the slit structure.

[0182] The steps of forming the slit structure in steps S100 - S600 are the same as those in the methods of the first and second embodiments of the present invention, and will not be described in detail herein.

[0183] Embodiment 4

[0184] This embodiment provides a semiconductor memory device, the semiconductor memory device comprising:

[0185] A semiconductor substrate, wherein the semiconductor substrate has at least one groove, and an opening of the groove faces a surface of the substrate;

[0186] at least one gate component, wherein the gate component is buried in the groove;

[0187] Wherein, the groove is a slit structure, and the aspect ratio of the slit structure is between 1:500 and 500:1.

[0188] In a further embodiment of this embodiment, the width of the slit structure is between 2 nm and 1000 nm, and the depth of the slit structure is between 2 nm and 1000 nm.

[0189] In this embodiment, the substrate surface includes source regions respectively located outside the gate components and drain regions located between the gate components.

[0190] The gate component may be a multi-layer structure, for example, including a gate dielectric layer and a gate electrode located on the gate dielectric layer.

[0191] In another further embodiment of this embodiment, the gate component may further include a polysilicon gate located between the gate dielectric layer and the gate electrode.

[0192] In another further embodiment of this embodiment, the gate electrode includes a metal liner layer located on the gate dielectric layer and a conductive metal layer located on the metal liner layer.

[0193] The gate dielectric layer material may be a suitable dielectric material such as SiO2. The metal liner layer material may be a metal-nonmetal oxide, a multi-component compound or an alloy having conductive properties. The conductive metal layer may be a suitable conductive metal such as tungsten. The selection of the materials of each layer of the gate assembly is described here only by way of example, and the materials of each layer may of course be defined or selected according to actual needs.

[0194] In this embodiment, the method for forming the slit structure is the same as the method for preparing the slit structure in Embodiment 1 and Embodiment 2 of the present invention, and will not be described in detail herein.

[0195] In summary, the present invention provides a method for preparing a slit structure, which comprises at least the following steps: providing a substrate; coating a photoresist layer on the substrate; forming a first groove in the photoresist layer; depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first groove to form a second groove, wherein the width of the second groove is less than the width of the first groove; modifying the spacer layer so that different regions of the spacer layer have different etching rates; etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is less than the width of the first groove. The method for preparing a slit structure of the present invention covers the sidewalls and bottom of the first groove by the spacer layer, and forms a second groove whose groove width is smaller than that of the first groove in the first groove, and modifies the spacer layer covering the sidewalls and bottom of the first groove and the photoresist layer so that different regions of the spacer layer have different molecular structures, and utilizes the difference in etching rates of materials with different molecular structures to achieve that when the spacer layer is etched, the etching rate in the second groove is faster than the etching rate outside the second groove, and finally obtains a complete slit structure. And the etching rate of the spacer layer inside and outside the second groove can be controlled by adjusting the energy, ion type and / or ion concentration of the ion implantation, so as to control the size of the slit structure. The method can form a micro-pore structure or micro-groove below the limiting resolution. The slit structure of the present invention, because it has a significantly smaller size than the prior art, helps to reduce the size of related semiconductor devices, such as semiconductor memory devices, while ensuring the good functionality of the semiconductor device. The semiconductor memory device of the present invention and its preparation method can reduce the size of the device while ensuring the performance of the semiconductor device, which is conducive to the integration of the device.

[0196] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations shall all fall within the scope defined by the appended claims.

Claims

1. A method for preparing a slit structure, characterized in that: At least the following steps are included: S100, providing a substrate (1101); S200, coating a photoresist layer (1103) on the substrate; S300, forming a first groove (1107) in the photoresist layer; S400, depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench (1106), wherein the width of the second trench is smaller than the width of the first trench; S500, modifying the spacer layer so that an etching rate of a portion of the spacer layer at the bottom of the first trench is greater than an etching rate of a portion of the spacer layer covering a sidewall of the first trench and the photoresist layer; S600, etching the modified spacer layer to form a slit structure (1403) on the substrate, wherein the width of the slit structure is smaller than the width of the first groove.

2. The preparation method according to claim 1, characterized in that: Step S500, modifying the spacer layer includes doping different ions in the spacer layer portion (1105) covering the sidewall of the first trench and the photoresist layer and the spacer layer portion (1104) covering the bottom of the first trench.

3. The preparation method according to claim 1, characterized in that: Step S500, modifying the spacer layer includes injecting ions into the spacer layer, and controlling the spacer layer portion covering the sidewall of the first trench and the photoresist layer and the spacer layer portion covering the bottom of the first trench to have different ion concentrations.

4. The preparation method according to claim 1, characterized in that: Step S500 , modifying the spacer layer includes doping ions in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer.

5. The preparation method according to claim 4, characterized in that: The spacer layer is modified by ion implantation, wherein the ion implantation angle is greater than 0° and less than arc tan A / B, where A is the depth of the second groove and B is is the width of the second groove.

6. The preparation method according to claim 5, characterized in that: The ion implantation has a depth of 2 nm to 1000 nm and an intensity of 2 KeV to 900 KeV.

7. The preparation method according to claim 5, characterized in that: The implanted ions include boron ions or phosphorus ions.

8. The preparation method according to claim 1, characterized in that: The spacer layer includes a silicon oxide layer or a silicon nitride layer.

9. The preparation method according to claim 1, characterized in that: Step S600, etching the modified spacer layer to form a slit structure on the substrate comprises: dry etching the modified spacer layer; The substrate is etched to form a slit structure.

10. The method according to claim 8, characterized in that After etching the substrate to form a slit structure, the following steps are also included: removing the spacer layer covering the photoresist layer and the sidewall and bottom of the first trench; The photoresist layer is removed.

11. The preparation method according to any one of claims 1 to 10, characterized in that: Before coating the photoresist layer on the substrate, the method further includes forming a semiconductor layer (1102) on the substrate.

12. The preparation method according to claim 11, characterized in that: The step of etching the modified spacer layer to form a slit structure on the substrate also includes the step of etching the semiconductor layer.

13. The preparation method according to any one of claims 1 to 10, characterized in that: Before coating the photoresist layer on the substrate, a step of forming a hard mask on the substrate is also included, wherein the hard mask includes one of SiN, SiO2, TaN and TiN or a combination thereof.

14. The preparation method according to claim 13, characterized in that: The step of etching the modified spacer layer to form a slit structure on the substrate further includes: etching the hard mask to form a third trench on the hard mask; The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

15. A slit structure, prepared by the method of claim 1, characterized in that: The slit structure comprises: Substrate, The substrate has a plurality of slit structures, and the aspect ratio of the slit structures is between 1:500 and 500:

1.

16. The slit structure according to claim 15, characterized in that: The width of the slit structure is between 2nm and 1000nm.

17. The slit structure according to claim 15, characterized in that: The depth of the slit structure is between 2nm and 1000nm.

18. The slit structure according to claim 15, characterized in that: The slit structure further includes a semiconductor layer formed on the substrate, and the slit structure is formed in the semiconductor layer of the substrate.

19. A method for preparing a semiconductor memory device, characterized in that: The method comprises the following steps: S100, providing a semiconductor substrate; S200, coating a photoresist layer on the substrate; S300, forming a first groove in the photoresist layer; S400, depositing a spacer layer covering the photoresist layer and the sidewalls and bottom of the first trench to form a second trench, wherein the width of the second trench is smaller than the width of the first trench; S500, modifying the spacer layer so that an etching rate of a portion of the spacer layer at the bottom of the first trench is greater than an etching rate of a portion of the spacer layer covering a sidewall of the first trench and the photoresist layer; S600, etching the modified spacer layer to form a slit structure on the substrate, wherein the width of the slit structure is smaller than the width of the first groove; and S700, forming a gate component in the slit structure.

20. The preparation method according to claim 19, characterized in that: Modifying the spacer layer includes doping different ions in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer and a portion of the spacer layer covering the bottom of the first trench.

21. The preparation method according to claim 19, characterized in that: Modifying the spacer layer includes injecting ions into the spacer layer, and controlling the spacer layer portion (1105) covering the sidewall of the first trench and the photoresist layer and the spacer layer portion (1104) covering the bottom of the first trench to have different ion concentrations.

22. The preparation method according to claim 19, characterized in that: Modifying the spacer layer includes doping ions only in a portion of the spacer layer covering the sidewall of the first trench and the photoresist layer.

23. The preparation method according to claim 22, characterized in that: In the process of modifying the spacer layer by ion implantation, the ion implantation angle is greater than 0° and less than arc tan A / B, where A is the depth of the second trench and B is the width of the second trench.

24. The preparation method according to claim 23, characterized in that: The ion implantation has a depth of 2 nm to 1000 nm and an intensity of 2 KeV to 900 KeV.

25. The preparation method according to claim 23, characterized in that: The implanted ions include boron ions or phosphorus ions.

26. The preparation method according to claim 19, characterized in that: The spacer layer includes silicon oxide or silicon nitride.

27. The preparation method according to claim 19, characterized in that: The step of etching the modified spacer layer to form a slit structure on the substrate comprises: dry etching the modified spacer layer; The substrate is etched to form a slit structure.

28. The preparation method according to claim 26, characterized in that: After etching the substrate to form a slit structure, the following steps are also included: removing the spacer layer covering the photoresist layer and the sidewall and bottom of the first trench; The photoresist layer is removed.

29. The preparation method according to any one of claims 19 to 28, characterized in that: Before coating the photoresist layer on the substrate, the method further includes forming a semiconductor layer on the substrate.

30. The preparation method according to claim 29, characterized in that: The step of etching the modified spacer layer to form a slit structure on the substrate further includes etching the semiconductor layer.

31. The preparation method according to any one of claims 19 to 28, characterized in that: Before coating the photoresist layer on the substrate, a hard mask is formed on the substrate. The hard mask comprises SiN, SiO2, TaN and TiN. one or a combination of them.

32. The preparation method according to claim 31, characterized in that: The step of etching the modified spacer layer to form a slit structure on the substrate further includes: etching the hard mask to form a third trench on the hard mask; The substrate is etched, and the third trench is transferred to the substrate through the hard mask to form a slit structure.

33. A semiconductor memory device, prepared by the method of claim 19, characterized in that: The semiconductor memory device comprises: A semiconductor substrate having at least one groove therein, wherein an opening of the groove faces a surface of the semiconductor substrate; and at least one gate component, wherein the gate component is buried in the groove; Wherein, the groove is a slit structure, and the aspect ratio of the slit structure is between 1:500 and 500:

1.

34. The semiconductor memory device according to claim 33, wherein: The width of the slit structure is between 2nm and 1000nm.

35. The semiconductor memory device according to claim 33, wherein: The depth of the slit structure is between 2nm and 1000nm.

36. The semiconductor memory device according to claim 33, wherein: The substrate surface includes source regions respectively located outside the gate components and drain regions located between the gate components.

37. The semiconductor memory device according to claim 33, wherein: The gate component includes a gate dielectric layer and a gate electrode.

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