Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same. A composite contact between a bit line and a semiconductor substrate (i.e., a source / drain region) is formed by stacking a metal contact and a polysilicon contact in sequence, thereby reducing the contact resistance between the bit line and the semiconductor substrate (i.e., the source / drain region). The present invention can also avoid the problem in the prior art that when the polysilicon contact is basically below the bit line, lateral etching during the process of etching the polysilicon contact below using the bit line (i.e., the bit line in a memory) as a mask causes the cross-sectional area of ​​the middle section of the polysilicon contact to become smaller and the resistance value to increase.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a well-known semiconductor storage device that is currently widely used in various electronic devices. Dynamic Random Access Memory (DRAM) consists of many repeated memory cells, each of which is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array. Each memory cell is electrically connected to each other through a word line (WL) and a bit line (BL).

[0003] In order to improve the integration of dynamic random access memory (DRAM) and speed up the operation speed of components, and to meet the needs of consumers for miniaturized electronic devices, the design of the length of the transistor channel region in dynamic random access memory (DRAM) has a trend of continuously shortening. However, this will cause serious problems such as short channel effect and reduced on current in the transistor. A known solution is to change the horizontal transistor structure in the dynamic random access memory (DRAM) to a vertical buried channel array transistor (BCAT) structure. The structure of the dynamic random access memory (DRAM) with a buried channel array transistor (BCAT) is as follows. Figure 1As shown, it includes: a semiconductor substrate 100, a gate (i.e., a word line) 104, and a bit line (i.e., a bit line of a memory) 110. The gate 104 is buried in a U-shaped longitudinal trench (not shown) of the semiconductor substrate 100 through a gate isolation layer 105, and is insulated and isolated from the semiconductor substrate 100 through a gate dielectric layer 102. Source / drain regions (not shown) are respectively formed in the semiconductor substrate 100 on both sides of the gate 104. The bit line (i.e., the bit line of the memory) 110 is connected to the source / drain region on one side of the gate 104 through a bit line contact (BLcontact) 108, and the source / drain region on the other side of the gate 104 is led outward through an upper conductive plug 112. The bit line 110 and the conductive plug 112 are both formed in an interlayer dielectric layer 111. Since the current needs to flow along the U-shaped longitudinal groove portion between the source region (i.e., the source / drain region on one side of the gate 104) and the drain region (the source / drain region on the other side of the gate 104, not shown in the figure), the actual effective channel length becomes longer, which reduces the area occupied by the transistor in each storage unit and can suppress the short channel effect.

[0004] The bit line contact 108 below the bottom of the bit line 110 of the existing dynamic random access memory is mostly formed of polysilicon, that is, the bit line contact 108 is mostly a polysilicon conductive contact structure. The resistance of polysilicon is higher than that of metal. Moreover, after the bit line 110 is formed, the bit line contact 108 needs to be etched using the bit line 110 as a mask so that the line width of the bit line contact 108 is equal to the line width of the bit line 110. When the bit line contact 108 is polysilicon, the process of etching the bit line contact 108 using the bit line 110 as a mask will cause lateral etching to the middle section of the bit line contact 108, thereby causing the cross-sectional area of ​​the middle section of the bit line contact 108 to become smaller, resulting in an increase in the resistance of the bit line contact 108, which will affect the performance and reliability of the storage unit, and even cause problems such as data access errors of the DRAM.

[0005] In view of this, it is necessary to design a new semiconductor device and a preparation method thereof to solve the above problems. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the contact resistance of the bit line contacts and improve the device performance.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0008] providing a semiconductor substrate having a gate;

[0009] forming a metal contact on the semiconductor substrate on one side of the gate;

[0010] forming a first polysilicon contact on the metal contact; and,

[0011] A bit line is formed on the first polysilicon contact.

[0012] Optionally, the step of forming the gate includes:

[0013] Providing a semiconductor substrate, and etching the semiconductor substrate to form a gate trench;

[0014] forming a gate dielectric layer on the sidewalls and bottom wall of the gate trench;

[0015] Filling a gate material in the gate trench to form the gate, wherein a top surface of the gate is lower than a top surface of the semiconductor substrate on a sidewall of the gate trench; and,

[0016] A gate isolation layer is filled in the gate trench, and the gate isolation layer fills up the gate trench to bury the gate therein.

[0017] Optionally, the gate is a metal gate, and the gate dielectric layer is a high-K dielectric with a dielectric constant greater than 4; after forming the gate dielectric layer and before filling the gate, a metal barrier layer is formed on the surface of the gate dielectric layer, and after the gate is filled, the metal barrier layer surrounds the bottom wall and side wall of the gate and exposes the surface of the gate dielectric layer above the gate, so that the side wall of the gate isolation layer directly contacts the side wall surface of the gate dielectric layer.

[0018] Optionally, the step of forming the metal contact and the first polysilicon contact includes:

[0019] Forming a hard mask layer on the semiconductor substrate having the gate, wherein the hard mask layer has an opening exposing a portion of the surface of the semiconductor substrate on one side of the gate;

[0020] Using the hard mask layer as a mask, etching the semiconductor substrate to form a contact trench;

[0021] Filling the metal contact in the contact trench, wherein the top surface of the metal contact is lower than the top surface of the hard mask layer;

[0022] The first polysilicon contact is filled in the contact trench.

[0023] Optionally, before filling the metal contact in the contact trench, a second polysilicon contact is first filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.

[0024] Optionally, the step of forming the bit line comprises:

[0025] forming a sacrificial layer covering the semiconductor substrate and the first polysilicon contact, wherein the sacrificial layer has an opening exposing a portion of a top surface of the first polysilicon contact;

[0026] filling the bit line in the opening of the sacrificial layer; and,

[0027] The sacrificial layer is removed, and the first polysilicon contact and the metal contact are sequentially etched to the top interface of the semiconductor substrate using the bit line as a mask, so that the first polysilicon contact and the metal contact have the same width as the bit line.

[0028] Optionally, the method for preparing a semiconductor device further includes:

[0029] forming an interlayer dielectric layer on the semiconductor substrate and the gate, wherein the interlayer dielectric layer buries the bit line; and,

[0030] A conductive plug is formed in the interlayer dielectric layer, wherein a bottom surface of the conductive plug contacts a surface of the semiconductor substrate on the other side of the gate.

[0031] Optionally, at least one active area is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active area, each gate trench is filled with the gate, a first source / drain area is formed in the active area between the two gate trenches, and a second source / drain area is formed in the active area on the opposite sides of the two gate trenches, the metal contact is formed above the first source / drain area and is electrically contacted with the first source / drain area, and the conductive plug is formed above the second source / drain area and is electrically contacted with the second source / drain area.

[0032] The present invention also provides a semiconductor device, comprising:

[0033] a semiconductor substrate having a gate;

[0034] A metal contact is located on the semiconductor substrate on one side of the gate;

[0035] A first polysilicon contact is stacked on the metal contact; and

[0036] The bit line is stacked on the first polysilicon contact.

[0037] Optionally, a gate trench is formed in the semiconductor substrate, the gate is filled in the gate trench and the top surface is lower than the top surface of the semiconductor substrate on the side wall of the gate trench; the semiconductor device also includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer is formed on the side wall and bottom wall of the gate trench; the gate isolation layer is filled in the gate trench and fills the gate trench to bury the gate therein.

[0038] Optionally, a contact trench is formed in the semiconductor substrate on one side of the gate, the metal contact is filled in the contact trench, and the top surface of the metal contact is not higher than the top surface of the semiconductor substrate on the side wall of the contact trench.

[0039] Optionally, the semiconductor device further includes a second polysilicon contact, wherein the second polysilicon contact is filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.

[0040] Optionally, the semiconductor device further includes:

[0041] an interlayer dielectric layer, covering the semiconductor substrate and the gate, wherein the interlayer dielectric layer buries the bit line; and

[0042] A conductive plug is formed in the interlayer dielectric layer, and a bottom surface of the conductive plug contacts a surface of the semiconductor substrate at the other side of the gate trench.

[0043] Optionally, at least one active area is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active area, each of the gate trenches is filled with the gate, a first source / drain area is formed in the active area between the two gate trenches, and a second source / drain area is formed in the active area on the opposite sides of the two gate trenches, respectively, the metal contact is formed above the first source / drain area and is electrically in contact with the first source / drain area, the conductive plug is formed above the second source / drain area and is electrically in contact with the second source / drain area; gaps are formed between the metal contact and the first polysilicon contact and the side walls facing the gate trenches, and the interlayer dielectric layer fills the gaps.

[0044] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0045] 1. The semiconductor device and the preparation method thereof of the present invention can reduce the contact resistance between the bit line and the semiconductor substrate (i.e., the source / drain region) by stacking metal contacts and polysilicon contacts in sequence to form a composite contact between the bit line and the semiconductor substrate (i.e., the source / drain region). It can also avoid the problem in the prior art that when the polysilicon contact is basically below the bit line, the lateral etching in the process of etching the polysilicon contact below using the bit line (i.e., the bit line in the memory) as a mask causes the cross-sectional area in the middle section of the polysilicon contact to become smaller and the resistance value to increase.

[0046] 2. The semiconductor device and the preparation method thereof of the present invention are applicable to the manufacture of any product having a metal gate, and are particularly applicable to a dynamic random access memory (DRAM) having a buried channel array transistor (BCAT) structure, and can improve the resistance of the contact at the bottom of the bit line and enhance the performance of the DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a known DRAM with BCAT (only the structure at one active region is shown).

[0048] Figure 2 The present invention is a flow chart of a method for preparing a semiconductor device according to a specific embodiment of the present invention.

[0049] Figures 3A to 3J yes Figure 2 A schematic cross-sectional view of a device structure in a method for preparing a semiconductor device is shown.

[0050] The reference numerals are as follows:

[0051] 100- semiconductor substrate;

[0052] 1002-first source / drain region;

[0053] 1003- second source / drain region;

[0054] 101-gate trench;

[0055] 102-gate dielectric layer;

[0056] 103, 1084, 1087, 1102 - metal barrier layer;

[0057] 104-gate;

[0058] 105-gate isolation layer;

[0059] 106-hard mask layer;

[0060] 107-contact groove;

[0061] 107a - gap;

[0062] 108-bit line contacts;

[0063] 1080-second polysilicon contact

[0064] 1081-metal contact;

[0065] 1082 - first polysilicon contact;

[0066] 1083, 1088, 1101 - metal silicide layer;

[0067] 1085, 1086, 1103 - metal adhesion layer;

[0068] 109-sacrificial layer;

[0069] 109a - opening in the sacrificial layer;

[0070] 110-bit line;

[0071] 1104 - bit line metal layer;

[0072] 111-interlayer dielectric layer;

[0073] 112-Conductive plug. DETAILED DESCRIPTION

[0074] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0075] Please refer to Figure 2 The present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0076] S1, providing a semiconductor substrate having a gate;

[0077] S2, forming a metal contact on the semiconductor substrate on one side of the gate;

[0078] S3, forming a first polysilicon contact on the metal contact; and,

[0079] S4, forming a bit line on the first polysilicon contact.

[0080] The method for preparing a semiconductor device of the present invention is described in detail below by taking a method for preparing a semiconductor device having a BCAT structure as an example.

[0081] Please refer to Figure 3A First, step S1 is performed to provide a semiconductor substrate 100 having a gate 104. The specific process includes:

[0082] Step 1, provide a semiconductor substrate 100. The semiconductor substrate 100 can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide or germanium on insulator. The semiconductor substrate 100 in this embodiment includes a base (not shown) and a semiconductor epitaxial layer (not shown) epitaxially grown on its surface. The semiconductor substrate 100 can be defined with at least one active area (not shown, formed in the semiconductor epitaxial layer) for forming a buried channel array transistor (BCAT) and a shallow trench isolation structure (not shown) for isolating the active area from the surrounding environment. The active area (not shown) can be a fin-type three-dimensional structure or a planar structure. When the semiconductor device to be manufactured is a memory, the shallow trench isolation structure can isolate all active areas into an array arrangement to manufacture a memory array of the memory. The shallow trench isolation structure may include a shallow trench (not shown) located in the semiconductor substrate 100 and a dielectric material filling the shallow trench. The dielectric material may include a liner oxide layer (line oxide) formed by a thermal oxidation process and covering the shallow trench, and silicon dioxide located on the surface of the liner oxide layer and filling the shallow trench, thereby improving the isolation performance of the shallow trench isolation structure. The specific formation process includes: (1) forming a pad oxide layer (not shown) on the surface of the semiconductor substrate 100 by a thermal oxidation process; (2) forming a silicon nitride hard mask layer (not shown) by a chemical vapor deposition process, and further forming a patterned photoresist layer (not shown) on the silicon nitride hard mask layer by photolithography processes such as photoresist coating, exposure, and development, wherein the patterned photoresist layer covers the active area and the layers above it, and exposing the silicon nitride hard mask layer above the semiconductor substrate 100 used as an isolation region between the active regions; (3) using the patterned photoresist layer as a mask, performing an etching process on the exposed silicon nitride hard mask layer and the pad oxide layer below it and a portion of the depth of the semiconductor substrate 100 to form a shallow trench in the semiconductor substrate 100 between the active regions, and the etching process can be dry etching; (4) removing the patterned photoresist layer; (5) forming a liner oxide layer (line oxide layer) by a vapor deposition process or a thermal oxidation process. oxide, not shown in the figure) on the sidewall and bottom surface of the shallow trench; (6) using chemical vapor deposition and other processes to deposit silicon dioxide on the surface of the shallow trench and the surface of the silicon nitride hard mask layer until the silicon dioxide fills the shallow trench; (7) using a chemical mechanical planarization process to planarize the top surface of the silicon dioxide until the top surface of the silicon dioxide is flush with the top surface of the silicon nitride hard mask layer to form a shallow trench isolation structure; (8) the silicon nitride hard mask layer can be removed by wet etching and other processes.Further, after depositing silicon dioxide, or after flattening the top surface of the silicon dioxide, or after removing the silicon nitride hard mask layer, the silicon dioxide is subjected to densification by high-energy light activation processes such as high-temperature thermal annealing, ultraviolet light (UV) or laser, etc., so as to increase the density of the dielectric material, ensure the isolation effect of the shallow trench isolation structure, and strengthen its mechanical strength. The process temperature of the high-temperature thermal annealing process is, for example, 800°C to 1200°C, and highly reactive gases such as ozone (O3) and / or carbon monoxide (CO) may be further introduced during the high-temperature thermal annealing process. In addition, after forming the shallow trench isolation structure, a well region (not shown) may be formed in each active region by an ion implantation process and further combined with annealing activation processes, wherein the doping type of the well region is determined by the conductivity type of the BCAT transistor to be formed. For example, in this embodiment, if the formed BCAT transistor is an N-type transistor, the well region is a P-type doped region. The doping depth of the well region can be adjusted according to actual conditions. It should be noted that the above-mentioned pad oxide layer can protect the semiconductor substrate 100 and the active area during the process of forming the shallow trench isolation structure, and the pad oxide layer can continue to be retained as a protective layer for the top surface of the semiconductor substrate 100 and the active area in subsequent processes.

[0083] Step 2, please continue to refer to Figure 3A, a patterned hard mask layer (not shown) is sequentially formed on the surface of the shallow trench isolation structure and the pad oxide layer. The specific formation process includes: (1) a hard mask layer can be formed on the surface of the shallow trench isolation structure and the pad oxide layer by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other processes. The material of the hard mask layer includes at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal nitride, metal oxide and metal carbide, preferably silicon nitride (SiN). Silicon nitride material is easy to obtain, low in cost, mature in manufacturing method, and has a high etching selectivity with the pad oxide layer; (2) a hard mask layer can be formed by photoresist coating, using a gate mask (gate (1) a photoresist layer having the opening is used as a mask, and the hard mask layer is etched to the surface of the pad oxide layer to transfer the gate (i.e., word line) pattern in the photoresist to the hard mask layer; (2) the photoresist is removed, and the hard mask layer is used as a mask to continue etching downward, that is, the pad oxide layer and the semiconductor substrate 100 (including the active area and the shallow trench isolation structure) are etched in sequence to form a gate trench 101 in the semiconductor substrate 100. In this embodiment, the bottom wall of the gate trench 101 also extends downward into the substrate 1001. The shape of the gate trench 101 can be a rounded U-shape, a right-angled U-shape, or a trapezoidal shape with a wide top and a narrow bottom. Since the electrical characteristics of the buried channel array transistor (BCAT) can be changed according to the depth from the upper surface (i.e., the top surface) of the semiconductor substrate 100 to the bottom surface of its buried gate 104, the depth of the gate trench 101 can be adjusted to achieve the required electrical characteristics of the buried channel array transistor (BCAT), thereby improving the electrical performance and reliability of the ultimately formed semiconductor device.

[0084] Step 3, please continue to refer to Figure 3A , the pad oxide layer, hard mask layer, etc. on the surface of the semiconductor substrate 100 can be removed by etching process or chemical mechanical planarization process, and further cleaned to expose the clean active area surface and the sidewall and bottom surface of the gate trench 101, so as to prepare for the formation of the gate 104. In this embodiment, two gate trenches 101 are arranged side by side in an active area of ​​the semiconductor substrate 100, and the active area between the two gate trenches 101 is used to form the first source / drain area later, and the active areas on the opposite sides of the two gate trenches 101 are used to form the second source / drain area respectively later, so that two BCATs can be made in one active area, which is conducive to improving the device integration.

[0085] Step 5: A thermal oxidation (dry oxygen or wet oxygen) process, chemical vapor deposition, atomic layer deposition and other processes may be used to cover the gate dielectric layer 102 on the active area and the sidewall and bottom surface of the gate trench 101. The material of the gate dielectric layer 102 is preferably a high-K dielectric (dielectric constant K is greater than 7). The material of the high-K dielectric is, for example, Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or other metal oxides, etc., to be compatible with the metal gate 104 to be formed, which is conducive to improving the mobility of carriers and improving device performance. It is also preferred to use atomic layer deposition (ALD) to prepare the gate dielectric layer 102 of high-K dielectric material to maintain the film quality and thickness uniformity of the gate dielectric layer 102.

[0086] Step six, depositing a metal barrier layer 103 on the surface of the gate dielectric layer 102 by physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes. Preferably, the metal barrier layer 103 is prepared by atomic layer deposition process to protect the gate dielectric layer 102 and prevent the gate dielectric layer 102 from deteriorating in quality. The metal barrier layer 103 is also called a metal barrier layer or a metal adhesion barrier layer, which is intended to protect the gate dielectric layer 102 from the introduction of metal impurities in subsequent steps, and to improve the adhesion between the gate dielectric layer 102 and the gate 104 formed subsequently. For example, in this embodiment, the gate 104 includes one or more work function metal layers. In the absence of the metal barrier layer 103, the metal materials from those work function metal layers will diffuse into the gate dielectric layer 102, thereby causing manufacturing defects. In various embodiments, the metal barrier layer 103 includes a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN or TaN, or any combination of metals and metal nitrides. It should be recognized that in some cases, a single-layer metal barrier layer 103 may not provide sufficient protection for the gate dielectric layer 102, and it is necessary to form a metal barrier layer 103 with a composite structure of multiple layers stacked in the gate trench 101 to enhance the protection of the gate dielectric layer 102 to prevent the surface metal barrier layer 103 from being etched and damaged, and the material in the gate 104 will be contaminated and diffused into the gate dielectric layer 102, causing device defects.

[0087] Step seven, depositing metal gate material on the surface of the metal barrier layer 103 by processes such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, etc., and the deposition thickness of the metal gate material on the bottom surface of the first gate trench 101 must at least reach the thickness required for the gate 104 to be formed.

[0088] In step eight, the metal gate material on the area outside the gate trench 101 can be removed by etching back, and the metal gate material is only filled in the gate trench 101 to serve as the gate 104. The etching back process makes the height of the gate 104 smaller than the depth of the gate trench 101, and reduces the height of the metal barrier layer 103 to not higher than the gate 104. The gate 104 is generally a stacked structure, including a work function metal layer covering the metal barrier layer 103 and a metal electrode layer surrounded by the work function metal layer. The material selection of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed. When the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a P-type work function metal material, and the P-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, W, other suitable P-type work function materials, or a combination thereof. When the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the metal gate 104 is an n-type work function metal material, and the n-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or a combination thereof. The work function metal layer may be a single layer or multiple layers. In this embodiment, the top surface of the gate 104 is lower than the top surface of the semiconductor substrate 100 on both sides, and further lower than the top surface of the first source / drain region 1002 and the second source / drain region 1003 formed subsequently, so that the distance between the work function metal layer and the first source / drain region 1002 and the second source / drain region 1003 is increased, which is beneficial to prevent the work function metal layer from gate-induced drain leakage (GIDL) between the first source / drain region 1002 and the second source / drain region 1003. The material of the metal electrode layer may include Al, W, Cu and / or other suitable metal materials.

[0089] Step 9. Please refer to Figure 3B A gate isolation layer 105 is deposited on the semiconductor substrate 100, the gate dielectric layer 102, the metal barrier layer 103 and the gate 104 by using physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes. The material of the gate isolation layer 105 includes but is not limited to silicon oxide, silicon nitride and silicon oxynitride.

[0090] Step 10: Please refer to Figure 3C, the redundant gate isolation layer 105 and the gate dielectric layer 102 on the top surface of the semiconductor substrate 100 can be removed by a chemical mechanical planarization process to form a gate 104 buried in the gate trench 101, and further, using the gate 104 and the gate isolation layer 105 as masks, LDD (lightly doped drain) ion implantation, Halo (halo) ion implantation, and source-drain heavily doped ion implantation are performed on the active regions on both sides of the gate (i.e., the gate trench 101) to respectively form a first source / drain region 1002 and a second source / drain region 1003 in the active regions on both sides of the gate 104 (i.e., the gate trench 101), thereby, the gate 104 and the first source / drain region 1002 and the second source / drain region 1003 separated on both sides of the gate 104 constitute the main part of the BCAT structure. In this embodiment, since two gate trenches 101 are formed in one active area, two BCATs can be manufactured in one active area, and a first source / drain region 1002 shared by the two BCATs is formed in the active area between the two gate trenches 101. The shared first source / drain region 1002 can be a drain region electrically connected to a subsequently formed bit line 110 (i.e., a bit line of the memory), and the second source / drain region 1003 can be a source region electrically connected to a subsequently formed conductive plug 112. In other embodiments of the present invention, the gate dielectric layer 102 and the gate isolation layer 105 on the surface of the active area between the two gates 104 and outside the two gates 104 can also be etched by an etching process to form an opening that exposes the surface of the active area for forming the first source / drain area 1002 and the second source / drain area 1003, and then, using the remaining gate dielectric layer 102 and the gate isolation layer 105 as a mask, the exposed active area is subjected to LDD (lightly doped drain) ion implantation, Halo (halo) ion implantation, and source / drain heavily doped ion implantation, etc., to form the first source / drain area 1002 and the second source / drain area 1003 in the active area on both sides of the gate 104. When the gate trench 101 is a U-shaped trench, a U-shaped conductive channel can be formed along the current conduction direction (i.e., the current flow direction from the source area to the drain area on both sides of the gate 104), thereby increasing the length of the conductive channel. Thus, as the size of the transistor decreases, even if the absolute distance between the source region and the drain region on both sides of the gate 104 decreases, the short channel effect of the transistor structure can be effectively improved because the formed conductive channel is a U-shaped channel.In addition, the first source / drain region 1002 and the second source / drain region 1003 are doped with ions of corresponding conductivity types according to transistor structures of different conductivity types. For example, when the transistor structure is an N-type transistor, the doped ions in the source / drain region are N-type doped ions, and the N-type doped ions are, for example, phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; when the transistor structure is a P-type transistor, the doped ions in the source / drain region are P-type doped ions, and the P-type doped ions are, for example, boron (B) ions and boron fluoride (BF2). + ) ions, gallium (Ga) ions, and indium (In) ions.

[0091] Please refer to Figure 3D and 3E In step S2, a metal contact 1081 is formed on the first source / drain region 1002. The specific process includes:

[0092] Step 1: Please refer to Figure 3D The hard mask layer 106 may be deposited by chemical vapor deposition, physical vapor deposition or other processes. The hard mask layer 106 covers the first source / drain region 1002, the second source / drain region 1003 and the gate isolation layer 105. The material of the hard mask layer 106 includes at least one of silicon oxide, silicon nitride and silicon oxynitride. The hard mask layer 106 above the first source / drain region 1002 is further opened by photolithography and etching processes to form an opening exposing the surface of the first source / drain region 1002.

[0093] Step 2: Please refer to Figure 3D , using the hard mask layer 106 with the opening as a mask, the first source / drain region 1002 is etched to a certain depth to form a contact trench 107, the bottom surface of the contact trench 107 is higher than the top surface of the gate 104, so as to enhance the isolation performance between the subsequently formed bit line 110 and the gate 104. In this embodiment, the contact trench 107 is connected to the two gate trenches 101 at the sidewalls.

[0094] Step 3: Please refer to Figure 3D and 3E, by adopting any suitable process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., a first layer of polysilicon, a metal barrier layer and a metal adhesion layer are deposited on the surface of the contact groove 107 and the hard mask layer 106, and the first layer of polysilicon may include at least one of doped polysilicon and undoped polysilicon, and the first layer of polysilicon, the metal barrier layer 1084 and the metal adhesion layer 1085 outside the contact groove 107 are further removed by an etching process or a chemical mechanical planarization (CMP) process to form a second polysilicon contact 1080, a metal barrier layer 1084, and a metal adhesion layer 1085 stacked in sequence. The second polysilicon contact 1080 is used to protect the first source / drain region 1002 from being damaged by the manufacturing process of the metal contact 1081. The metal adhesion layer 1085 can enhance the adhesion between the subsequent metal contact 1081 and the second polysilicon contact 1080 to prevent the poor contact between the metal contact 1081 and the first source / drain region 1002. The material of the metal adhesion layer 1085 can be a metal such as W, Ti or Ta. The metal barrier layer 1084 can prevent the metal in the metal contact 1081 from diffusing into the first source / drain region 1002 and affecting the first source / drain region 1002. In order to improve the performance of the drain region 1002, the material of the metal barrier layer 1084 can be a metal nitride such as TiAlN, TaCN, TaSiN, TiN or TaN; and in the present embodiment, in order to reduce the contact resistance between the second polysilicon contact 1080 and the subsequently formed metal contact 1081, a metal silicide layer 1083 is further formed between the interface of the metal barrier layer 1084 and the second polysilicon contact 1080, and the metal silicide layer 1083 can be a metal silicide containing at least one of the metal elements such as Ti, W, Co, Ni, Zr, Mo, Ta, etc. The formation process of the metal silicide layer 1083 is preferably as follows: using the metal material or metal nitride material for forming the metal barrier layer 1084, first depositing a metal-containing film on the surface of the second polysilicon contact 1080, and then annealing, so that the surface layer of the second polysilicon contact 1080 and the metal in the metal-containing film react naturally, thereby forming the metal silicide layer 1083 at the interface of the second polysilicon contact 1080, thereby simplifying the process, saving costs, and being able to reduce contact resistance while enhancing the adhesion between the second polysilicon contact 1080 and the metal barrier layer 1084. In other embodiments of the present invention, one, two or all of the second polysilicon contact 1080, the metal barrier layer 1084, and the metal adhesion layer 1085 may also be omitted.

[0095] Step 4: Please refer to Figure 3E, Al, W, Cu and / or other suitable metal materials can be filled in the contact groove 107 by evaporation, electroplating, chemical vapor deposition, atomic layer deposition and other processes, and the metal material on the top of the hard mask layer 106 can be further removed by chemical mechanical planarization process to form a metal contact 1081.

[0096] Please refer to 3E and Figure 3FIn step S3, a first polysilicon contact (poly contact) 1082 is filled in the contact trench 107. Specifically, a metal adhesion layer 1086, a metal barrier layer 1087, a metal silicide layer 1088 and a second polysilicon layer are sequentially formed on the surface of the contact trench 107 having the metal contact 1081 and the hard mask layer 106 by adopting any suitable process such as physical vapor deposition (including sputtering, evaporation), chemical vapor deposition, atomic layer deposition, etc., and the metal adhesion layer 1086, the metal barrier layer 1087, the metal silicide layer 1088 and the second polysilicon layer outside the contact trench 107 are further removed by an etching process or a chemical mechanical planarization (CMP) process to form a metal adhesion layer 1086, a metal barrier layer 1087, a metal silicide layer 1088 and a first polysilicon contact 1082 stacked on the metal contact 1081 in sequence. The first polysilicon contact 1082 may include at least one of doped polysilicon and undoped polysilicon, and its thickness is greater than the second polysilicon layer contact 1080, and may be comparable to or even greater than the thickness of the metal contact 1081, thereby reducing the contact resistance between the bit line 110 and the first source / drain region 1002 while ensuring the advantages of the bit line 110 contact only using polysilicon material; the metal adhesion layer 1086 may enhance the adhesion between the metal contact 1081 and the first polysilicon contact 1082, prevent the metal contact 1081 from having poor contact with the first polysilicon contact 1082, and prevent the metal adhesion layer 1086 from having poor contact with the first polysilicon contact 1082. The material of layer 1086 can be metal such as W, Ti or Ta; the metal barrier layer 1087 can prevent the metal in the metal contact 1081 from diffusing into the first polysilicon contact 1082 and affecting the performance of the first polysilicon contact 1082. The material of the metal barrier layer 1087 can be metal nitride such as TiAlN, TaCN, TaSiN, TiN or TaN; the metal silicide layer 1088 can reduce the contact resistance between the first polysilicon contact 1082 and the metal contact 1081. The metal silicide layer 1088 can be a metal silicide containing at least one of the metal elements such as Ti, W, Co, Ni, Zr, Mo, Ta and the like. The formation process of the metal silicide layer 1087 is preferably as follows: after depositing the second polysilicon layer, an annealing treatment is performed to utilize the natural reaction of metal and silicon at the interface between the metal barrier layer 1087 and the first polysilicon contact 1082, thereby forming a metal silicide layer 1088 at the interface between the metal barrier layer 1087 and the first polysilicon contact 1082, thereby simplifying the process, saving costs, and being able to reduce contact resistance while enhancing the adhesion between the first polysilicon contact 1082 and the metal barrier layer 1087. In other embodiments of the present invention, the metal barrier layer 1087 and / or the metal adhesion layer 1086 may also be omitted.

[0097] Please refer to Figure 3G and 3H In step S4, a bit line 110 is formed on the first polysilicon contact 1082. The specific process includes:

[0098] Step 1: Please refer to Figure 3G The sacrificial layer 109 can be formed by spin coating, chemical vapor deposition, physical vapor deposition and other processes to cover the hard mask layer 106 and the first polysilicon contact 1082, and an opening 109a is further formed in the sacrificial layer 109 by photolithography, etching and the like, and the width of the opening 109a is less than Figure 3D The width of the contact trench 107 shown in the figure is to expose a portion of the top surface of the first polysilicon contact 1082; the deposition thickness of the sacrificial layer 109 can determine the height of the bit line 110, and its material can be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material and / or other suitable insulating materials.

[0099] Step 2: Please refer to Figure 3G and 3H, a metal silicide layer 1101, a metal barrier layer 1102, a metal adhesion layer 1103 and a bit line metal layer 1104 are sequentially formed in the opening 109a by any suitable process such as evaporation, electroplating, chemical vapor deposition, atomic layer deposition, etc., and a chemical mechanical planarization process is further used to remove the metal material on the top of the sacrificial layer 109 to form the bit line 110. The bit line metal layer 1104 fills the opening 109a and may include Al, W, Cu and / or other suitable metal materials; the metal adhesion layer 1103 may enhance the adhesion between the bit line metal layer 1104 and the first polysilicon contact 1082 to prevent the bit line metal layer 1104 from having poor contact with the first polysilicon contact 1082, and the material of the metal adhesion layer 1103 may be a metal such as W, Ti or Ta; the metal barrier layer 1102 may prevent the metal in the bit line metal layer 1104 from diffusing to the first polysilicon contact 1082; In the first polysilicon contact 1082, the performance of the first polysilicon contact 1082 is affected. The material of the metal barrier layer 1102 can be a metal nitride such as TiAlN, TaCN, TaSiN, TiN or TaN; the metal silicide layer 1101 can reduce the contact resistance between the first polysilicon contact 1082 and the bit line metal layer 1104, and the metal silicide layer 1101 can be a metal silicide containing at least one of the metal elements such as Ti, W, Co, Ni, Zr, Mo, Ta, etc. The formation process of the metal silicide layer 1101 is preferably as follows: an annealing treatment is performed after the metal barrier layer 1102 is deposited, so as to form the metal silicide layer 1101 at the interface between the metal barrier layer 1102 and the first polysilicon contact 1082 by utilizing the natural reaction between metal and silicon at the interface between the metal barrier layer 1102 and the first polysilicon contact 1082, thereby simplifying the process, saving costs, and being able to reduce contact resistance while enhancing the adhesion between the first polysilicon contact 1082 and the metal barrier layer 1102. In other embodiments of the present invention, one or more of the metal silicide layer 1101, the metal barrier layer 1102 and the metal adhesion layer 1103 may also be omitted.

[0100] Step 3: Please refer to FIG. 3G to FIG. 3I, the sacrificial layer 109 is removed by a suitable process such as etching, and further, the first polysilicon contact 1082 and the metal contact 1081 are etched in sequence using the bit line 110 as a mask, and the etching stops at the interface between the first source / drain region 1002 and the second polysilicon contact 1080 to form a gap 107a. At this time, a structure stacked from the second polysilicon contact 1080 to the first polysilicon contact 1082 from bottom to top forms a bit line composite contact 108 with the same width as the bit line 110, and a gap 107a is formed between the side walls facing each other of the bit line composite contact 108 and the gate dielectric layer 102. Since the bit line composite contact 108 is a composite structure, mainly composed of a metal contact 1081 and a first polysilicon contact 1082 stacked on the metal contact 1081, the low resistance characteristic of the metal material can be used to reduce the contact resistance. At the same time, it can also avoid the problem in the prior art that the side wall of the polysilicon bit line contact becomes smaller in cross-sectional area and larger in resistance due to lateral etching.

[0101] Please refer to Figure 3J After that, the conductive plug 112 on the second source / drain region 1003 may be fabricated. The specific process includes:

[0102] First, the hard mask layer 106 can be removed by a suitable process (such as wet etching), and processes such as spin coating, chemical vapor deposition, and physical vapor deposition can be further combined with a chemical mechanical planarization process to form an interlayer dielectric layer 111 with a flat top surface to cover the gate isolation layer 105, the first source / drain region 1002, the second source / drain region 1003 and the bit line 110. The interlayer dielectric layer 111 fills the gap 107a and buries the bit line 110 and the bit line composite contact 108 therein. The material of the interlayer dielectric layer 111 can be silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material and / or other suitable insulating materials.

[0103] Then, a contact hole (not shown) aligned with the second source / drain region 1003 is formed in the interlayer dielectric layer 111 by photolithography, etching and other processes, and the contact hole exposes a portion of the top surface of the second source / drain region 1003 .

[0104] Next, the contact hole is filled with metal material such as W by electroplating, sputtering or other processes to form a conductive plug 112 filled in the contact hole of the interlayer dielectric layer 111 , and the bottom surface of the conductive plug 112 contacts the top surface of the second source / drain region 1003 .

[0105] The method for preparing a semiconductor device of the present invention substantially replaces the existing single polysilicon bit line contact with a bit line composite contact formed by stacking a polysilicon contact on top of a metal contact, thereby utilizing the low resistance property of the metal to reduce the contact resistance. Moreover, because the total thickness of the bit line composite contact is limited, when the metal contact is set, it is equivalent to reducing the thickness of the polysilicon contact. Therefore, the problem of lateral etching of the middle section of the polysilicon contact when etching the bit line composite contact using the bit line as a mask can be avoided, thereby ensuring the sidewall morphology of the bit line composite contact, thereby improving the device performance and reliability. The method for preparing a semiconductor device of the present invention is particularly suitable for the manufacture of a memory. When the method for preparing a semiconductor device of the present invention is applied to the manufacture of a memory, the gate electrodes 104 of multiple active regions are aligned and connected together to form a word line of the memory, and the bit lines 110 of multiple active regions are aligned and connected together to form a bit line of the memory. For example, please refer to Figures 3A to 3J In one embodiment of the present invention, the semiconductor substrate 100 has a plurality of active areas (not shown) arranged in unit rows (i.e., corresponding to the word line direction) and unit columns (i.e., corresponding to the bit line direction), and a shallow trench isolation structure (not shown) is also provided between adjacent active areas, that is, all shallow trench isolation structures may include several parallel lines and several intersecting lines, thereby isolating all active areas into an array structure arranged in unit rows and unit columns, for making a memory array of a memory. Each of the active areas arranged along the word line direction intersects with two adjacent gate trenches 101. The gate 104 filled in each gate trench 101 serves as the word line corresponding to the corresponding unit row, and the bit line 110 on the active area between the two gate trenches 101 serves as the bit line on the corresponding unit column.

[0106] Please refer to Figures 3A to 3J An embodiment of the present invention provides a semiconductor device, which is preferably prepared by the above-mentioned method for preparing a semiconductor device of the present invention. The semiconductor device includes: a semiconductor substrate 100 having a gate 104, a bit line composite contact 108, a bit line 110, an interlayer dielectric layer 111 and a conductive plug 112.

[0107] Among them, at least one active area (not shown) is formed in the semiconductor substrate 100, and at least one gate trench 101 is set in each active area. A first source / drain area 1002 and a second source / drain area 1003 are respectively formed in the active areas on both sides of the gate trench 101. The gate 104 is filled in the gate trench 101, and the height of the gate 104 is less than the depth of the gate trench 101. The semiconductor device also includes a gate isolation layer 105, and the gate isolation layer 105 is filled in the gate trench 101 and fills the gate trench 101 to bury the gate 104 therein.

[0108] In this embodiment, the semiconductor device further includes a gate dielectric layer 102 and a metal barrier layer 103, wherein the gate dielectric layer 102 is formed on the sidewalls and bottom wall of the gate trench 101, and the metal barrier layer 103 is formed between the gate dielectric layer 102 and the gate 104 and surrounds the bottom wall and sidewall of the gate 104, and the metal barrier layer 103 exposes the sidewall surface of the gate dielectric layer 102 above the gate 104. The material of the gate dielectric layer 102 is preferably a high-K dielectric (with a dielectric constant K greater than 7), and the material of the high-K dielectric is, for example, Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2 or other metal oxides of other components, so as to be compatible with the gate 104, which is conducive to improving the mobility of carriers and improving device performance. The metal barrier layer 103 is intended to protect the gate dielectric layer 102, prevent the introduction of metal impurities into the gate dielectric layer 102, and improve the adhesion between the gate dielectric layer 102 and the gate 104. The metal barrier layer 103 can be a single-layer structure or a stacked-layer structure, including a metal layer such as Ti or Ta, a metal nitride layer such as TiAlN, TaCN, TaSiN, TiN or TaN, or at least one of a metal and a metal nitride. In this embodiment, the gate 104 may include one or more work function metal layers and a metal electrode layer surrounded by the work function metal layer, wherein the material selection of the work function metal layer is determined by the conductivity type of the BCAT transistor to be formed. When the BCAT transistor to be formed is a P-type transistor, the work function metal layer in the metal gate 104 is a p-type work function metal material, and the p-type work function metal material may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, W and other suitable p-type work function materials or a combination thereof. When the BCAT transistor to be formed is an N-type transistor, the work function metal layer in the gate 104 is an n-type work function metal material, and the n-type work function metal material includes Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials or a combination thereof; the material of the metal electrode layer may include Al, W, Cu and / or other suitable metal materials.

[0109] In this embodiment, the bit line composite contact 108 is formed on the first source / drain region 1002, and the top surface of the bit line composite contact 108 can be flush with the top surface of the gate isolation layer 105, can be lower than the top surface of the gate isolation layer 105, or can be higher than the top surface of the gate isolation layer 105. The bit line composite contact 108 includes a metal contact 1081 and a first polysilicon contact 1082 stacked thereon. A second polysilicon contact 1080, a metal silicide layer 1083, a metal barrier layer 1084, and a metal adhesion layer 1085 are stacked in sequence from bottom to top between the metal contact 1081 and the first source / drain region 1002, and a metal adhesion layer 1086, a metal barrier layer 1087, and a metal silicide layer 1088 are stacked in sequence from bottom to top between the metal contact 1081 and the first polysilicon contact 1082. The second polysilicon contact 1080 can protect the first source / drain region 1002, the metal adhesion layer 1085 can enhance the adhesion between the metal contact 1081 and the first source / drain region 1002, and prevent the bit line composite contact 108 from having poor contact with the first source / drain region 1002, the metal adhesion layer 1086 can enhance the adhesion between the metal contact 1081 and the first polysilicon contact 1082, and prevent the first polysilicon contact 1082 from having poor contact with the metal contact 1081, and the material of the metal adhesion layers 1085 and 1086 can be a metal such as W, Ti or Ta; the metal barrier layer 1084 can prevent the metal in the metal contact 1081 from diffusing into the first source / drain region 1002, thereby affecting the first source / drain region 1002. The metal barrier layer 1087 can prevent the metal in the metal contact 1081 from diffusing into the first polysilicon contact 102 and affecting the performance of the first polysilicon contact 1082. The materials of the metal barrier layers 1084 and 1087 can be metal nitrides such as TiAlN, TaCN, TaSiN, TiN or TaN; the metal silicide layer 1083 can reduce the contact resistance between the metal contact 1081 and the first source / drain region 1002, and the metal silicide layer 1088 can reduce the contact resistance between the metal contact 1081 and the first polysilicon contact. The metal silicide layers 1083 and 1088 can be metal silicides containing at least one of the metal elements such as Ti, W, Co, Ni, Zr, Mo, Ta, etc.

[0110] A gap is formed between the sidewalls of the bit line composite contact 108 and the gate trench 101 facing each other; a bit line 110 is formed on the bit line composite contact 108, and the bit line 110 and the bit line composite contact 108 are arranged with the same width; the bit line 110 includes a metal silicide layer 1101, a metal barrier layer 1102, a metal adhesion layer 1103 and a bit line metal layer 1104 stacked from bottom to top. The bit line metal layer 1104 may include Al, W, Cu and / or other suitable metal materials; the metal adhesion layer 1103 may enhance the adhesion between the bit line metal layer 1104 and the first polysilicon contact 1082 to prevent the bit line metal layer 1104 from having poor contact with the first polysilicon contact 1082, and the material of the metal adhesion layer 1103 may be a metal such as W, Ti or Ta; the metal barrier layer 1102 may prevent the metal in the bit line metal layer 1104 from diffusing into the first polysilicon contact 1082 and affecting the performance of the first polysilicon contact 1082, and the material of the metal barrier layer 1102 may be a metal nitride such as TiAlN, TaCN, TaSiN, TiN or TaN; the metal silicide layer 1101 may reduce the contact resistance between the first polysilicon contact 1082 and the bit line metal layer 1104, and the metal silicide layer 1101 may be a metal silicide containing at least one of the metal elements such as Ti, W, Co, Ni, Zr, Mo, Ta, etc.

[0111] The semiconductor device of this embodiment further includes an interlayer dielectric layer 111, which covers the gate isolation layer 105, the first source / drain region 1002, the second source / drain region 1003, the bit line 110 and the bit line composite contact 108. The interlayer dielectric layer 111 fills the gap between the sidewalls of the bit line composite contact 108 and buries the bit line 110 and the bit line composite contact 108. A conductive plug 112 is formed in the interlayer dielectric layer 111, and the bottom surface of the conductive plug 112 contacts the top surface of the second source / drain region 1003.

[0112] In one embodiment of the present invention, a plurality of active regions (not shown) are formed in the semiconductor substrate 100, two gate trenches 101 are arranged side by side in each active region, a first source / drain region 1002 is formed in the active region between the two gate trenches 101, and second source / drain regions 1003 are respectively formed in the active regions on the opposite sides of the two gate trenches 101, and the bit line composite contact 108 is formed above the first source / drain region 1002 and has a bottom surface that is adjacent to the first source / drain region 100. 2, the conductive plug 112 is formed above the second source / drain region 1003 and the bottom surface is in contact with the top surface of the second source / drain region 1003, thereby forming two BCATs in one active region, thereby improving the device integration. When the semiconductor device is a memory, the multiple active regions are arranged in an array according to cell rows and cell columns, the gates on each cell row are connected as a word line of the memory, and the bit lines 110 on each cell column are connected as a bit line of the memory.

[0113] In addition, the present invention also provides an electronic device, including the semiconductor device of the present invention. The electronic device of the present invention can be various mobile terminals such as mobile phones, wearable devices, laptop computers, tablet computers, etc., and the wearable devices include smart glasses, head-mounted devices, and wrist-mounted devices such as watches and bracelets.

[0114] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor device, It is characterized in that include: providing a semiconductor substrate having a gate; forming a metal contact on the semiconductor substrate on one side of the gate; forming a first polysilicon contact on the metal contact; as well as, forming a bit line on the first polysilicon contact; The step of forming the metal contact and the first polysilicon contact comprises: Forming a hard mask layer on the semiconductor substrate having the gate, wherein the hard mask layer has an opening exposing a portion of the surface of the semiconductor substrate on one side of the gate; Using the hard mask layer as a mask, etching the semiconductor substrate to form a contact trench; Filling the metal contact in the contact trench, wherein the top surface of the metal contact is lower than the top surface of the hard mask layer, and the bottom surface of the contact trench is higher than the top surface of the gate; filling the first polysilicon contact in the contact trench; Before the metal contact is filled in the contact trench, a second polysilicon contact is first filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.

2. The method for preparing a semiconductor device according to claim 1, It is characterized in that The steps of forming the gate include: Providing a semiconductor substrate, and etching the semiconductor substrate to form a gate trench; forming a gate dielectric layer on the sidewalls and bottom wall of the gate trench; Filling a gate material in the gate trench to form the gate, wherein a top surface of the gate is lower than a top surface of the semiconductor substrate on a sidewall of the gate trench; and, A gate isolation layer is filled in the gate trench, and the gate isolation layer fills up the gate trench to bury the gate therein.

3. The method for preparing a semiconductor device according to claim 2, It is characterized in that The gate is a metal gate, and the gate dielectric layer is a high-K dielectric with a dielectric constant greater than 4; after forming the gate dielectric layer and before filling the gate, a metal barrier layer is formed on the surface of the gate dielectric layer, and after the gate is filled, the metal barrier layer surrounds the bottom wall and side wall of the gate and exposes the surface of the gate dielectric layer above the gate, so that the side wall of the gate isolation layer is directly in contact with the side wall surface of the gate dielectric layer.

4. A method for preparing a semiconductor device according to any one of claims 1 to 3, It is characterized in that The steps of forming the bit line include: forming a sacrificial layer covering the semiconductor substrate and the first polysilicon contact, wherein the sacrificial layer has an opening exposing a portion of a top surface of the first polysilicon contact; filling the bit line in the opening of the sacrificial layer; and, The sacrificial layer is removed, and the first polysilicon contact and the metal contact are sequentially etched to the top interface of the semiconductor substrate using the bit line as a mask, so that the first polysilicon contact and the metal contact have the same width as the bit line.

5. The method for preparing a semiconductor device according to claim 4, It is characterized in that Also includes: forming an interlayer dielectric layer on the semiconductor substrate and the gate, wherein the interlayer dielectric layer buries the bit line; as well as, A conductive plug is formed in the interlayer dielectric layer, wherein a bottom surface of the conductive plug contacts a surface of the semiconductor substrate on the other side of the gate.

6. The method for preparing a semiconductor device according to claim 5, It is characterized in that At least one active area is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active area, each of the gate trenches is filled with the gate, a first source / drain area is formed in the active area between the two gate trenches, and second source / drain areas are formed in the active areas on opposite sides of the two gate trenches, respectively. The metal contact is formed above the first source / drain area and electrically contacts the first source / drain area, and the conductive plug is formed above the second source / drain area and electrically contacts the second source / drain area.

7. A semiconductor device, It is characterized in that include: a semiconductor substrate having a gate; A metal contact is located on the semiconductor substrate on one side of the gate; a first polysilicon contact, stacked on the metal contact; as well as, A bit line stacked on the first polysilicon contact; A contact groove is formed in the semiconductor substrate on one side of the gate, the metal contact is filled in the contact groove, the top surface of the metal contact is not higher than the top surface of the semiconductor substrate on the side wall of the contact groove, and the bottom surface of the contact groove is higher than the top surface of the gate; A second polysilicon contact is filled in the contact trench, and the metal contact is stacked on the second polysilicon contact.

8. The semiconductor device according to claim 7, It is characterized in that A gate trench is formed in the semiconductor substrate, the gate is filled in the gate trench and the top surface is lower than the top surface of the semiconductor substrate on the side wall of the gate trench; the semiconductor device also includes a gate dielectric layer and a gate isolation layer, the gate dielectric layer is formed on the side wall and bottom wall of the gate trench; the gate isolation layer is filled in the gate trench and fills the gate trench to bury the gate therein.

9. The semiconductor device according to claim 7, It is characterized in that Also includes: An interlayer dielectric layer, covering the semiconductor substrate and the gate, wherein the interlayer dielectric layer buries the bit line; as well as, A conductive plug is formed in the interlayer dielectric layer, and a bottom surface of the conductive plug contacts a surface of the semiconductor substrate on the other side of the gate.

10. The semiconductor device according to claim 9, It is characterized in that At least one active area is formed in the semiconductor substrate, two gate trenches are arranged side by side in the active area, each of the gate trenches is filled with the gate, a first source / drain area is formed in the active area between the two gate trenches, and a second source / drain area is formed in the active area on the opposite sides of the two gate trenches, respectively, the metal contact is formed above the first source / drain area and electrically contacts the first source / drain area, the conductive plug is formed above the second source / drain area and electrically contacts the second source / drain area; gaps are formed between the metal contact and the first polysilicon contact and the side walls facing the gate trenches, and the interlayer dielectric layer fills the gaps.

Images