Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a method for preparing the same, belonging to the technical field of integrated circuits. The semiconductor device of the present invention comprises: a substrate; a source electrode formed on one side of the substrate; a drain electrode formed on the other side of the substrate relative to the source electrode; a gate electrode formed on the surface of the substrate; a first isolation structure located on the side of the gate electrode adjacent to the drain electrode and extending downward from the gate electrode to the substrate; a second isolation structure located on the side of the first isolation structure adjacent to the drain electrode and extending downward from the gate electrode to the substrate; the depth of the first isolation structure is different from the depth of the first isolation structure. The present invention reduces the resistance of the region while ensuring the voltage resistance of the semiconductor device, thereby increasing its saturation current.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a semiconductor device and a preparation method thereof. Background Art

[0002] Power semiconductor devices are widely used in the power electronics industry and are one of the basic components of electronic products. In the process of industrial electronic upgrading, they are increasingly valued and applied. In recent years, the call for the Internet of Everything has become louder and louder. Transportation represented by automobiles and high-speed railways, new energy fields represented by photovoltaics and wind power, communication equipment represented by mobile phones, and consumer products represented by televisions, washing machines, air conditioners, and refrigerators are all constantly improving their electronic levels. Among them, the high degree of electronicization of new energy vehicles is the most eye-catching. At the same time, traditional industries such as industry and power grids are also accelerating the process of electronicization. The electronic development of almost all industries is bound to greatly increase the demand for power semiconductor devices.

[0003] High-voltage devices are power semiconductor devices commonly used in high-voltage power integrated circuits. In order to meet the high-voltage resistance requirements, an isolation structure can be buried under the gate, that is, trench isolation technology can be used in the drift region to increase the breakdown voltage of high-voltage devices. Although this method can improve the voltage resistance of high-voltage devices, the addition of isolation structures will increase the on-resistance and reduce the saturation current, thereby reducing the performance of high-voltage devices. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for preparing the same, which solves the problem that the conventional semiconductor device uses trench isolation technology in the drift region to increase the breakdown voltage, but at the same time brings about large on-resistance and reduced performance of the high-voltage device.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a semiconductor device, comprising:

[0007] substrate;

[0008] A source electrode formed on one side of the substrate;

[0009] A drain electrode formed on the other side of the substrate relative to the source electrode;

[0010] A gate formed on the surface of the substrate;

[0011] A first isolation structure, which is located on a side of the gate adjacent to the drain and extends downward from the gate into the substrate;

[0012] A second isolation structure, located on a side of the first isolation structure adjacent to the drain and extending downward from the gate into the substrate;

[0013] The depth of the first isolation structure is different from the depth of the second isolation structure.

[0014] In one embodiment of the present invention, the depth of the first isolation structure is greater than the depth of the second isolation structure.

[0015] In one embodiment of the present invention, the depth of the first isolation structure is greater than the depth of the second isolation structure.

[0016] In one embodiment of the present invention, there is a first preset distance between the first isolation structure and the second isolation structure.

[0017] In one embodiment of the present invention, the first preset spacing is 0-0.12 μm.

[0018] In one embodiment of the present invention, the depth of the first isolation structure is 1 / 3 to 2 / 3 times the depth of the second isolation structure.

[0019] In one embodiment of the present invention, the depth of the first isolation structure is

[0020] In one embodiment of the present invention, the sum of the widths of the first isolation structure and the second isolation structure is 0.15-0.3 μm.

[0021] In one embodiment of the present invention, the gate covers a portion of the second isolation structure.

[0022] The present invention provides a method for preparing a semiconductor device, which at least comprises the following steps:

[0023] providing a substrate;

[0024] forming a first trench and a second trench in the substrate by a first etching;

[0025] Performing a second etching on the first groove or the second groove to obtain a third groove;

[0026] Filling the first trench or the second trench and the third trench with an isolation material to obtain a first isolation structure and a second isolation structure, wherein the depth of the first isolation structure is different from the depth of the second isolation structure;

[0027] forming a gate on the surface of the substrate, wherein the gate covers the first isolation structure and the second isolation structure;

[0028] A source is formed on a side of the gate away from the first isolation structure and the second isolation structure, and a drain is formed on a side of the gate close to the first isolation structure and the second isolation structure.

[0029] The present invention can define the regions of grooves of different depths through photoresist, so as to effectively and reasonably control the distribution of the isolation structure, and by defining the combination of deep and shallow isolation structures, effectively isolate the field effect tubes by using the deep groove isolation structure, and match the shallow groove / deep groove isolation structures with different distributions in the high-voltage area of ​​the field effect tube, so as to provide a certain degree of withstand voltage requirements while reducing the resistance of the region, thereby increasing its saturation current. The present invention can also reduce the width of the existing deep groove isolation structure by etching, so as to provide a certain degree of withstand voltage requirements while reducing the resistance of the region, thereby increasing its saturation current.

[0030] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 is a flow chart of a method for preparing a semiconductor device of the present invention;

[0033] Figure 2-Figure 3 for Figure 1 The structural diagram corresponding to step S2;

[0034] Figure 4-Figure 5 middle Figure 1 The structural diagram corresponding to step S3;

[0035] Figure 6-Figure 8 for Figure 1 The structural diagram corresponding to step S4;

[0036] Figure 9-12 for Figure 1 The structural diagram corresponding to step S5 and step S6;

[0037] Figure 13-Figure 16 It is a schematic diagram of the structures of multiple embodiments of the present invention.

[0038] Reference numerals

[0039] 001 Substrate 002 Source 003 Drain 004 Gate 005 The first isolation structure 006 Second isolation structure 007 Gate oxide 008 First groove 009 Second groove 010 The third groove 011 Pad oxide layer 012 Barrier layer 013 Carbon layer 014 First anti-reflective coating 015 First patterned photoresist layer 016 Second patterned photoresist layer 017 Second anti-reflective coating 018 P-well 019 N-well 020 The third patterned photoresist layer 021 Third anti-reflective coating 022 Fourth patterned photoresist layer 023 Polysilicon layer DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] See also Figures 1 to 16 The present invention provides a semiconductor device, which may include a plurality of field effect transistors, and adjacent field effect transistors are isolated by an isolation structure. The semiconductor device of the present invention includes: a substrate 001, a source 002, a drain 003, a gate 004 located between the source / drain 003, a first isolation structure 005 located on the side of the gate 004 adjacent to the drain 003, and a second isolation structure 006 located on the side of the first isolation structure 005 adjacent to the drain 003, wherein one end of the first isolation structure 005 and one end of the second isolation structure 006 are located in the gate 004 structure, and the other end of the first isolation structure 005 and the other end of the second isolation structure 006 extend into the substrate 001, and the depth of the first isolation structure 005 is different from the depth of the second isolation structure 006, the deeper isolation structure can be named a deep trench isolation structure, and the shallower isolation structure can be named a shallow trench isolation structure, wherein the deep trench isolation structure has the same depth as the conventional isolation structure. The depth of the deep trench isolation structure is, for example, The depth of the shallow trench isolation structure is 1 / 3 to 2 / 3 times the depth of the deep trench isolation structure. In some embodiments, the shallow trench isolation structure is, for example, the first isolation structure 005, and its depth is, for example, 1 / 3 to 2 / 3 times the depth of the second isolation structure 006. The deep trench isolation structure is, for example, the second isolation structure 006, and its depth can be, for example, The sum of the widths of the first isolation structure 005 and the second isolation structure 006 is 0.15 μm-0.3 μm. The depth of the first isolation structure 005 is 1 / 3 times-2 / 3 times the depth of the second isolation structure 006, which can effectively ensure the withstand voltage requirement while reducing the resistance of the region, thereby reducing its saturation current. In some other embodiments, a gate oxide layer 007 is further included between the gate 004 structure and the substrate 001, which is used for insulation between the gate 004 structure and the source / drain 003 and the substrate 001.

[0042] See also Figures 1 to 16Specifically, the substrate 001 may include but is not limited to single crystal or polycrystalline semiconductor materials, and the substrate 001 may also include an intrinsic single crystal silicon substrate 001 or a doped silicon substrate 001. The substrate 001 includes a substrate 001 of a first doping type, and the first doping type may be P-type or N-type. In this embodiment, the first doping type is only taken as an example of P-type, that is, in this embodiment, the substrate 001 is only taken as an example of P-type substrate 001, for example, P-type silicon substrate 001. In some embodiments, the substrate 001 may also be a single crystal silicon substrate 001, a Ge substrate 001, a SiGe substrate 001, a silicon on insulator (Silion On Insulation, SOI) or any combination thereof. According to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 001, which is not limited here. In some embodiments, the substrate 001 may also be composed of a compound semiconductor material, and the compound semiconductor material may be, for example, a III-V semiconductor material or a II-VI semiconductor material. In this embodiment, the substrate 001 used is a P-type semiconductor silicon substrate 001 with a low doping concentration, and then a gate oxide layer 007 is formed on the surface of the P-type semiconductor. In this embodiment, the gate oxide layer 007 is, for example, a silicon dioxide (SiO2) insulating layer. A first isolation structure 005 and a second isolation structure 006 extending into the substrate 001 are formed through the gate oxide layer 007. The other ends of the first isolation structure 005 and the second isolation structure 006 are flush with each other and higher than the gate oxide layer 007 at the same time. The depth of the first isolation structure 005 is different from the depth of the second isolation structure 006. Then, a gate 004 is formed on the substrate 001 by chemical vapor deposition, physical vapor deposition, photolithography and other technologies on the gate oxide layer 007, the first isolation structure 005 and the second isolation structure 006. Two N+ regions with high doping concentrations can be made on the substrate 001 by semiconductor photolithography and diffusion processes, and two electrodes are drawn out by, for example, metal aluminum, which are used as the source 002 and the drain 003 respectively.

[0043] See also Figures 1 to 16In some other embodiments, the same method is used to form a gate oxide layer 007 on a N-type semiconductor silicon substrate 001 with a low doping concentration, and then on the surface of the N-type semiconductor. In this embodiment, the gate oxide layer 007 is, for example, a silicon dioxide (SiO2) insulating layer. A first isolation structure 005 and a second isolation structure 006 extending into the substrate 001 are formed through the gate oxide layer 007. The other ends of the first isolation structure 005 and the second isolation structure 006 are flush with each other and higher than the gate oxide layer 007. The depth of the first isolation structure 005 is different from the depth of the second isolation structure 006. The deeper isolation structure is a deep trench isolation structure, and the shallower isolation structure is a shallow trench isolation structure, wherein the deep trench isolation structure has the same depth as the conventional isolation structure. Then, a gate 004 is formed on the substrate 001 on the gate oxide layer 007, the first isolation structure 005 and the second isolation structure 006 by chemical vapor deposition, physical vapor deposition, photolithography and other technologies. Semiconductor photolithography and diffusion processes can be used to make two P+ regions with high doping concentration on the substrate 001, and two electrodes can be drawn out using, for example, metal aluminum, which serve as the source 002 and the drain 003 respectively.

[0044] See also Figures 1 to 16 In some other embodiments, one end portion of the second isolation structure 006 is located in the gate 004 structure to form a gate 004 field plate, which is beneficial to prevent the device from breaking down prematurely at the edge of the gate 004 and make the electric field distribution smoother. The introduction of the gate 004 field plate structure is equivalent to providing additional negative charges on the channel surface, which has a depletion effect on the electrons in the channel, and can increase the width of the lateral depletion region of the channel. Another peak electric field appears at the edge of the gate 004 field plate, which reduces the electric field peak at the edge of the gate 004, making the distribution of the channel electric field smoother, thereby effectively improving the breakdown voltage of the device.

[0045] See also Figures 1 to 16 In some embodiments, the depth of the first isolation structure 005 may be greater than the depth of the second isolation structure 006, or the depth of the first isolation structure 005 may be less than the depth of the second isolation structure 006. The deeper depth of the first isolation structure 005 or the second isolation structure 006 is equal to the depth of the conventional isolation structure, and the shallower depth of the first isolation structure 005 or the second isolation structure 006 is shallower than the depth of the conventional isolation structure. Under the condition that the sum of the widths of the first isolation structure 005 and the second isolation structure 006 is not greater than that of the conventional isolation structure, the reduction in depth reduces the volume of the isolation structure, so that the device reduces the on-resistance while ensuring the withstand voltage. When the depth of the first isolation structure 005 is greater than / less than the depth of the second isolation structure 006, there is a first preset spacing between the first isolation structure 005 and the second isolation structure 006, and the first preset spacing is, for example, 0-0.12 μm.

[0046] See also Figures 1 to 16 In some other embodiments, the depth of the first isolation structure 005 may be equal to the depth of the second isolation structure 006. When the depth of the first isolation structure 005 is equal to the depth of the second isolation structure 006, the depth of the first isolation structure 005 or the second isolation structure 006 is equal to the depth of the conventional isolation structure. At this time, there is a second preset spacing between the first isolation structure 005 and the second isolation structure 006. The second preset spacing is, for example, 0-0.12μm. At this time, the sum of the widths of the first isolation structure 005 and the second isolation structure 006 is less than the width of the conventional isolation structure. Since the width is reduced, the volume of the isolation structure is reduced, so while maintaining the voltage resistance of the device, the on-resistance is reduced.

[0047] See also Figures 1 to 16 In some other embodiments, multiple field effect transistors can be prepared on the substrate 001 and isolated from each other by a conventional isolation structure to obtain the semiconductor device of the present invention. The depth of the conventional isolation structure is equal to the deeper one of the first isolation structure 005 and the second isolation structure 006. Figure 1 , only one field effect transistor structure is shown in the figure, but those skilled in the art should understand that in order to make the figure clearly express the core idea of ​​the present application, the figure only shows the semiconductor device and structure in the form of a schematic diagram, but this does not mean that the semiconductor device involved in the present invention only includes these parts, and well-known semiconductor device structures and process steps may also be included therein.

[0048] See also Figures 1 to 16 The present invention also provides a method for preparing a semiconductor device, which at least comprises the following steps:

[0049] S1, providing a substrate 001;

[0050] S2, forming a first trench 008 and a second trench 009 in the substrate 001 by a first etching;

[0051] S3, performing a second etching on the first trench 008 or the second trench 009 to obtain a third trench 010;

[0052] S4, filling the first trench 008 or the second trench 009 and the third trench 010 with an isolation material to obtain a first isolation structure 005 and a second isolation structure 006, wherein the depth of the first isolation structure 005 is different from the depth of the second isolation structure 006;

[0053] S5, forming a gate 004 on the surface of the substrate 001, wherein the gate 004 covers the first isolation structure 005 and the second isolation structure 006;

[0054] S6. Form a source 002 on a side of the gate 004 away from the first isolation structure 005 and the second isolation structure 006 by ion implantation, and form a drain 003 on a side of the gate 004 close to the first isolation structure 005 and the second isolation structure 006.

[0055] Combination Figures 1 to 16 , each step of the method for preparing the semiconductor device of the present invention is described in detail.

[0056] See also Figure 1 and Figure 2 In step S1, a substrate 001 is first provided. The substrate 001 may include but is not limited to single crystal or polycrystalline semiconductor materials. The substrate 001 may also include an intrinsic single crystal silicon substrate 001 or a doped silicon substrate 001. The substrate 001 includes a substrate 001 of a first doping type. The first doping type may be P-type or N-type. In this embodiment, the first doping type is only taken as an example of P-type, that is, in this embodiment, the substrate 001 is only taken as an example of P-type substrate 001, for example, P-type silicon substrate 001. In some embodiments, the substrate 001 may also be a single crystal silicon substrate 001, a Ge substrate 001, a SiGe substrate 001, a silicon on insulator (Silion On Insulation, SOI) or any combination thereof. According to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 001, which is not limited here. In some embodiments, the substrate 001 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material. In this embodiment, the selected substrate 001 is a P-type semiconductor silicon substrate 001 with a low doping concentration.

[0057] See also Figure 1 and Figure 2 In step S2, a pad oxide layer 011 is formed on the surface of the substrate 001. The material of the pad oxide layer 011 may be, for example, silicon oxide or silicon oxynitride. During preparation, the pad oxide layer 011 of silicon oxide may be formed by, for example, furnace tube oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods. Silicon oxide may be subjected to a nitridation process to form silicon oxynitride, wherein the nitridation process may be high-temperature furnace tube nitridation, rapid thermal annealing nitridation, plasma nitridation or other nitridation processes.

[0058] See also Figure 1 and Figure 2In step S2, a barrier layer 012 is formed on the surface of the pad oxide layer 011. The pad oxide layer 011 is used to reduce the stress between the substrate 001 and the barrier layer 012, and is also used to form the gate oxide layer 007 later. The barrier layer 012 is used to protect the active area in the subsequent etching process. In this embodiment, the material of the barrier layer 012 may be, for example, silicon nitride. The barrier layer 012 may be formed by, for example, chemical vapor deposition technology during preparation. The chemical vapor deposition technology here may be a low-pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.

[0059] See also Figure 1 and Figure 2 In other embodiments, in step S2, a carbon layer 013 and / or a first anti-reflective coating 014 may be formed on the barrier layer 012 by physical vapor deposition or chemical vapor deposition, which is beneficial to the subsequent photolithography process.

[0060] See also Figures 1 to 3 In step S2, a first patterned photoresist layer 015 is formed on the blocking layer 012, the first patterned photoresist layer 015 exposes a portion of the blocking layer 012, and the positions of the first groove 008 and the second groove 009 are defined by the first patterned photoresist layer 015. The first etching is performed corresponding to the positions defined by the first patterned photoresist layer 015 to obtain the first groove 008 and the second groove 009. In this embodiment, the first etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, the blocking layer 012 and the pad oxide layer 011 are sequentially etched by a reactive ion etching or plasma etching process to expose the surface material of the substrate 001, and then the substrate 001 is etched by using a fluorine-containing etching gas with the blocking layer 012 and the pad oxide layer 011 as a mask, so as to form the first groove 008 and the second groove 009 extending into the substrate 001, and a first preset spacing is set between the first groove 008 and the second groove 009, and the first preset spacing is, for example, 0-0.12 μm.

[0061] See also Figures 1 to 3In step S2, in some embodiments, a photoresist layer may be formed on the barrier layer 012 by, for example, spin coating, and after exposure and development processes, an opening is formed on the photoresist layer to obtain a first patterned photoresist layer 015. The first patterned photoresist layer 015 is used as a mask to remove the barrier layer 012 and the pad oxide layer 011 under the opening pattern until the substrate 001 is exposed. Then, the photoresist layer may be removed by wet cleaning, and then the barrier layer 012 and the pad oxide layer 011 are used as masks to etch the substrate 001 by dry etching until the first trench 008 and the second trench 009 are formed in the substrate 001. The first groove 008 and the second groove 009 penetrate the pad oxide layer 011 and the barrier layer 012 and extend into the substrate 001. In some embodiments, a first anti-reflection coating 014 may be further provided on the barrier layer 012 to reduce the reflection of the etching beam and remove the anti-reflection coating by wet cleaning after etching.

[0062] See also Figures 3 to 5 In step S3, one of the grooves is shielded, and the other groove is etched for a second time to obtain a third groove 010. On the basis of step S2, a second patterned photoresist layer 016 is formed on the blocking layer 012. In this process, the second patterned photoresist layer 016 fills the first groove 008 and the second groove 009. The position of the third groove 010 is defined by the second patterned photoresist layer 016. The defined position of the third groove 010 can correspond to the position of the original first groove 008 or the second groove 009. The substrate 001 is etched for a second time downward along the original first groove 008 or the second groove 009 to obtain the third groove 010. In this embodiment, a second etching can be performed, for example, using a reactive ion etching or plasma etching process, that is, etching downward along the original first groove 008 or the second groove 009 by a reactive ion etching or plasma etching process to obtain a third groove 010, and the depth of the third groove 010 is different from the depth of the first groove 008 or the second groove 009.

[0063] See also Figures 3 to 5In step S3, in some embodiments, a photoresist layer can be formed on the barrier layer 012 by, for example, a spin coating method, and the photoresist layer fills the first groove 008 and the second groove 009. After exposure and development processes, an opening is formed on the photoresist layer to obtain a second patterned photoresist layer 016. The position of the third groove 010 is defined by the second patterned photoresist layer 016. The position of the defined third groove 010 can correspond to the position of the original first groove 008 or the second groove 009. The second patterned photoresist layer 016 is used as a mask to remove the substrate 001 under the opening pattern, that is, the substrate 001 is etched downward for a second time along the original first groove 008 or the second groove 009 to obtain the third groove 010, and then the remaining photoresist layer can be removed by wet cleaning.

[0064] See also Figures 3 to 5 In step S3, in some embodiments, based on step S2, a second anti-reflection coating 017 and a second patterned photoresist layer 016 may be sequentially formed on the barrier layer 012, the second anti-reflection coating 017 fills the first groove 008 and the second groove 009, the second patterned photoresist layer 016 defines the position of the third groove 010, the position of the defined third groove 010 may correspond to the position of the original first groove 008 or the second groove 009, and the second anti-reflection coating 017 and the substrate 001 are etched downward along the original first groove 008 or the second groove 009 for a second time to obtain the third groove 010. In this embodiment, the second etching may be performed, for example, by using a reactive ion etching or plasma etching process, that is, etching is performed downward along the original first groove 008 or the second groove 009 by using a reactive ion etching or plasma etching process to obtain the third groove 010. In this embodiment, specifically, the substrate 001 is etched downward along the original second trench 009 by reactive ion etching or plasma etching process to obtain the third trench 010 .

[0065] See also Figures 3 to 5In step S3, in some embodiments, a second anti-reflective coating 017 and a photoresist layer may be sequentially formed on the barrier layer 012 by, for example, a spin coating method, the second anti-reflective coating 017 fills the first groove 008 and the second groove 009, and after exposure and development processes, an opening is formed on the photoresist layer to obtain a second patterned photoresist layer 016, and the position of the third groove 010 is defined by the second patterned photoresist layer 016, and the position of the defined third groove 010 may correspond to the position of the original first groove 008 or the second groove 009, and the second patterned photoresist layer 016 is used as a mask to remove the second anti-reflective coating 017 and the substrate 001 under the opening pattern, that is, the second anti-reflective coating 017 and the substrate 001 are etched downward along the original first groove 008 or the second groove 009 for a second time to obtain the third groove 010, and then the second anti-reflective coating 017 and the photoresist layer may be removed by wet cleaning.

[0066] See also Figures 6 to 16 In step S4, an isolation material is filled in the first trench 008 or the second trench 009 and the third trench 010 to obtain a first isolation structure 005 and a second isolation structure 006. An isolation material is deposited on the barrier layer 012 by high-density plasma chemical vapor deposition to fill the first trench 008 or the second trench 009 and the third trench 010, and then, for example, chemical mechanical polishing is performed to make the upper surface of the isolation material in the first trench 008 or the second trench 009 and the third trench 010 flush with the upper surface of the barrier layer 012, and the barrier layer 012 is removed by dry or wet etching to expose the pad oxide layer 011 to form the first isolation structure 005 and the second isolation structure 006. The depth of the first isolation structure 005 is The depth of the second isolation structure 006 is different. Specifically, the depth of the first isolation structure 005 can be deeper than the depth of the second isolation structure 006, or the depth of the first isolation structure 005 can be shallower than the depth of the second isolation structure 006. There is a first preset spacing between the first isolation structure 005 and the second isolation structure 006. The first preset spacing is, for example, 0-0.12 μm. The deeper isolation structure can be named a deep trench isolation structure, and the shallower isolation structure can be named a shallow trench isolation structure. The deep trench isolation structure has the same depth as the conventional isolation structure. The depth of the deep trench isolation structure is, for example, The depth of the shallow trench isolation structure is 1 / 3 to 2 / 3 times the depth of the deep trench isolation structure. In some embodiments, the shallow trench isolation structure is, for example, the first isolation structure 005, and its depth is, for example, 1 / 3 to 2 / 3 times the depth of the second isolation structure 006. The deep trench isolation structure is, for example, the second isolation structure 006, and its depth can be, for example, The sum of the widths of the first isolation structure 005 and the second isolation structure 006 is 0.15μm-0.3μm. Under the condition that the sum of the widths of the first isolation structure 005 and the second isolation structure 006 is kept not greater than that of the conventional isolation structure, the reduction in depth reduces the volume of the isolation structure, so that the device reduces the on-resistance while ensuring the voltage resistance, that is, it can effectively ensure the voltage resistance requirement while reducing the resistance of the region, thereby reducing its saturation current. In this embodiment, for example, a wet etching method is used to remove the barrier layer 012, and the wet etching reagent is, for example, phosphoric acid or hydrofluoric acid. In this embodiment, the isolation material is, for example, silicon oxide, silicon nitride or silicon oxynitride.

[0067] See also Figures 6 to 16 In some other embodiments, the depth of the first isolation structure 005 is the same as the depth of the second isolation structure 006, that is, the depth of the first isolation structure 005 is equal to the depth of the second isolation structure 006, and the depth of the first isolation structure 005 and the depth of the second isolation structure 006 are equal to the depth of the conventional isolation structure. When the depth of the first isolation structure 005 is equal to the depth of the second isolation structure 006, a second preset spacing is provided between the first isolation structure 005 and the second isolation structure 006, and the second preset spacing is, for example, 0-0.12 μm. The sum of the widths of the first isolation structure 005 and the second isolation structure 006 is less than the width of the conventional isolation structure. Since the width is reduced, the volume of the isolation structure is reduced, so while maintaining the voltage resistance of the device, the on-resistance is reduced. In this embodiment, the first trench 008 corresponding to the first isolation structure 005 and the third trench 010 corresponding to the second isolation structure 006 can be completed simultaneously by a single etching process.

[0068] See also Fig. 9 In step S4, after removing the barrier layer 012, different types of ion implantation are performed on different regions of the substrate 001. For example, a P well 018 is formed on one side of a region of the substrate 001 corresponding to a field effect transistor shown in the figure, and an N well 019 is formed on the other side. The ion implantation source used is preferably a phosphorus source, a boron source or a fluorine source.

[0069] See also Fig. 9 In step S5, a third patterned photoresist layer 020 is formed on the surface of the pad oxide layer 011, and the third patterned photoresist layer 020 exposes a portion of the pad oxide layer 011. The third patterned photoresist layer 020 defines the position of the gate oxide layer 007, and a third etching is performed corresponding to the position defined by the third patterned photoresist layer 020 to obtain the gate oxide layer 007. In this embodiment, the third etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, the pad oxide layer 011 is etched by a reactive ion etching or plasma etching process to expose the surface material of the substrate 001, and the remaining pad oxide layer 011 forms the gate oxide layer 007.

[0070] See also Fig. 9 In step S5, in some embodiments, a photoresist layer can be formed on the pad oxide layer 011 by, for example, a spin coating method. After exposure and development processes, an opening is formed on the photoresist layer to obtain a third patterned photoresist layer 020. The position of the gate oxide layer 007 is defined by the third patterned photoresist layer 020. The pad oxide layer 011 is etched by a reactive ion etching or plasma etching process to expose the surface material of the substrate 001. The remaining pad oxide layer 011 after etching forms a gate oxide layer 007. Then, the photoresist layer can be removed by wet cleaning.

[0071] See also Fig. 9 In step S5, in some embodiments, on the basis of step S4, a third anti-reflective coating 021 and a third patterned photoresist layer 020 are sequentially formed on the surface of the pad oxide layer 011, the third patterned photoresist layer 020 exposes a portion of the third anti-reflective coating 021, the position of the gate oxide layer 007 is defined by the third patterned photoresist layer 020, and the third etching is performed corresponding to the position defined by the third patterned photoresist layer 020 to obtain the gate oxide layer 007. In this embodiment, the third etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, the third anti-reflective coating 021 and the pad oxide layer 011 are etched by a reactive ion etching or plasma etching process to expose the surface material of the substrate 001, and then the third anti-reflective coating 021 and the remaining third patterned photoresist layer 020 can be removed by wet cleaning, and the remaining pad oxide layer 011 after etching forms the gate oxide layer 007.

[0072] See also Fig.10 In step S5, a polysilicon layer 023 is deposited on the substrate 001, the gate oxide layer 007, the first isolation structure 005 and the second isolation structure 006, and the polysilicon layer 023 covers the surfaces of the substrate 001, the gate oxide layer 007, the first isolation structure 005 and the second isolation structure 006, and then the deposited polysilicon layer 023 is planarized. The above-mentioned deposition process and planarization process are preferably carried out by conventional techniques in the art, such as using a chemical mechanical planarization method to planarize the polysilicon layer 023.

[0073] See also Fig.11 and Fig.12In step S5, a fourth patterned photoresist layer 022 is formed on the surface of the polysilicon layer 023, the fourth patterned photoresist layer 022 exposes a portion of the polysilicon layer 023, the fourth patterned photoresist layer 022 defines the position of the gate 004, and the fourth etching is performed corresponding to the position defined by the fourth patterned photoresist layer 022 to obtain the gate 004. In this embodiment, the fourth etching can be performed, for example, by using a reactive ion etching or plasma etching process, that is, the polysilicon layer 023 is etched by a reactive ion etching or plasma etching process, the polysilicon layer 023 corresponding to the pattern position of the fourth patterned photoresist layer 022 is etched away, and then the fourth patterned photoresist layer 022 is removed, so as to obtain the gate 004.

[0074] See also Fig.11 In step S5, in some embodiments, a photoresist layer can be formed on the polysilicon layer 023 by, for example, a spin coating method. After exposure and development processes, an opening is formed on the photoresist layer to obtain a fourth patterned photoresist layer 022. The position of the gate 004 is defined by the fourth patterned photoresist layer 022. The polysilicon layer 023 is etched by a reactive ion etching or plasma etching process to expose the surface material of the substrate 001. The remaining pad oxide layer 011 after etching forms a gate oxide layer 007. The polysilicon layer 023 corresponding to the pattern position of the fourth patterned photoresist layer 022 is etched away, and then the photoresist layer can be removed by wet cleaning.

[0075] See also Fig.12 In step S6, a source 002 is formed on a side of the gate 004 away from the first isolation structure 005 and the second isolation structure 006 by ion implantation, and a drain 003 is formed on a side of the gate 004 close to the first isolation structure 005 and the second isolation structure 006.

[0076] See also Figures 1 to 16 The present invention utilizes the first etching to form an isolation structure with a shallower groove, namely the shallow groove isolation structure, and then utilizes the second etching to form an isolation structure with a deeper groove, namely the deep groove isolation structure, wherein the depth of the deep groove isolation structure is equal to that of the conventional groove isolation structure, and the deep groove isolation structure is formed by performing a second precise etching in the original shallow groove isolation structure area. The distribution of the deep and shallow groove isolation structures can be effectively and reasonably controlled by etching twice to form areas with grooves of different depths. Through the combination of the deep and shallow groove isolation structures, the deep groove isolation structure is used to effectively isolate the field effect transistors, and the shallow groove / deep groove isolation structures with different distributions are matched in the high-voltage area of ​​the field effect transistor. This process method can reasonably control the distribution of the deep and shallow grooves, thereby achieving the purpose of reducing the resistance of the area and reducing the on-resistance while ensuring the voltage resistance of the device, thereby increasing its saturation current.

[0077] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for preparing a semiconductor device, characterized in that: It at least includes the following steps: providing a substrate; forming a first trench and a second trench in the substrate by a first etching; Performing a second etching on the first groove or the second groove to obtain a third groove; Filling the first trench or the second trench and the third trench with an isolation material to obtain a first isolation structure and a second isolation structure, wherein the depth of the first isolation structure is different from the depth of the first isolation structure; the sum of the widths of the first isolation structure and the second isolation structure is 0.15µm-0.3µm, and the sum of the widths of the first isolation structure and the second isolation structure is not greater than that of a conventional isolation structure; the deeper depth of the first isolation structure or the second isolation structure is equal to the depth of a conventional isolation structure, and the shallower depth of the first isolation structure or the second isolation structure is shallower than the depth of a conventional isolation structure, and a conventional isolation structure is arranged between field effect transistors for isolation; the depth of the conventional isolation structure is 4000Å-5000Å; forming a gate on the surface of the substrate, wherein the gate covers the first isolation structure and the second isolation structure, and the gate covers a portion of the second isolation structure; A source electrode is formed on a side of the gate away from the first isolation structure and the second isolation structure, and a drain electrode is formed on a side of the gate close to the first isolation structure and the second isolation structure; Wherein, the preparation method further comprises: forming a pad oxide layer and a barrier layer, a carbon layer and a first anti-reflection coating in sequence on the substrate; Forming a first groove and a second groove by a first etching, and performing a second etching on the first groove or the second groove to obtain a third groove; Fill the first trench or the second trench and the third trench with an isolation material, flatten the isolation material, make the upper surface of the isolation material flush with the upper surface of the barrier layer, remove the barrier layer, and obtain a first isolation structure and a second isolation structure; etch the pad oxide layer, and make the remaining pad oxide layer a gate oxide layer, and the first isolation structure and the second isolation structure protrude from the gate oxide layer.

2. A method for preparing a semiconductor device according to claim 1, characterized in that: The depth of the first isolation structure is greater than the depth of the second isolation structure.

3. A method for preparing a semiconductor device according to claim 1, characterized in that: The depth of the second isolation structure is greater than the depth of the first isolation structure.

4. A method for preparing a semiconductor device according to claim 2 or 3, characterized in that: There is a first preset distance between the first isolation structure and the second isolation structure.

5. A method for preparing a semiconductor device according to claim 4, characterized in that: The first preset spacing is 0-0.12µm.

6. The method for preparing a semiconductor device according to claim 1, characterized in that: The depth of the first isolation structure is 1 / 3 to 2 / 3 times the depth of the second isolation structure.

7. A method for preparing a semiconductor device according to claim 1, characterized in that: The depth of the first isolation structure is 4000Å-5000Å.

Images